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Sparc: convert interrupt helpers to trace framework

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Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2011-09-11 15:05:41 +00:00
parent ec0ceb1759
commit 11e66bca8a
3 changed files with 23 additions and 26 deletions
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13
target-sparc/int32_helper.c
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@ -18,16 +18,9 @@
*/ */
#include "cpu.h" #include "cpu.h"
#include "trace.h"
//#define DEBUG_PCALL //#define DEBUG_PCALL
//#define DEBUG_CACHE_CONTROL
#ifdef DEBUG_CACHE_CONTROL
#define DPRINTF_CACHE_CONTROL(fmt, ...) \
do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
#endif
#ifdef DEBUG_PCALL #ifdef DEBUG_PCALL
static const char * const excp_names[0x80] = { static const char * const excp_names[0x80] = {
@ -142,7 +135,7 @@ static void leon3_cache_control_int(CPUState *env)
state = env->cache_control & CACHE_STATE_MASK; state = env->cache_control & CACHE_STATE_MASK;
if (state == CACHE_ENABLED) { if (state == CACHE_ENABLED) {
state = CACHE_FROZEN; state = CACHE_FROZEN;
DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n"); trace_int_helper_icache_freeze();
} }
env->cache_control &= ~CACHE_STATE_MASK; env->cache_control &= ~CACHE_STATE_MASK;
@ -154,7 +147,7 @@ static void leon3_cache_control_int(CPUState *env)
state = (env->cache_control >> 2) & CACHE_STATE_MASK; state = (env->cache_control >> 2) & CACHE_STATE_MASK;
if (state == CACHE_ENABLED) { if (state == CACHE_ENABLED) {
state = CACHE_FROZEN; state = CACHE_FROZEN;
DPRINTF_CACHE_CONTROL("Data cache: freeze\n"); trace_int_helper_dcache_freeze();
} }
env->cache_control &= ~(CACHE_STATE_MASK << 2); env->cache_control &= ~(CACHE_STATE_MASK << 2);

29
target-sparc/int64_helper.c
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@ -19,16 +19,9 @@
#include "cpu.h" #include "cpu.h"
#include "helper.h" #include "helper.h"
#include "trace.h"
//#define DEBUG_PCALL //#define DEBUG_PCALL
//#define DEBUG_PSTATE
#ifdef DEBUG_PSTATE
#define DPRINTF_PSTATE(fmt, ...) \
do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF_PSTATE(fmt, ...) do {} while (0)
#endif
#ifdef DEBUG_PCALL #ifdef DEBUG_PCALL
static const char * const excp_names[0x80] = { static const char * const excp_names[0x80] = {
@ -172,33 +165,37 @@ trap_state *cpu_tsptr(CPUState* env)
return &env->ts[env->tl & MAXTL_MASK]; return &env->ts[env->tl & MAXTL_MASK];
} }
static void do_modify_softint(CPUState *env, const char *operation, static bool do_modify_softint(CPUState *env, uint32_t value)
uint32_t value)
{ {
if (env->softint != value) { if (env->softint != value) {
env->softint = value; env->softint = value;
DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint);
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
if (cpu_interrupts_enabled(env)) { if (cpu_interrupts_enabled(env)) {
cpu_check_irqs(env); cpu_check_irqs(env);
} }
#endif #endif
return true;
} }
return false;
} }
void helper_set_softint(CPUState *env, uint64_t value) void helper_set_softint(CPUState *env, uint64_t value)
{ {
do_modify_softint(env, "helper_set_softint", if (do_modify_softint(env, env->softint | (uint32_t)value)) {
env->softint | (uint32_t)value); trace_int_helper_set_softint(env->softint);
}
} }
void helper_clear_softint(CPUState *env, uint64_t value) void helper_clear_softint(CPUState *env, uint64_t value)
{ {
do_modify_softint(env, "helper_clear_softint", if (do_modify_softint(env, env->softint & (uint32_t)~value)) {
env->softint & (uint32_t)~value); trace_int_helper_clear_softint(env->softint);
}
} }
void helper_write_softint(CPUState *env, uint64_t value) void helper_write_softint(CPUState *env, uint64_t value)
{ {
do_modify_softint(env, "helper_write_softint", (uint32_t)value); if (do_modify_softint(env, (uint32_t)value)) {
trace_int_helper_write_softint(env->softint);
}
} }

7
trace-events
View File

@ -609,3 +609,10 @@ mmu_helper_tmiss(uint64_t address, uint64_t context) "TMISS at %"PRIx64" context
mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64"" mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64""
mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64"" mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64""
mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at %"PRIx64" -> %"PRIx64", mmu_idx=%d tl=%d primary context=%"PRIx64" secondary context=%"PRIx64"" mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at %"PRIx64" -> %"PRIx64", mmu_idx=%d tl=%d primary context=%"PRIx64" secondary context=%"PRIx64""
# target-sparc/int_helper.c
int_helper_set_softint(uint32_t softint) "new %08x"
int_helper_clear_softint(uint32_t softint) "new %08x"
int_helper_write_softint(uint32_t softint) "new %08x"
int_helper_icache_freeze(void) "Instruction cache: freeze"
int_helper_dcache_freeze(void) "Data cache: freeze"