MIPS Magnum R4000 machine
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4164 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32
parent
b60aee0027
commit
4ce7ff6e68
@ -559,14 +559,14 @@ OBJS+= unin_pci.o ppc_chrp.o
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OBJS+= pflash_cfi02.o ppc4xx_devs.o ppc405_uc.o ppc405_boards.o
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endif
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ifeq ($(TARGET_BASE_ARCH), mips)
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OBJS+= mips_r4k.o mips_malta.o mips_pica61.o mips_mipssim.o
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OBJS+= mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o
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OBJS+= jazz_led.o
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OBJS+= mips_r4k.o mips_jazz.o mips_malta.o mips_pica61.o mips_mipssim.o
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OBJS+= mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o rc4030.o
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OBJS+= g364fb.o jazz_led.o
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OBJS+= ide.o gt64xxx.o pckbd.o ps2.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
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OBJS+= piix_pci.o parallel.o cirrus_vga.o $(SOUND_HW)
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OBJS+= piix_pci.o parallel.o cirrus_vga.o pcspk.o $(SOUND_HW)
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OBJS+= mipsnet.o
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OBJS+= pflash_cfi01.o
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CPPFLAGS += -DHAS_AUDIO
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CPPFLAGS += -DHAS_AUDIO -DHAS_AUDIO_CHOICE
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endif
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ifeq ($(TARGET_BASE_ARCH), cris)
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OBJS+= etraxfs.o
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@ -36,6 +36,9 @@ extern QEMUMachine taihu_machine;
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/* mips_r4k.c */
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extern QEMUMachine mips_machine;
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/* mips_jazz.c */
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extern QEMUMachine mips_magnum_machine;
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/* mips_malta.c */
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extern QEMUMachine mips_malta_machine;
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@ -9,6 +9,11 @@ PCIBus *pci_gt64120_init(qemu_irq *pic);
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void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
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void ds1225y_set_protection(void *opaque, int protection);
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/* g364fb.c */
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int g364fb_mm_init(DisplayState *ds,
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int vram_size, int it_shift,
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target_phys_addr_t vram_base, target_phys_addr_t ctrl_base);
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/* mipsnet.c */
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void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
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@ -22,4 +27,7 @@ extern void cpu_mips_irq_init_cpu(CPUState *env);
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extern void cpu_mips_clock_init(CPUState *);
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extern void cpu_mips_irqctrl_init (void);
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/* rc4030.c */
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qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus);
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#endif
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275
hw/mips_jazz.c
Normal file
275
hw/mips_jazz.c
Normal file
@ -0,0 +1,275 @@
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/*
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* QEMU MIPS Jazz support
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*
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* Copyright (c) 2007-2008 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "mips.h"
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#include "pc.h"
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#include "isa.h"
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#include "fdc.h"
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#include "sysemu.h"
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#include "audio/audio.h"
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#include "boards.h"
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#include "net.h"
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#include "scsi.h"
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extern int nographic;
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#ifdef TARGET_WORDS_BIGENDIAN
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#define BIOS_FILENAME "mips_bios.bin"
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#else
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#define BIOS_FILENAME "mipsel_bios.bin"
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#endif
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#ifdef TARGET_MIPS64
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#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL)
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#else
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#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU)
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#endif
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#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
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enum jazz_model_e
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{
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JAZZ_MAGNUM,
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};
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static void main_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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cpu_reset(env);
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}
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static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
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{
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CPUState *env = opaque;
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return cpu_inw(env, 0x71);
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}
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static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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CPUState *env = opaque;
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cpu_outw(env, 0x71, val & 0xff);
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}
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static CPUReadMemoryFunc *rtc_read[3] = {
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rtc_readb,
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rtc_readb,
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rtc_readb,
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};
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static CPUWriteMemoryFunc *rtc_write[3] = {
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rtc_writeb,
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rtc_writeb,
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rtc_writeb,
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};
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#ifdef HAS_AUDIO
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static void audio_init(qemu_irq *pic)
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{
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struct soundhw *c;
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int audio_enabled = 0;
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for (c = soundhw; !audio_enabled && c->name; ++c) {
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audio_enabled = c->enabled;
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}
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if (audio_enabled) {
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AudioState *s;
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s = AUD_init();
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if (s) {
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for (c = soundhw; c->name; ++c) {
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if (c->enabled) {
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if (c->isa) {
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c->init.init_isa(s, pic);
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}
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}
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}
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}
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}
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}
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#endif
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void espdma_memory_read(void *opaque, uint8_t *buf, int len)
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{
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printf("espdma_memory_read(buf %p, len %d) not implemented\n", buf, len);
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}
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void espdma_memory_write(void *opaque, uint8_t *buf, int len)
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{
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printf("espdma_memory_write(buf %p, len %d) not implemented\n", buf, len);
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}
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#define MAGNUM_BIOS_SIZE_MAX 0x7e000
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#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
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static
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void mips_jazz_init (int ram_size, int vga_ram_size,
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DisplayState *ds, const char *cpu_model,
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enum jazz_model_e jazz_model)
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{
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char buf[1024];
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unsigned long bios_offset;
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int bios_size, n;
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CPUState *env;
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qemu_irq *rc4030, *i8259;
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void *scsi_hba;
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int hd;
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int s_rtc;
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PITState *pit;
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BlockDriverState *fds[MAX_FD];
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qemu_irq esp_reset;
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/* init CPUs */
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if (cpu_model == NULL) {
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#ifdef TARGET_MIPS64
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cpu_model = "R4000";
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#else
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/* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
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cpu_model = "24Kf";
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#endif
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}
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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/* load the BIOS image. */
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bios_offset = ram_size + vga_ram_size;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
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bios_size = load_image(buf, phys_ram_base + bios_offset);
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if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
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fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
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buf);
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exit(1);
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}
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cpu_register_physical_memory(0x1fc00000LL,
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MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
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cpu_register_physical_memory(0xfff00000LL,
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MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
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/* Init CPU internal devices */
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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/* Chipset */
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rc4030 = rc4030_init(env->irq[6], env->irq[3]);
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/* ISA devices */
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i8259 = i8259_init(env->irq[4]);
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pit = pit_init(0x40, i8259[0]);
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pcspk_init(pit);
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/* ISA IO space at 0x90000000 */
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isa_mmio_init(0x90000000, 0x01000000);
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isa_mem_base = 0x11000000;
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/* Video card */
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switch (jazz_model) {
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case JAZZ_MAGNUM:
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g364fb_mm_init(ds, vga_ram_size, 0, 0x40000000, 0x60000000);
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break;
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default:
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break;
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}
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/* Network controller */
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/* FIXME: missing NS SONIC DP83932 */
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/* SCSI adapter */
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scsi_hba = esp_init(0x80002000,
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espdma_memory_read, espdma_memory_write, NULL,
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rc4030[5], &esp_reset);
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for (n = 0; n < ESP_MAX_DEVS; n++) {
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hd = drive_get_index(IF_SCSI, 0, n);
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if (hd != -1) {
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esp_scsi_attach(scsi_hba, drives_table[hd].bdrv, n);
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}
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}
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/* Floppy */
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if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
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fprintf(stderr, "qemu: too many floppy drives\n");
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exit(1);
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}
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for (n = 0; n < MAX_FD; n++) {
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int fd = drive_get_index(IF_FLOPPY, 0, n);
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if (fd != -1)
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fds[n] = drives_table[fd].bdrv;
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else
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fds[n] = NULL;
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}
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fdctrl_init(rc4030[1], 0, 1, 0x80003000, fds);
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/* Real time clock */
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rtc_init(0x70, i8259[8]);
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s_rtc = cpu_register_io_memory(0, rtc_read, rtc_write, env);
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cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
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/* Keyboard (i8042) */
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i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0);
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/* Serial ports */
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if (serial_hds[0])
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serial_mm_init(0x80006000, 0, rc4030[8], serial_hds[0], 1);
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if (serial_hds[1])
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serial_mm_init(0x80007000, 0, rc4030[9], serial_hds[1], 1);
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/* Parallel port */
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if (parallel_hds[0])
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parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
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/* Sound card */
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/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
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#ifdef HAS_AUDIO
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audio_init(i8259);
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#endif
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/* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
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ds1225y_init(0x80009000, "nvram");
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/* LED indicator */
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jazz_led_init(ds, 0x8000f000);
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}
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static
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void mips_magnum_init (int ram_size, int vga_ram_size,
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const char *boot_device, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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mips_jazz_init(ram_size, vga_ram_size, ds, cpu_model, JAZZ_MAGNUM);
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}
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QEMUMachine mips_magnum_machine = {
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"magnum",
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"MIPS Magnum",
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mips_magnum_init,
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};
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608
hw/rc4030.c
Normal file
608
hw/rc4030.c
Normal file
@ -0,0 +1,608 @@
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/*
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* QEMU JAZZ RC4030 chipset
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*
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* Copyright (c) 2007-2008 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
|
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* in the Software without restriction, including without limitation the rights
|
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
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* THE SOFTWARE.
|
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*/
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#include "hw.h"
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#include "qemu-timer.h"
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//#define DEBUG_RC4030
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#ifdef DEBUG_RC4030
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static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
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"network", "scsi", "keyboard", "mouse", "serial0", "serial1" };
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#endif
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typedef struct rc4030State
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{
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uint32_t config; /* 0x0000: RC4030 config register */
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uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
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/* DMA */
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uint32_t dma_regs[8][4];
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uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
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uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
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/* cache */
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uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
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uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
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uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
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uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
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uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
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uint32_t cache_bwin; /* 0x0060: I/O Cache Buffer Window */
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uint32_t offset208;
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uint32_t offset210;
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uint32_t nvram_protect; /* 0x0220: NV ram protect register */
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uint32_t offset238;
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uint32_t rem_speed[15];
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uint32_t imr_jazz; /* Local bus int enable mask */
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uint32_t isr_jazz; /* Local bus int source */
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/* timer */
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QEMUTimer *periodic_timer;
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uint32_t itr; /* Interval timer reload */
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uint32_t dummy32;
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qemu_irq timer_irq;
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qemu_irq jazz_bus_irq;
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} rc4030State;
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static void set_next_tick(rc4030State *s)
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{
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qemu_irq_lower(s->timer_irq);
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uint32_t hz;
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hz = 1000 / (s->itr + 1);
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qemu_mod_timer(s->periodic_timer, qemu_get_clock(vm_clock) + ticks_per_sec / hz);
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}
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/* called for accesses to rc4030 */
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static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
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{
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rc4030State *s = opaque;
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uint32_t val;
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addr &= 0x3fff;
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switch (addr & ~0x3) {
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/* Global config register */
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case 0x0000:
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val = s->config;
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break;
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/* Invalid Address register */
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case 0x0010:
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val = s->invalid_address_register;
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break;
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/* DMA transl. table base */
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case 0x0018:
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val = s->dma_tl_base;
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break;
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/* DMA transl. table limit */
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case 0x0020:
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val = s->dma_tl_limit;
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break;
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/* Remote Failed Address */
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case 0x0038:
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val = s->remote_failed_address;
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break;
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/* Memory Failed Address */
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case 0x0040:
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val = s->memory_failed_address;
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break;
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/* I/O Cache Byte Mask */
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case 0x0058:
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val = s->cache_bmask;
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/* HACK */
|
||||
if (s->cache_bmask == (uint32_t)-1)
|
||||
s->cache_bmask = 0;
|
||||
break;
|
||||
/* Remote Speed Registers */
|
||||
case 0x0070:
|
||||
case 0x0078:
|
||||
case 0x0080:
|
||||
case 0x0088:
|
||||
case 0x0090:
|
||||
case 0x0098:
|
||||
case 0x00a0:
|
||||
case 0x00a8:
|
||||
case 0x00b0:
|
||||
case 0x00b8:
|
||||
case 0x00c0:
|
||||
case 0x00c8:
|
||||
case 0x00d0:
|
||||
case 0x00d8:
|
||||
case 0x00e0:
|
||||
val = s->rem_speed[(addr - 0x0070) >> 3];
|
||||
break;
|
||||
/* DMA channel base address */
|
||||
case 0x0100:
|
||||
case 0x0108:
|
||||
case 0x0110:
|
||||
case 0x0118:
|
||||
case 0x0120:
|
||||
case 0x0128:
|
||||
case 0x0130:
|
||||
case 0x0138:
|
||||
case 0x0140:
|
||||
case 0x0148:
|
||||
case 0x0150:
|
||||
case 0x0158:
|
||||
case 0x0160:
|
||||
case 0x0168:
|
||||
case 0x0170:
|
||||
case 0x0178:
|
||||
case 0x0180:
|
||||
case 0x0188:
|
||||
case 0x0190:
|
||||
case 0x0198:
|
||||
case 0x01a0:
|
||||
case 0x01a8:
|
||||
case 0x01b0:
|
||||
case 0x01b8:
|
||||
case 0x01c0:
|
||||
case 0x01c8:
|
||||
case 0x01d0:
|
||||
case 0x01d8:
|
||||
case 0x01e0:
|
||||
case 0x1e8:
|
||||
case 0x01f0:
|
||||
case 0x01f8:
|
||||
{
|
||||
int entry = (addr - 0x0100) >> 5;
|
||||
int idx = (addr & 0x1f) >> 3;
|
||||
val = s->dma_regs[entry][idx];
|
||||
}
|
||||
break;
|
||||
/* Offset 0x0208 */
|
||||
case 0x0208:
|
||||
val = s->offset208;
|
||||
break;
|
||||
/* Offset 0x0210 */
|
||||
case 0x0210:
|
||||
val = s->offset210;
|
||||
break;
|
||||
/* NV ram protect register */
|
||||
case 0x0220:
|
||||
val = s->nvram_protect;
|
||||
break;
|
||||
/* Interval timer count */
|
||||
case 0x0230:
|
||||
val = s->dummy32;
|
||||
qemu_irq_lower(s->timer_irq);
|
||||
break;
|
||||
/* Offset 0x0238 */
|
||||
case 0x0238:
|
||||
val = s->offset238;
|
||||
break;
|
||||
default:
|
||||
#ifdef DEBUG_RC4030
|
||||
printf("rc4030: invalid read [" TARGET_FMT_lx "]\n", addr);
|
||||
#endif
|
||||
val = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef DEBUG_RC4030
|
||||
if ((addr & ~3) != 0x230)
|
||||
printf("rc4030: read 0x%02x at " TARGET_FMT_lx "\n", val, addr);
|
||||
#endif
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
uint32_t v = rc4030_readl(opaque, addr & ~0x3);
|
||||
if (addr & 0x2)
|
||||
return v >> 16;
|
||||
else
|
||||
return v & 0xffff;
|
||||
}
|
||||
|
||||
static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
uint32_t v = rc4030_readl(opaque, addr & ~0x3);
|
||||
return (v >> (8 * (addr & 0x3))) & 0xff;
|
||||
}
|
||||
|
||||
static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
rc4030State *s = opaque;
|
||||
addr &= 0x3fff;
|
||||
|
||||
#ifdef DEBUG_RC4030
|
||||
printf("rc4030: write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
|
||||
#endif
|
||||
|
||||
switch (addr & ~0x3) {
|
||||
/* Global config register */
|
||||
case 0x0000:
|
||||
s->config = val;
|
||||
break;
|
||||
/* DMA transl. table base */
|
||||
case 0x0018:
|
||||
s->dma_tl_base = val;
|
||||
break;
|
||||
/* DMA transl. table limit */
|
||||
case 0x0020:
|
||||
s->dma_tl_limit = val;
|
||||
break;
|
||||
/* I/O Cache Physical Tag */
|
||||
case 0x0048:
|
||||
s->cache_ptag = val;
|
||||
break;
|
||||
/* I/O Cache Logical Tag */
|
||||
case 0x0050:
|
||||
s->cache_ltag = val;
|
||||
break;
|
||||
/* I/O Cache Byte Mask */
|
||||
case 0x0058:
|
||||
s->cache_bmask |= val; /* HACK */
|
||||
break;
|
||||
/* I/O Cache Buffer Window */
|
||||
case 0x0060:
|
||||
s->cache_bwin = val;
|
||||
/* HACK */
|
||||
if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
|
||||
target_phys_addr_t dests[] = { 4, 0, 8, 0x10 };
|
||||
static int current = 0;
|
||||
target_phys_addr_t dest = 0 + dests[current];
|
||||
uint8_t buf;
|
||||
current = (current + 1) % (sizeof(dests)/sizeof(dests[0]));
|
||||
buf = s->cache_bwin - 1;
|
||||
cpu_physical_memory_rw(dest, &buf, 1, 1);
|
||||
}
|
||||
break;
|
||||
/* Remote Speed Registers */
|
||||
case 0x0070:
|
||||
case 0x0078:
|
||||
case 0x0080:
|
||||
case 0x0088:
|
||||
case 0x0090:
|
||||
case 0x0098:
|
||||
case 0x00a0:
|
||||
case 0x00a8:
|
||||
case 0x00b0:
|
||||
case 0x00b8:
|
||||
case 0x00c0:
|
||||
case 0x00c8:
|
||||
case 0x00d0:
|
||||
case 0x00d8:
|
||||
case 0x00e0:
|
||||
s->rem_speed[(addr - 0x0070) >> 3] = val;
|
||||
break;
|
||||
/* DMA channel base address */
|
||||
case 0x0100:
|
||||
case 0x0108:
|
||||
case 0x0110:
|
||||
case 0x0118:
|
||||
case 0x0120:
|
||||
case 0x0128:
|
||||
case 0x0130:
|
||||
case 0x0138:
|
||||
case 0x0140:
|
||||
case 0x0148:
|
||||
case 0x0150:
|
||||
case 0x0158:
|
||||
case 0x0160:
|
||||
case 0x0168:
|
||||
case 0x0170:
|
||||
case 0x0178:
|
||||
case 0x0180:
|
||||
case 0x0188:
|
||||
case 0x0190:
|
||||
case 0x0198:
|
||||
case 0x01a0:
|
||||
case 0x01a8:
|
||||
case 0x01b0:
|
||||
case 0x01b8:
|
||||
case 0x01c0:
|
||||
case 0x01c8:
|
||||
case 0x01d0:
|
||||
case 0x01d8:
|
||||
case 0x01e0:
|
||||
case 0x1e8:
|
||||
case 0x01f0:
|
||||
case 0x01f8:
|
||||
{
|
||||
int entry = (addr - 0x0100) >> 5;
|
||||
int idx = (addr & 0x1f) >> 3;
|
||||
s->dma_regs[entry][idx] = val;
|
||||
}
|
||||
break;
|
||||
/* Offset 0x0210 */
|
||||
case 0x0210:
|
||||
s->offset210 = val;
|
||||
break;
|
||||
/* Interval timer reload */
|
||||
case 0x0228:
|
||||
s->itr = val;
|
||||
qemu_irq_lower(s->timer_irq);
|
||||
set_next_tick(s);
|
||||
break;
|
||||
default:
|
||||
#ifdef DEBUG_RC4030
|
||||
printf("rc4030: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
|
||||
|
||||
if (addr & 0x2)
|
||||
val = (val << 16) | (old_val & 0x0000ffff);
|
||||
else
|
||||
val = val | (old_val & 0xffff0000);
|
||||
rc4030_writel(opaque, addr & ~0x3, val);
|
||||
}
|
||||
|
||||
static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
|
||||
|
||||
switch (addr & 3) {
|
||||
case 0:
|
||||
val = val | (old_val & 0xffffff00);
|
||||
break;
|
||||
case 1:
|
||||
val = (val << 8) | (old_val & 0xffff00ff);
|
||||
break;
|
||||
case 2:
|
||||
val = (val << 16) | (old_val & 0xff00ffff);
|
||||
break;
|
||||
case 3:
|
||||
val = (val << 24) | (old_val & 0x00ffffff);
|
||||
break;
|
||||
}
|
||||
rc4030_writel(opaque, addr & ~0x3, val);
|
||||
}
|
||||
|
||||
static CPUReadMemoryFunc *rc4030_read[3] = {
|
||||
rc4030_readb,
|
||||
rc4030_readw,
|
||||
rc4030_readl,
|
||||
};
|
||||
|
||||
static CPUWriteMemoryFunc *rc4030_write[3] = {
|
||||
rc4030_writeb,
|
||||
rc4030_writew,
|
||||
rc4030_writel,
|
||||
};
|
||||
|
||||
static void update_jazz_irq(rc4030State *s)
|
||||
{
|
||||
uint16_t pending;
|
||||
|
||||
pending = s->isr_jazz & s->imr_jazz;
|
||||
|
||||
#ifdef DEBUG_RC4030
|
||||
if (s->isr_jazz != 0) {
|
||||
uint32_t irq = 0;
|
||||
printf("jazz pending:");
|
||||
for (irq = 0; irq < sizeof(irq_names)/sizeof(irq_names[0]); irq++) {
|
||||
if (s->isr_jazz & (1 << irq)) {
|
||||
printf(" %s", irq_names[irq]);
|
||||
if (!(s->imr_jazz & (1 << irq))) {
|
||||
printf("(ignored)");
|
||||
}
|
||||
}
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
if (pending != 0)
|
||||
qemu_irq_raise(s->jazz_bus_irq);
|
||||
else
|
||||
qemu_irq_lower(s->jazz_bus_irq);
|
||||
}
|
||||
|
||||
static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
|
||||
{
|
||||
rc4030State *s = opaque;
|
||||
|
||||
if (level) {
|
||||
s->isr_jazz |= 1 << irq;
|
||||
} else {
|
||||
s->isr_jazz &= ~(1 << irq);
|
||||
}
|
||||
|
||||
update_jazz_irq(s);
|
||||
}
|
||||
|
||||
static void rc4030_periodic_timer(void *opaque)
|
||||
{
|
||||
rc4030State *s = opaque;
|
||||
|
||||
set_next_tick(s);
|
||||
qemu_irq_raise(s->timer_irq);
|
||||
}
|
||||
|
||||
static uint32_t int_readb(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
rc4030State *s = opaque;
|
||||
uint32_t val;
|
||||
uint32_t irq;
|
||||
addr &= 0xfff;
|
||||
|
||||
switch (addr) {
|
||||
case 0x00: {
|
||||
/* Local bus int source */
|
||||
uint32_t pending = s->isr_jazz & s->imr_jazz;
|
||||
val = 0;
|
||||
irq = 0;
|
||||
while (pending) {
|
||||
if (pending & 1) {
|
||||
//printf("returning irq %s\n", irq_names[irq]);
|
||||
val = (irq + 1) << 2;
|
||||
break;
|
||||
}
|
||||
irq++;
|
||||
pending >>= 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
#ifdef DEBUG_RC4030
|
||||
printf("rc4030: (interrupt controller) invalid read [" TARGET_FMT_lx "]\n", addr);
|
||||
#endif
|
||||
val = 0;
|
||||
}
|
||||
|
||||
#ifdef DEBUG_RC4030
|
||||
printf("rc4030: (interrupt controller) read 0x%02x at " TARGET_FMT_lx "\n", val, addr);
|
||||
#endif
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static uint32_t int_readw(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
uint32_t v;
|
||||
v = int_readb(opaque, addr);
|
||||
v |= int_readb(opaque, addr + 1) << 8;
|
||||
return v;
|
||||
}
|
||||
|
||||
static uint32_t int_readl(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
uint32_t v;
|
||||
v = int_readb(opaque, addr);
|
||||
v |= int_readb(opaque, addr + 1) << 8;
|
||||
v |= int_readb(opaque, addr + 2) << 16;
|
||||
v |= int_readb(opaque, addr + 3) << 24;
|
||||
return v;
|
||||
}
|
||||
|
||||
static void int_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
rc4030State *s = opaque;
|
||||
addr &= 0xfff;
|
||||
|
||||
#ifdef DEBUG_RC4030
|
||||
printf("rc4030: (interrupt controller) write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
|
||||
#endif
|
||||
|
||||
switch (addr) {
|
||||
/* Local bus int enable mask */
|
||||
case 0x02:
|
||||
s->imr_jazz = (s->imr_jazz & 0xff00) | (val << 0); update_jazz_irq(s);
|
||||
break;
|
||||
case 0x03:
|
||||
s->imr_jazz = (s->imr_jazz & 0x00ff) | (val << 8); update_jazz_irq(s);
|
||||
break;
|
||||
default:
|
||||
#ifdef DEBUG_RC4030
|
||||
printf("rc4030: (interrupt controller) invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void int_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
int_writeb(opaque, addr, val & 0xff);
|
||||
int_writeb(opaque, addr + 1, (val >> 8) & 0xff);
|
||||
}
|
||||
|
||||
static void int_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
int_writeb(opaque, addr, val & 0xff);
|
||||
int_writeb(opaque, addr + 1, (val >> 8) & 0xff);
|
||||
int_writeb(opaque, addr + 2, (val >> 16) & 0xff);
|
||||
int_writeb(opaque, addr + 3, (val >> 24) & 0xff);
|
||||
}
|
||||
|
||||
static CPUReadMemoryFunc *int_read[3] = {
|
||||
int_readb,
|
||||
int_readw,
|
||||
int_readl,
|
||||
};
|
||||
|
||||
static CPUWriteMemoryFunc *int_write[3] = {
|
||||
int_writeb,
|
||||
int_writew,
|
||||
int_writel,
|
||||
};
|
||||
|
||||
#define G364_512KB_RAM (0x0)
|
||||
#define G364_2MB_RAM (0x1)
|
||||
#define G364_8MB_RAM (0x2)
|
||||
#define G364_32MB_RAM (0x3)
|
||||
|
||||
static void rc4030_reset(void *opaque)
|
||||
{
|
||||
rc4030State *s = opaque;
|
||||
int i;
|
||||
|
||||
s->config = (G364_2MB_RAM << 8) | 0x04;
|
||||
s->invalid_address_register = 0;
|
||||
|
||||
memset(s->dma_regs, 0, sizeof(s->dma_regs));
|
||||
s->dma_tl_base = s->dma_tl_limit = 0;
|
||||
|
||||
s->remote_failed_address = s->memory_failed_address = 0;
|
||||
s->cache_ptag = s->cache_ltag = 0;
|
||||
s->cache_bmask = s->cache_bwin = 0;
|
||||
|
||||
s->offset208 = 0;
|
||||
s->offset210 = 0x18186;
|
||||
s->nvram_protect = 7;
|
||||
s->offset238 = 7;
|
||||
for (i = 0; i < 15; i++)
|
||||
s->rem_speed[i] = 7;
|
||||
s->imr_jazz = s->isr_jazz = 0;
|
||||
|
||||
s->itr = 0;
|
||||
s->dummy32 = 0;
|
||||
|
||||
qemu_irq_lower(s->timer_irq);
|
||||
qemu_irq_lower(s->jazz_bus_irq);
|
||||
}
|
||||
|
||||
qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus)
|
||||
{
|
||||
rc4030State *s;
|
||||
int s_chipset, s_int;
|
||||
|
||||
s = qemu_mallocz(sizeof(rc4030State));
|
||||
if (!s)
|
||||
return NULL;
|
||||
|
||||
s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
|
||||
s->timer_irq = timer;
|
||||
s->jazz_bus_irq = jazz_bus;
|
||||
|
||||
qemu_register_reset(rc4030_reset, s);
|
||||
rc4030_reset(s);
|
||||
|
||||
s_chipset = cpu_register_io_memory(0, rc4030_read, rc4030_write, s);
|
||||
cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
|
||||
s_int = cpu_register_io_memory(0, int_read, int_write, s);
|
||||
cpu_register_physical_memory(0xf0000000, 0x00001000, s_int);
|
||||
|
||||
return qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
|
||||
}
|
||||
4
vl.c
4
vl.c
@ -26,7 +26,6 @@
|
||||
#include "hw/usb.h"
|
||||
#include "hw/pcmcia.h"
|
||||
#include "hw/pc.h"
|
||||
#include "hw/fdc.h"
|
||||
#include "hw/audiodev.h"
|
||||
#include "hw/isa.h"
|
||||
#include "net.h"
|
||||
@ -8002,6 +8001,7 @@ static void register_machines(void)
|
||||
qemu_register_machine(&taihu_machine);
|
||||
#elif defined(TARGET_MIPS)
|
||||
qemu_register_machine(&mips_machine);
|
||||
qemu_register_machine(&mips_magnum_machine);
|
||||
qemu_register_machine(&mips_malta_machine);
|
||||
qemu_register_machine(&mips_pica61_machine);
|
||||
qemu_register_machine(&mips_mipssim_machine);
|
||||
@ -8056,7 +8056,7 @@ static void register_machines(void)
|
||||
#ifdef HAS_AUDIO
|
||||
struct soundhw soundhw[] = {
|
||||
#ifdef HAS_AUDIO_CHOICE
|
||||
#ifdef TARGET_I386
|
||||
#if defined(TARGET_I386) || defined(TARGET_MIPS)
|
||||
{
|
||||
"pcspk",
|
||||
"PC speaker",
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user