SYS-OSS/FRET-qemu
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

target-ppc: Add bctar Instruction

Browse Source 
This patch adds the Branch Conditional to Address Register (bctar)
instruction.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Tom Musta 2014-02-10 11:26:55 -06:00 committed by Alexander Graf
parent 60511041d6
commit 52a4984d97
1 changed files with 10 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
target-ppc/translate.c
View File

@ -3745,6 +3745,7 @@ static void gen_b(DisasContext *ctx)
#define BCOND_IM 0 #define BCOND_IM 0
#define BCOND_LR 1 #define BCOND_LR 1
#define BCOND_CTR 2 #define BCOND_CTR 2
#define BCOND_TAR 3
static inline void gen_bcond(DisasContext *ctx, int type) static inline void gen_bcond(DisasContext *ctx, int type)
{ {
@ -3753,10 +3754,12 @@ static inline void gen_bcond(DisasContext *ctx, int type)
TCGv target; TCGv target;
ctx->exception = POWERPC_EXCP_BRANCH; ctx->exception = POWERPC_EXCP_BRANCH;
if (type == BCOND_LR || type == BCOND_CTR) { if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
target = tcg_temp_local_new(); target = tcg_temp_local_new();
if (type == BCOND_CTR) if (type == BCOND_CTR)
tcg_gen_mov_tl(target, cpu_ctr); tcg_gen_mov_tl(target, cpu_ctr);
else if (type == BCOND_TAR)
gen_load_spr(target, SPR_TAR);
else else
tcg_gen_mov_tl(target, cpu_lr); tcg_gen_mov_tl(target, cpu_lr);
} else { } else {
@ -3838,6 +3841,11 @@ static void gen_bclr(DisasContext *ctx)
gen_bcond(ctx, BCOND_LR); gen_bcond(ctx, BCOND_LR);
} }
static void gen_bctar(DisasContext *ctx)
{
gen_bcond(ctx, BCOND_TAR);
}
/*** Condition register logical ***/ /*** Condition register logical ***/
#define GEN_CRLOGIC(name, tcg_op, opc) \ #define GEN_CRLOGIC(name, tcg_op, opc) \
static void glue(gen_, name)(DisasContext *ctx) \ static void glue(gen_, name)(DisasContext *ctx) \
@ -9594,6 +9602,7 @@ GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)