Remove dyngen ARM code, which did't build.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4501 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
parent
811d4cf4b0
commit
a2a64a1f2d
316
dyngen.c
316
dyngen.c
@ -1284,161 +1284,6 @@ get_plt_index (const char *name, unsigned long addend)
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#endif
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#endif
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#ifdef HOST_ARM
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int arm_emit_ldr_info(const char *name, unsigned long start_offset,
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FILE *outfile, uint8_t *p_start, uint8_t *p_end,
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ELF_RELOC *relocs, int nb_relocs)
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{
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uint8_t *p;
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uint32_t insn;
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int offset, min_offset, pc_offset, data_size, spare, max_pool;
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uint8_t data_allocated[1024];
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unsigned int data_index;
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int type;
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memset(data_allocated, 0, sizeof(data_allocated));
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p = p_start;
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min_offset = p_end - p_start;
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spare = 0x7fffffff;
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while (p < p_start + min_offset) {
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insn = get32((uint32_t *)p);
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/* TODO: Armv5e ldrd. */
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/* TODO: VFP load. */
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if ((insn & 0x0d5f0000) == 0x051f0000) {
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/* ldr reg, [pc, #im] */
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offset = insn & 0xfff;
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if (!(insn & 0x00800000))
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offset = -offset;
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max_pool = 4096;
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type = 0;
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} else if ((insn & 0x0e5f0f00) == 0x0c1f0100) {
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/* FPA ldf. */
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offset = (insn & 0xff) << 2;
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if (!(insn & 0x00800000))
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offset = -offset;
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max_pool = 1024;
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type = 1;
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} else if ((insn & 0x0fff0000) == 0x028f0000) {
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/* Some gcc load a doubleword immediate with
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add regN, pc, #imm
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ldmia regN, {regN, regM}
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Hope and pray the compiler never generates somethin like
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add reg, pc, #imm1; ldr reg, [reg, #-imm2]; */
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int r;
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r = (insn & 0xf00) >> 7;
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offset = ((insn & 0xff) >> r) | ((insn & 0xff) << (32 - r));
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max_pool = 1024;
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type = 2;
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} else {
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max_pool = 0;
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type = -1;
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}
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if (type >= 0) {
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/* PC-relative load needs fixing up. */
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if (spare > max_pool - offset)
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spare = max_pool - offset;
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if ((offset & 3) !=0)
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error("%s:%04x: pc offset must be 32 bit aligned",
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name, start_offset + p - p_start);
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if (offset < 0)
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error("%s:%04x: Embedded literal value",
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name, start_offset + p - p_start);
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pc_offset = p - p_start + offset + 8;
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if (pc_offset <= (p - p_start) ||
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pc_offset >= (p_end - p_start))
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error("%s:%04x: pc offset must point inside the function code",
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name, start_offset + p - p_start);
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if (pc_offset < min_offset)
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min_offset = pc_offset;
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if (outfile) {
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/* The intruction position */
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fprintf(outfile, " arm_ldr_ptr->ptr = gen_code_ptr + %d;\n",
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p - p_start);
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/* The position of the constant pool data. */
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data_index = ((p_end - p_start) - pc_offset) >> 2;
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fprintf(outfile, " arm_ldr_ptr->data_ptr = arm_data_ptr - %d;\n",
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data_index);
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fprintf(outfile, " arm_ldr_ptr->type = %d;\n", type);
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fprintf(outfile, " arm_ldr_ptr++;\n");
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}
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}
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p += 4;
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}
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/* Copy and relocate the constant pool data. */
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data_size = (p_end - p_start) - min_offset;
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if (data_size > 0 && outfile) {
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spare += min_offset;
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fprintf(outfile, " arm_data_ptr -= %d;\n", data_size >> 2);
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fprintf(outfile, " arm_pool_ptr -= %d;\n", data_size);
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fprintf(outfile, " if (arm_pool_ptr > gen_code_ptr + %d)\n"
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" arm_pool_ptr = gen_code_ptr + %d;\n",
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spare, spare);
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data_index = 0;
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for (pc_offset = min_offset;
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pc_offset < p_end - p_start;
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pc_offset += 4) {
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ELF_RELOC *rel;
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int i, addend, type;
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const char *sym_name;
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char relname[1024];
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/* data value */
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addend = get32((uint32_t *)(p_start + pc_offset));
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relname[0] = '\0';
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for(i = 0, rel = relocs;i < nb_relocs; i++, rel++) {
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if (rel->r_offset == (pc_offset + start_offset)) {
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sym_name = get_rel_sym_name(rel);
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/* the compiler leave some unnecessary references to the code */
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get_reloc_expr(relname, sizeof(relname), sym_name);
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type = ELF32_R_TYPE(rel->r_info);
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if (type != R_ARM_ABS32)
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error("%s: unsupported data relocation", name);
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break;
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}
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}
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fprintf(outfile, " arm_data_ptr[%d] = 0x%x",
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data_index, addend);
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if (relname[0] != '\0')
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fprintf(outfile, " + %s", relname);
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fprintf(outfile, ";\n");
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data_index++;
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}
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}
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if (p == p_start)
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goto arm_ret_error;
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p -= 4;
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insn = get32((uint32_t *)p);
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/* The last instruction must be an ldm instruction. There are several
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forms generated by gcc:
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ldmib sp, {..., pc} (implies a sp adjustment of +4)
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ldmia sp, {..., pc}
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ldmea fp, {..., pc} */
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if ((insn & 0xffff8000) == 0xe99d8000) {
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if (outfile) {
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fprintf(outfile,
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" *(uint32_t *)(gen_code_ptr + %d) = 0xe28dd004;\n",
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p - p_start);
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}
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p += 4;
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} else if ((insn & 0xffff8000) != 0xe89d8000
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&& (insn & 0xffff8000) != 0xe91b8000) {
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arm_ret_error:
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if (!outfile)
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printf("%s: invalid epilog\n", name);
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}
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return p - p_start;
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}
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#endif
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#define MAX_ARGS 3
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#define MAX_ARGS 3
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/* generate op code */
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/* generate op code */
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@ -1633,27 +1478,6 @@ void gen_code(const char *name, host_ulong offset, host_ulong size,
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copy_size = p - p_start;
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copy_size = p - p_start;
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}
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}
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#elif defined(HOST_ARM)
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{
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uint32_t insn;
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if ((p_end - p_start) <= 16)
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error("%s: function too small", name);
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if (get32((uint32_t *)p_start) != 0xe1a0c00d ||
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(get32((uint32_t *)(p_start + 4)) & 0xffff0000) != 0xe92d0000 ||
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get32((uint32_t *)(p_start + 8)) != 0xe24cb004)
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error("%s: invalid prolog", name);
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p_start += 12;
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start_offset += 12;
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insn = get32((uint32_t *)p_start);
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if ((insn & 0xffffff00) == 0xe24dd000) {
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/* Stack adjustment. Assume op uses the frame pointer. */
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p_start -= 4;
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start_offset -= 4;
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}
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copy_size = arm_emit_ldr_info(name, start_offset, NULL, p_start, p_end,
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relocs, nb_relocs);
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}
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#elif defined(HOST_M68K)
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#elif defined(HOST_M68K)
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{
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{
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uint8_t *p;
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uint8_t *p;
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@ -1725,6 +1549,8 @@ void gen_code(const char *name, host_ulong offset, host_ulong size,
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}
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}
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copy_size = p - p_start;
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copy_size = p - p_start;
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}
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}
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#elif defined(HOST_ARM)
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error("dyngen targets not supported on ARM");
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#else
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#else
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#error unsupported CPU
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#error unsupported CPU
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#endif
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#endif
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@ -2558,74 +2384,6 @@ void gen_code(const char *name, host_ulong offset, host_ulong size,
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}
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}
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}
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}
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}
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}
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#elif defined(HOST_ARM)
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{
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char relname[256];
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int type;
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int addend;
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int reloc_offset;
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uint32_t insn;
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insn = get32((uint32_t *)(p_start + 4));
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/* If prologue ends in sub sp, sp, #const then assume
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op has a stack frame and needs the frame pointer. */
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if ((insn & 0xffffff00) == 0xe24dd000) {
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int i;
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uint32_t opcode;
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opcode = 0xe28db000; /* add fp, sp, #0. */
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#if 0
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/* ??? Need to undo the extra stack adjustment at the end of the op.
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For now just leave the stack misaligned and hope it doesn't break anything
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too important. */
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if ((insn & 4) != 0) {
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/* Preserve doubleword stack alignment. */
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fprintf(outfile,
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" *(uint32_t *)(gen_code_ptr + 4)= 0x%x;\n",
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insn + 4);
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opcode -= 4;
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}
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#endif
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insn = get32((uint32_t *)(p_start - 4));
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/* Calculate the size of the saved registers,
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excluding pc. */
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for (i = 0; i < 15; i++) {
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if (insn & (1 << i))
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opcode += 4;
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}
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fprintf(outfile,
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" *(uint32_t *)gen_code_ptr = 0x%x;\n", opcode);
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}
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arm_emit_ldr_info(relname, start_offset, outfile, p_start, p_end,
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relocs, nb_relocs);
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for(i = 0, rel = relocs;i < nb_relocs; i++, rel++) {
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if (rel->r_offset >= start_offset &&
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rel->r_offset < start_offset + copy_size) {
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sym_name = strtab + symtab[ELFW(R_SYM)(rel->r_info)].st_name;
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/* the compiler leave some unnecessary references to the code */
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if (sym_name[0] == '\0')
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continue;
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get_reloc_expr(relname, sizeof(relname), sym_name);
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type = ELF32_R_TYPE(rel->r_info);
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addend = get32((uint32_t *)(text + rel->r_offset));
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reloc_offset = rel->r_offset - start_offset;
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switch(type) {
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case R_ARM_ABS32:
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fprintf(outfile, " *(uint32_t *)(gen_code_ptr + %d) = %s + %d;\n",
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reloc_offset, relname, addend);
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break;
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case R_ARM_PC24:
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case R_ARM_JUMP24:
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case R_ARM_CALL:
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fprintf(outfile, " arm_reloc_pc24((uint32_t *)(gen_code_ptr + %d), 0x%x, %s);\n",
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reloc_offset, addend, relname);
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break;
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default:
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error("unsupported arm relocation (%d)", type);
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}
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}
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}
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}
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#elif defined(HOST_M68K)
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#elif defined(HOST_M68K)
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{
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{
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char relname[256];
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char relname[256];
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@ -2810,6 +2568,8 @@ void gen_code(const char *name, host_ulong offset, host_ulong size,
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}
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}
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}
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}
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}
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}
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#elif defined(HOST_ARM)
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error("dyngen targets not supported on ARM");
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#else
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#else
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#error unsupported CPU
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#error unsupported CPU
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#endif
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#endif
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@ -2868,59 +2628,7 @@ int gen_file(FILE *outfile, int out_type)
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/* generate big code generation switch */
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/* generate big code generation switch */
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#ifdef HOST_ARM
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#ifdef HOST_ARM
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#error broken
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error("dyngen targets not supported on ARM");
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/* We need to know the size of all the ops so we can figure out when
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to emit constant pools. This must be consistent with opc.h. */
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fprintf(outfile,
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"static const uint32_t arm_opc_size[] = {\n"
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" 0,\n" /* end */
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" 0,\n" /* nop */
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" 0,\n" /* nop1 */
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" 0,\n" /* nop2 */
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" 0,\n"); /* nop3 */
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for(i = 0, sym = symtab; i < nb_syms; i++, sym++) {
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const char *name;
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name = get_sym_name(sym);
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if (strstart(name, OP_PREFIX, NULL)) {
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fprintf(outfile, " %d,\n", sym->st_size);
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}
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}
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fprintf(outfile,
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"};\n");
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#endif
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#ifdef HOST_ARM
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#error broken
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/* Arm is tricky because it uses constant pools for loading immediate values.
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We assume (and require) each function is code followed by a constant pool.
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All the ops are small so this should be ok. For each op we figure
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out how much "spare" range we have in the load instructions. This allows
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us to insert subsequent ops in between the op and the constant pool,
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eliminating the neeed to jump around the pool.
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We currently generate:
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[ For this example we assume merging would move op1_pool out of range.
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In practice we should be able to combine many ops before the offset
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limits are reached. ]
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op1_code;
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op2_code;
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goto op3;
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op2_pool;
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op1_pool;
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op3:
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op3_code;
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ret;
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op3_pool;
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Ideally we'd put op1_pool before op2_pool, but that requires two passes.
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*/
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fprintf(outfile,
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" uint8_t *last_gen_code_ptr = gen_code_buf;\n"
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" LDREntry *arm_ldr_ptr = arm_ldr_table;\n"
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" uint32_t *arm_data_ptr = arm_data_table + ARM_LDR_TABLE_SIZE;\n"
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/* Initialise the parmissible pool offset to an arbitary large value. */
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" uint8_t *arm_pool_ptr = gen_code_buf + 0x1000000;\n");
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#endif
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#endif
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#ifdef HOST_IA64
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#ifdef HOST_IA64
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#error broken
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#error broken
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@ -2981,20 +2689,6 @@ fprintf(outfile,
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}
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}
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#endif
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#endif
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#ifdef HOST_ARM
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#error broken
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/* Generate constant pool if needed */
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fprintf(outfile,
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" if (gen_code_ptr + arm_opc_size[*opc_ptr] >= arm_pool_ptr) {\n"
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|
||||||
" gen_code_ptr = arm_flush_ldr(gen_code_ptr, arm_ldr_table, "
|
|
||||||
"arm_ldr_ptr, arm_data_ptr, arm_data_table + ARM_LDR_TABLE_SIZE, 1);\n"
|
|
||||||
" last_gen_code_ptr = gen_code_ptr;\n"
|
|
||||||
" arm_ldr_ptr = arm_ldr_table;\n"
|
|
||||||
" arm_data_ptr = arm_data_table + ARM_LDR_TABLE_SIZE;\n"
|
|
||||||
" arm_pool_ptr = gen_code_ptr + 0x1000000;\n"
|
|
||||||
" }\n");
|
|
||||||
#endif
|
|
||||||
|
|
||||||
for(i = 0, sym = symtab; i < nb_syms; i++, sym++) {
|
for(i = 0, sym = symtab; i < nb_syms; i++, sym++) {
|
||||||
const char *name;
|
const char *name;
|
||||||
name = get_sym_name(sym);
|
name = get_sym_name(sym);
|
||||||
|
|||||||
103
tcg/tcg-dyngen.c
103
tcg/tcg-dyngen.c
@ -143,109 +143,6 @@ void fix_bsr(void *p, int offset) {
|
|||||||
|
|
||||||
#endif /* __alpha__ */
|
#endif /* __alpha__ */
|
||||||
|
|
||||||
#ifdef __arm__
|
|
||||||
|
|
||||||
#define ARM_LDR_TABLE_SIZE 1024
|
|
||||||
|
|
||||||
typedef struct LDREntry {
|
|
||||||
uint8_t *ptr;
|
|
||||||
uint32_t *data_ptr;
|
|
||||||
unsigned type:2;
|
|
||||||
} LDREntry;
|
|
||||||
|
|
||||||
static LDREntry arm_ldr_table[1024];
|
|
||||||
static uint32_t arm_data_table[ARM_LDR_TABLE_SIZE];
|
|
||||||
|
|
||||||
extern char exec_loop;
|
|
||||||
|
|
||||||
static inline void arm_reloc_pc24(uint32_t *ptr, uint32_t insn, int val)
|
|
||||||
{
|
|
||||||
*ptr = (insn & ~0xffffff) | ((insn + ((val - (int)ptr) >> 2)) & 0xffffff);
|
|
||||||
}
|
|
||||||
|
|
||||||
static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr,
|
|
||||||
LDREntry *ldr_start, LDREntry *ldr_end,
|
|
||||||
uint32_t *data_start, uint32_t *data_end,
|
|
||||||
int gen_jmp)
|
|
||||||
{
|
|
||||||
LDREntry *le;
|
|
||||||
uint32_t *ptr;
|
|
||||||
int offset, data_size, target;
|
|
||||||
uint8_t *data_ptr;
|
|
||||||
uint32_t insn;
|
|
||||||
uint32_t mask;
|
|
||||||
|
|
||||||
data_size = (data_end - data_start) << 2;
|
|
||||||
|
|
||||||
if (gen_jmp) {
|
|
||||||
/* generate branch to skip the data */
|
|
||||||
if (data_size == 0)
|
|
||||||
return gen_code_ptr;
|
|
||||||
target = (long)gen_code_ptr + data_size + 4;
|
|
||||||
arm_reloc_pc24((uint32_t *)gen_code_ptr, 0xeafffffe, target);
|
|
||||||
gen_code_ptr += 4;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* copy the data */
|
|
||||||
data_ptr = gen_code_ptr;
|
|
||||||
memcpy(gen_code_ptr, data_start, data_size);
|
|
||||||
gen_code_ptr += data_size;
|
|
||||||
|
|
||||||
/* patch the ldr to point to the data */
|
|
||||||
for(le = ldr_start; le < ldr_end; le++) {
|
|
||||||
ptr = (uint32_t *)le->ptr;
|
|
||||||
offset = ((unsigned long)(le->data_ptr) - (unsigned long)data_start) +
|
|
||||||
(unsigned long)data_ptr -
|
|
||||||
(unsigned long)ptr - 8;
|
|
||||||
if (offset < 0) {
|
|
||||||
fprintf(stderr, "Negative constant pool offset\n");
|
|
||||||
tcg_abort();
|
|
||||||
}
|
|
||||||
switch (le->type) {
|
|
||||||
case 0: /* ldr */
|
|
||||||
mask = ~0x00800fff;
|
|
||||||
if (offset >= 4096) {
|
|
||||||
fprintf(stderr, "Bad ldr offset\n");
|
|
||||||
tcg_abort();
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case 1: /* ldc */
|
|
||||||
mask = ~0x008000ff;
|
|
||||||
if (offset >= 1024 ) {
|
|
||||||
fprintf(stderr, "Bad ldc offset\n");
|
|
||||||
tcg_abort();
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case 2: /* add */
|
|
||||||
mask = ~0xfff;
|
|
||||||
if (offset >= 1024 ) {
|
|
||||||
fprintf(stderr, "Bad add offset\n");
|
|
||||||
tcg_abort();
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
fprintf(stderr, "Bad pc relative fixup\n");
|
|
||||||
tcg_abort();
|
|
||||||
}
|
|
||||||
insn = *ptr & mask;
|
|
||||||
switch (le->type) {
|
|
||||||
case 0: /* ldr */
|
|
||||||
insn |= offset | 0x00800000;
|
|
||||||
break;
|
|
||||||
case 1: /* ldc */
|
|
||||||
insn |= (offset >> 2) | 0x00800000;
|
|
||||||
break;
|
|
||||||
case 2: /* add */
|
|
||||||
insn |= (offset >> 2) | 0xf00;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
*ptr = insn;
|
|
||||||
}
|
|
||||||
return gen_code_ptr;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* __arm__ */
|
|
||||||
|
|
||||||
#ifdef __ia64
|
#ifdef __ia64
|
||||||
|
|
||||||
/* Patch instruction with "val" where "mask" has 1 bits. */
|
/* Patch instruction with "val" where "mask" has 1 bits. */
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user