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hw/pci-bridge/xio3130: Remove unused functions

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Introduced in 48ebf2f90f8 and faf1e708d5b, these functions
were never used. Remove them.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé 2018-10-10 23:53:53 +02:00 committed by Michael S. Tsirkin
parent 0259e96687
commit c6329a2d09
4 changed files with 2 additions and 71 deletions
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28
hw/pci-bridge/xio3130_downstream.c
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@ -23,7 +23,7 @@
#include "hw/pci/pci_ids.h" #include "hw/pci/pci_ids.h"
#include "hw/pci/msi.h" #include "hw/pci/msi.h"
#include "hw/pci/pcie.h" #include "hw/pci/pcie.h"
#include "xio3130_downstream.h" #include "hw/pci/pcie_port.h"
#include "qapi/error.h" #include "qapi/error.h"
#define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */ #define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */
@ -127,32 +127,6 @@ static void xio3130_downstream_exitfn(PCIDevice *d)
pci_bridge_exitfn(d); pci_bridge_exitfn(d);
} }
PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,
const char *bus_name, pci_map_irq_fn map_irq,
uint8_t port, uint8_t chassis,
uint16_t slot)
{
PCIDevice *d;
PCIBridge *br;
DeviceState *qdev;
d = pci_create_multifunction(bus, devfn, multifunction,
"xio3130-downstream");
if (!d) {
return NULL;
}
br = PCI_BRIDGE(d);
qdev = DEVICE(d);
pci_bridge_map_irq(br, bus_name, map_irq);
qdev_prop_set_uint8(qdev, "port", port);
qdev_prop_set_uint8(qdev, "chassis", chassis);
qdev_prop_set_uint16(qdev, "slot", slot);
qdev_init_nofail(qdev);
return PCIE_SLOT(d);
}
static Property xio3130_downstream_props[] = { static Property xio3130_downstream_props[] = {
DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
QEMU_PCIE_SLTCAP_PCP_BITNR, true), QEMU_PCIE_SLTCAP_PCP_BITNR, true),

11
hw/pci-bridge/xio3130_downstream.h
View File

@ -1,11 +0,0 @@
#ifndef QEMU_XIO3130_DOWNSTREAM_H
#define QEMU_XIO3130_DOWNSTREAM_H
#include "hw/pci/pcie_port.h"
PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,
const char *bus_name, pci_map_irq_fn map_irq,
uint8_t port, uint8_t chassis,
uint16_t slot);
#endif /* QEMU_XIO3130_DOWNSTREAM_H */

24
hw/pci-bridge/xio3130_upstream.c
View File

@ -23,7 +23,7 @@
#include "hw/pci/pci_ids.h" #include "hw/pci/pci_ids.h"
#include "hw/pci/msi.h" #include "hw/pci/msi.h"
#include "hw/pci/pcie.h" #include "hw/pci/pcie.h"
#include "xio3130_upstream.h" #include "hw/pci/pcie_port.h"
#define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */ #define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */
#define XIO3130_REVISION 0x2 #define XIO3130_REVISION 0x2
@ -108,28 +108,6 @@ static void xio3130_upstream_exitfn(PCIDevice *d)
pci_bridge_exitfn(d); pci_bridge_exitfn(d);
} }
PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
const char *bus_name, pci_map_irq_fn map_irq,
uint8_t port)
{
PCIDevice *d;
PCIBridge *br;
DeviceState *qdev;
d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream");
if (!d) {
return NULL;
}
br = PCI_BRIDGE(d);
qdev = DEVICE(d);
pci_bridge_map_irq(br, bus_name, map_irq);
qdev_prop_set_uint8(qdev, "port", port);
qdev_init_nofail(qdev);
return PCIE_PORT(d);
}
static const VMStateDescription vmstate_xio3130_upstream = { static const VMStateDescription vmstate_xio3130_upstream = {
.name = "xio3130-express-upstream-port", .name = "xio3130-express-upstream-port",
.priority = MIG_PRI_PCI_BUS, .priority = MIG_PRI_PCI_BUS,

10
hw/pci-bridge/xio3130_upstream.h
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@ -1,10 +0,0 @@
#ifndef QEMU_XIO3130_UPSTREAM_H
#define QEMU_XIO3130_UPSTREAM_H
#include "hw/pci/pcie_port.h"
PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
const char *bus_name, pci_map_irq_fn map_irq,
uint8_t port);
#endif /* QEMU_XIO3130_UPSTREAM_H */