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serial: Use enum device_endian in serial_mm_init parameter

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The use of DEVICE_NATIVE_ENDIAN cleans up lots of ifdefs in
many of the callers.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Richard Henderson 2011-08-11 16:07:14 -07:00 committed by Avi Kivity
parent 8e8ffc44e8
commit fb50cfe44d
14 changed files with 38 additions and 84 deletions
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14
hw/mips_jazz.c
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@ -264,18 +264,12 @@ static void mips_jazz_init(MemoryRegion *address_space,
/* Serial ports */ /* Serial ports */
if (serial_hds[0]) { if (serial_hds[0]) {
#ifdef TARGET_WORDS_BIGENDIAN serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0],
serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1); 1, DEVICE_NATIVE_ENDIAN);
#else
serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0);
#endif
} }
if (serial_hds[1]) { if (serial_hds[1]) {
#ifdef TARGET_WORDS_BIGENDIAN serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1],
serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1); 1, DEVICE_NATIVE_ENDIAN);
#else
serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0);
#endif
} }
/* Parallel port */ /* Parallel port */

7
hw/mips_malta.c
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@ -446,11 +446,8 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
s->display = qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init); s->display = qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init);
#ifdef TARGET_WORDS_BIGENDIAN s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr,
s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1, 1); 1, DEVICE_NATIVE_ENDIAN);
#else
s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1, 0);
#endif
malta_fpga_reset(s); malta_fpga_reset(s);
qemu_register_reset(malta_fpga_reset, s); qemu_register_reset(malta_fpga_reset, s);

14
hw/musicpal.c
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@ -1486,22 +1486,12 @@ static void musicpal_init(ram_addr_t ram_size,
pic[MP_TIMER4_IRQ], NULL); pic[MP_TIMER4_IRQ], NULL);
if (serial_hds[0]) { if (serial_hds[0]) {
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
serial_hds[0], 1, 1); serial_hds[0], 1, DEVICE_NATIVE_ENDIAN);
#else
serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
serial_hds[0], 1, 0);
#endif
} }
if (serial_hds[1]) { if (serial_hds[1]) {
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
serial_hds[1], 1, 1); serial_hds[1], 1, DEVICE_NATIVE_ENDIAN);
#else
serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
serial_hds[1], 1, 0);
#endif
} }
/* Register flash */ /* Register flash */

17
hw/omap_uart.c
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@ -60,15 +60,9 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
s->base = base; s->base = base;
s->fclk = fclk; s->fclk = fclk;
s->irq = irq; s->irq = irq;
#ifdef TARGET_WORDS_BIGENDIAN
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
chr ?: qemu_chr_new(label, "null", NULL), 1, chr ?: qemu_chr_new(label, "null", NULL), 1,
1); DEVICE_NATIVE_ENDIAN);
#else
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
chr ?: qemu_chr_new(label, "null", NULL), 1,
0);
#endif
return s; return s;
} }
@ -182,15 +176,8 @@ struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr) void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
{ {
/* TODO: Should reuse or destroy current s->serial */ /* TODO: Should reuse or destroy current s->serial */
#ifdef TARGET_WORDS_BIGENDIAN
s->serial = serial_mm_init(s->base, 2, s->irq, s->serial = serial_mm_init(s->base, 2, s->irq,
omap_clk_getrate(s->fclk) / 16, omap_clk_getrate(s->fclk) / 16,
chr ?: qemu_chr_new("null", "null", NULL), 1, chr ?: qemu_chr_new("null", "null", NULL), 1,
1); DEVICE_NATIVE_ENDIAN);
#else
s->serial = serial_mm_init(s->base, 2, s->irq,
omap_clk_getrate(s->fclk) / 16,
chr ?: qemu_chr_new("null", "null", NULL), 1,
0);
#endif
} }

2
hw/pc.h
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@ -18,7 +18,7 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase,
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
qemu_irq irq, int baudbase, qemu_irq irq, int baudbase,
CharDriverState *chr, int ioregister, CharDriverState *chr, int ioregister,
int be); enum device_endian);
static inline bool serial_isa_init(int index, CharDriverState *chr) static inline bool serial_isa_init(int index, CharDriverState *chr)
{ {
ISADevice *dev; ISADevice *dev;

2
hw/petalogix_ml605_mmu.c
View File

@ -185,7 +185,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
} }
serial_mm_init(UART16550_BASEADDR + 0x1000, 2, irq[5], 115200, serial_mm_init(UART16550_BASEADDR + 0x1000, 2, irq[5], 115200,
serial_hds[0], 1, 0); serial_hds[0], 1, DEVICE_LITTLE_ENDIAN);
/* 2 timers at irq 2 @ 100 Mhz. */ /* 2 timers at irq 2 @ 100 Mhz. */
xilinx_timer_create(TIMER_BASEADDR, irq[2], 2, 100 * 1000000); xilinx_timer_create(TIMER_BASEADDR, irq[2], 2, 100 * 1000000);

8
hw/ppc405_uc.c
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@ -2150,11 +2150,11 @@ CPUState *ppc405cr_init (MemoryRegion ram_memories[4],
/* Serial ports */ /* Serial ports */
if (serial_hds[0] != NULL) { if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
serial_hds[0], 1, 1); serial_hds[0], 1, DEVICE_BIG_ENDIAN);
} }
if (serial_hds[1] != NULL) { if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
serial_hds[1], 1, 1); serial_hds[1], 1, DEVICE_BIG_ENDIAN);
} }
/* IIC controller */ /* IIC controller */
ppc405_i2c_init(0xef600500, pic[2]); ppc405_i2c_init(0xef600500, pic[2]);
@ -2505,11 +2505,11 @@ CPUState *ppc405ep_init (MemoryRegion ram_memories[2],
/* Serial ports */ /* Serial ports */
if (serial_hds[0] != NULL) { if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
serial_hds[0], 1, 1); serial_hds[0], 1, DEVICE_BIG_ENDIAN);
} }
if (serial_hds[1] != NULL) { if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
serial_hds[1], 1, 1); serial_hds[1], 1, DEVICE_BIG_ENDIAN);
} }
/* OCM */ /* OCM */
ppc405_ocm_init(env); ppc405_ocm_init(env);

4
hw/ppc440.c
View File

@ -93,11 +93,11 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
if (serial_hds[0] != NULL) { if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
serial_hds[0], 1, 1); serial_hds[0], 1, DEVICE_BIG_ENDIAN);
} }
if (serial_hds[1] != NULL) { if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
serial_hds[1], 1, 1); serial_hds[1], 1, DEVICE_BIG_ENDIAN);
} }
return env; return env;

4
hw/ppce500_mpc8544ds.c
View File

@ -276,13 +276,13 @@ static void mpc8544ds_init(ram_addr_t ram_size,
if (serial_hds[0]) { if (serial_hds[0]) {
serial_mm_init(MPC8544_SERIAL0_REGS_BASE, serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
0, mpic[12+26], 399193, 0, mpic[12+26], 399193,
serial_hds[0], 1, 1); serial_hds[0], 1, DEVICE_BIG_ENDIAN);
} }
if (serial_hds[1]) { if (serial_hds[1]) {
serial_mm_init(MPC8544_SERIAL1_REGS_BASE, serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
0, mpic[12+26], 399193, 0, mpic[12+26], 399193,
serial_hds[0], 1, 1); serial_hds[0], 1, DEVICE_BIG_ENDIAN);
} }
/* General Utility device */ /* General Utility device */

29
hw/pxa2xx.c
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@ -2113,19 +2113,16 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
for (i = 0; pxa270_serial[i].io_base; i ++) for (i = 0; pxa270_serial[i].io_base; i++) {
if (serial_hds[i]) if (serial_hds[i]) {
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(pxa270_serial[i].io_base, 2, serial_mm_init(pxa270_serial[i].io_base, 2,
qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
14857000 / 16, serial_hds[i], 1, 1); 14857000 / 16, serial_hds[i], 1,
#else DEVICE_NATIVE_ENDIAN);
serial_mm_init(pxa270_serial[i].io_base, 2, } else {
qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
14857000 / 16, serial_hds[i], 1, 0);
#endif
else
break; break;
}
}
if (serial_hds[i]) if (serial_hds[i])
s->fir = pxa2xx_fir_init(0x40800000, s->fir = pxa2xx_fir_init(0x40800000,
qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
@ -2248,20 +2245,16 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
for (i = 0; pxa255_serial[i].io_base; i ++) for (i = 0; pxa255_serial[i].io_base; i++) {
if (serial_hds[i]) { if (serial_hds[i]) {
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(pxa255_serial[i].io_base, 2, serial_mm_init(pxa255_serial[i].io_base, 2,
qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
14745600 / 16, serial_hds[i], 1, 1); 14745600 / 16, serial_hds[i], 1,
#else DEVICE_NATIVE_ENDIAN);
serial_mm_init(pxa255_serial[i].io_base, 2,
qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
14745600 / 16, serial_hds[i], 1, 0);
#endif
} else { } else {
break; break;
} }
}
if (serial_hds[i]) if (serial_hds[i])
s->fir = pxa2xx_fir_init(0x40800000, s->fir = pxa2xx_fir_init(0x40800000,
qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),

4
hw/serial.c
View File

@ -858,10 +858,9 @@ static const MemoryRegionOps serial_mm_ops[3] = {
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
qemu_irq irq, int baudbase, qemu_irq irq, int baudbase,
CharDriverState *chr, int ioregister, CharDriverState *chr, int ioregister,
int be) enum device_endian end)
{ {
SerialState *s; SerialState *s;
enum device_endian end;
s = g_malloc0(sizeof(SerialState)); s = g_malloc0(sizeof(SerialState));
@ -873,7 +872,6 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
serial_init_core(s); serial_init_core(s);
vmstate_register(NULL, base, &vmstate_serial, s); vmstate_register(NULL, base, &vmstate_serial, s);
end = (be ? DEVICE_BIG_ENDIAN : DEVICE_LITTLE_ENDIAN);
memory_region_init_io(&s->io, &serial_mm_ops[end], s, memory_region_init_io(&s->io, &serial_mm_ops[end], s,
"serial", 8 << it_shift); "serial", 8 << it_shift);
if (ioregister) { if (ioregister) {

8
hw/sm501.c
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@ -1440,15 +1440,9 @@ void sm501_init(uint32_t base, uint32_t local_mem_bytes, qemu_irq irq,
/* bridge to serial emulation module */ /* bridge to serial emulation module */
if (chr) { if (chr) {
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2, serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
NULL, /* TODO : chain irq to IRL */ NULL, /* TODO : chain irq to IRL */
115200, chr, 1, 1); 115200, chr, 1, DEVICE_NATIVE_ENDIAN);
#else
serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
NULL, /* TODO : chain irq to IRL */
115200, chr, 1, 0);
#endif
} }
/* create qemu graphic console */ /* create qemu graphic console */

2
hw/sun4u.c
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@ -771,7 +771,7 @@ static void sun4uv_init(ram_addr_t RAM_size,
i = 0; i = 0;
if (hwdef->console_serial_base) { if (hwdef->console_serial_base) {
serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
serial_hds[i], 1, 1); serial_hds[i], 1, DEVICE_BIG_ENDIAN);
i++; i++;
} }
for(; i < MAX_SERIAL_PORTS; i++) { for(; i < MAX_SERIAL_PORTS; i++) {

3
hw/virtex_ml507.c
View File

@ -226,7 +226,8 @@ static void virtex_init(ram_addr_t ram_size,
irq[i] = qdev_get_gpio_in(dev, i); irq[i] = qdev_get_gpio_in(dev, i);
} }
serial_mm_init(0x83e01003ULL, 2, irq[9], 115200, serial_hds[0], 1, 0); serial_mm_init(0x83e01003ULL, 2, irq[9], 115200, serial_hds[0],
1, DEVICE_LITTLE_ENDIAN);
/* 2 timers at irq 2 @ 62 Mhz. */ /* 2 timers at irq 2 @ 62 Mhz. */
xilinx_timer_create(0x83c00000, irq[3], 2, 62 * 1000000); xilinx_timer_create(0x83c00000, irq[3], 2, 62 * 1000000);