310 lines
8.5 KiB
C
310 lines
8.5 KiB
C
/*
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* Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Copyright (c) 2011 Linaro Limited
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* Written by Paul Brook, Peter Maydell
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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/* This device implements the per-cpu private timer and watchdog block
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* which is used in both the ARM11MPCore and Cortex-A9MP.
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*/
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#define MAX_CPUS 4
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/* State of a single timer or watchdog block */
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typedef struct {
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uint32_t count;
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uint32_t load;
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uint32_t control;
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uint32_t status;
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int64_t tick;
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QEMUTimer *timer;
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qemu_irq irq;
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MemoryRegion iomem;
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} TimerBlock;
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typedef struct {
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SysBusDevice busdev;
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uint32_t num_cpu;
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TimerBlock timerblock[MAX_CPUS];
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MemoryRegion iomem;
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} ARMMPTimerState;
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static inline int get_current_cpu(ARMMPTimerState *s)
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{
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CPUState *cpu_single_cpu = ENV_GET_CPU(cpu_single_env);
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if (cpu_single_cpu->cpu_index >= s->num_cpu) {
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hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n",
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s->num_cpu, cpu_single_cpu->cpu_index);
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}
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return cpu_single_cpu->cpu_index;
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}
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static inline void timerblock_update_irq(TimerBlock *tb)
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{
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qemu_set_irq(tb->irq, tb->status);
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}
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/* Return conversion factor from mpcore timer ticks to qemu timer ticks. */
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static inline uint32_t timerblock_scale(TimerBlock *tb)
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{
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return (((tb->control >> 8) & 0xff) + 1) * 10;
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}
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static void timerblock_reload(TimerBlock *tb, int restart)
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{
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if (tb->count == 0) {
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return;
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}
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if (restart) {
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tb->tick = qemu_get_clock_ns(vm_clock);
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}
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tb->tick += (int64_t)tb->count * timerblock_scale(tb);
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qemu_mod_timer(tb->timer, tb->tick);
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}
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static void timerblock_tick(void *opaque)
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{
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TimerBlock *tb = (TimerBlock *)opaque;
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tb->status = 1;
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if (tb->control & 2) {
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tb->count = tb->load;
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timerblock_reload(tb, 0);
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} else {
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tb->count = 0;
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}
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timerblock_update_irq(tb);
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}
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static uint64_t timerblock_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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TimerBlock *tb = (TimerBlock *)opaque;
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int64_t val;
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switch (addr) {
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case 0: /* Load */
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return tb->load;
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case 4: /* Counter. */
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if (((tb->control & 1) == 0) || (tb->count == 0)) {
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return 0;
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}
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/* Slow and ugly, but hopefully won't happen too often. */
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val = tb->tick - qemu_get_clock_ns(vm_clock);
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val /= timerblock_scale(tb);
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if (val < 0) {
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val = 0;
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}
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return val;
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case 8: /* Control. */
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return tb->control;
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case 12: /* Interrupt status. */
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return tb->status;
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default:
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return 0;
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}
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}
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static void timerblock_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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TimerBlock *tb = (TimerBlock *)opaque;
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int64_t old;
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switch (addr) {
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case 0: /* Load */
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tb->load = value;
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/* Fall through. */
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case 4: /* Counter. */
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if ((tb->control & 1) && tb->count) {
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/* Cancel the previous timer. */
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qemu_del_timer(tb->timer);
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}
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tb->count = value;
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if (tb->control & 1) {
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timerblock_reload(tb, 1);
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}
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break;
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case 8: /* Control. */
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old = tb->control;
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tb->control = value;
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if (((old & 1) == 0) && (value & 1)) {
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if (tb->count == 0 && (tb->control & 2)) {
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tb->count = tb->load;
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}
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timerblock_reload(tb, 1);
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}
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break;
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case 12: /* Interrupt status. */
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tb->status &= ~value;
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timerblock_update_irq(tb);
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break;
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}
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}
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/* Wrapper functions to implement the "read timer/watchdog for
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* the current CPU" memory regions.
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*/
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static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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ARMMPTimerState *s = (ARMMPTimerState *)opaque;
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int id = get_current_cpu(s);
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return timerblock_read(&s->timerblock[id], addr, size);
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}
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static void arm_thistimer_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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ARMMPTimerState *s = (ARMMPTimerState *)opaque;
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int id = get_current_cpu(s);
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timerblock_write(&s->timerblock[id], addr, value, size);
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}
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static const MemoryRegionOps arm_thistimer_ops = {
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.read = arm_thistimer_read,
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.write = arm_thistimer_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const MemoryRegionOps timerblock_ops = {
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.read = timerblock_read,
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.write = timerblock_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void timerblock_reset(TimerBlock *tb)
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{
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tb->count = 0;
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tb->load = 0;
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tb->control = 0;
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tb->status = 0;
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tb->tick = 0;
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if (tb->timer) {
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qemu_del_timer(tb->timer);
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}
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}
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static void arm_mptimer_reset(DeviceState *dev)
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{
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ARMMPTimerState *s =
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FROM_SYSBUS(ARMMPTimerState, SYS_BUS_DEVICE(dev));
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int i;
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for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) {
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timerblock_reset(&s->timerblock[i]);
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}
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}
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static int arm_mptimer_init(SysBusDevice *dev)
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{
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ARMMPTimerState *s = FROM_SYSBUS(ARMMPTimerState, dev);
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int i;
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if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) {
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hw_error("%s: num-cpu must be between 1 and %d\n", __func__, MAX_CPUS);
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}
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/* We implement one timer block per CPU, and expose multiple MMIO regions:
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* * region 0 is "timer for this core"
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* * region 1 is "timer for core 0"
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* * region 2 is "timer for core 1"
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* and so on.
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* The outgoing interrupt lines are
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* * timer for core 0
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* * timer for core 1
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* and so on.
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*/
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memory_region_init_io(&s->iomem, &arm_thistimer_ops, s,
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"arm_mptimer_timer", 0x20);
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sysbus_init_mmio(dev, &s->iomem);
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for (i = 0; i < s->num_cpu; i++) {
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TimerBlock *tb = &s->timerblock[i];
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tb->timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb);
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sysbus_init_irq(dev, &tb->irq);
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memory_region_init_io(&tb->iomem, &timerblock_ops, tb,
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"arm_mptimer_timerblock", 0x20);
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sysbus_init_mmio(dev, &tb->iomem);
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}
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return 0;
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}
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static const VMStateDescription vmstate_timerblock = {
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.name = "arm_mptimer_timerblock",
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(count, TimerBlock),
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VMSTATE_UINT32(load, TimerBlock),
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VMSTATE_UINT32(control, TimerBlock),
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VMSTATE_UINT32(status, TimerBlock),
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VMSTATE_INT64(tick, TimerBlock),
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VMSTATE_TIMER(timer, TimerBlock),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_arm_mptimer = {
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.name = "arm_mptimer",
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu,
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2, vmstate_timerblock, TimerBlock),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property arm_mptimer_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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static void arm_mptimer_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
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sbc->init = arm_mptimer_init;
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dc->vmsd = &vmstate_arm_mptimer;
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dc->reset = arm_mptimer_reset;
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dc->no_user = 1;
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dc->props = arm_mptimer_properties;
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}
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static const TypeInfo arm_mptimer_info = {
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.name = "arm_mptimer",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ARMMPTimerState),
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.class_init = arm_mptimer_class_init,
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};
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static void arm_mptimer_register_types(void)
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{
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type_register_static(&arm_mptimer_info);
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}
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type_init(arm_mptimer_register_types)
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