 e4ea952fb0
			
		
	
	
		e4ea952fb0
		
	
	
	
	
		
			
			Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-41-richard.henderson@linaro.org>
		
			
				
	
	
		
			141 lines
		
	
	
		
			4.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			141 lines
		
	
	
		
			4.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Allwinner H3 System Control emulation
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|  *
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|  * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
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|  *
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|  * This program is free software: you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License as published by
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|  * the Free Software Foundation, either version 2 of the License, or
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|  * (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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|  */
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| 
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| #include "qemu/osdep.h"
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| #include "qemu/units.h"
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| #include "hw/sysbus.h"
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| #include "migration/vmstate.h"
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| #include "qemu/log.h"
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| #include "qemu/module.h"
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| #include "hw/misc/allwinner-h3-sysctrl.h"
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| 
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| /* System Control register offsets */
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| enum {
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|     REG_VER               = 0x24,  /* Version */
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|     REG_EMAC_PHY_CLK      = 0x30,  /* EMAC PHY Clock */
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| };
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| 
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| #define REG_INDEX(offset)   (offset / sizeof(uint32_t))
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| 
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| /* System Control register reset values */
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| enum {
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|     REG_VER_RST           = 0x0,
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|     REG_EMAC_PHY_CLK_RST  = 0x58000,
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| };
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| 
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| static uint64_t allwinner_h3_sysctrl_read(void *opaque, hwaddr offset,
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|                                           unsigned size)
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| {
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|     const AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
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|     const uint32_t idx = REG_INDEX(offset);
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| 
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|     if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
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|         qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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|                       __func__, (uint32_t)offset);
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|         return 0;
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|     }
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| 
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|     return s->regs[idx];
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| }
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| 
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| static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset,
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|                                        uint64_t val, unsigned size)
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| {
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|     AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
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|     const uint32_t idx = REG_INDEX(offset);
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| 
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|     if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
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|         qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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|                       __func__, (uint32_t)offset);
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|         return;
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|     }
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| 
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|     switch (offset) {
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|     case REG_VER:       /* Version */
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|         break;
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|     default:
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|         s->regs[idx] = (uint32_t) val;
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|         break;
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|     }
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| }
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| 
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| static const MemoryRegionOps allwinner_h3_sysctrl_ops = {
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|     .read = allwinner_h3_sysctrl_read,
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|     .write = allwinner_h3_sysctrl_write,
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|     .endianness = DEVICE_NATIVE_ENDIAN,
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|     .valid = {
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|         .min_access_size = 4,
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|         .max_access_size = 4,
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|     },
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|     .impl.min_access_size = 4,
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| };
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| 
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| static void allwinner_h3_sysctrl_reset(DeviceState *dev)
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| {
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|     AwH3SysCtrlState *s = AW_H3_SYSCTRL(dev);
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| 
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|     /* Set default values for registers */
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|     s->regs[REG_INDEX(REG_VER)] = REG_VER_RST;
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|     s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST;
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| }
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| 
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| static void allwinner_h3_sysctrl_init(Object *obj)
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| {
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|     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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|     AwH3SysCtrlState *s = AW_H3_SYSCTRL(obj);
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| 
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|     /* Memory mapping */
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|     memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sysctrl_ops, s,
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|                            TYPE_AW_H3_SYSCTRL, 4 * KiB);
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|     sysbus_init_mmio(sbd, &s->iomem);
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| }
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| 
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| static const VMStateDescription allwinner_h3_sysctrl_vmstate = {
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|     .name = "allwinner-h3-sysctrl",
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|     .version_id = 1,
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|     .minimum_version_id = 1,
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|     .fields = (const VMStateField[]) {
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|         VMSTATE_UINT32_ARRAY(regs, AwH3SysCtrlState, AW_H3_SYSCTRL_REGS_NUM),
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|         VMSTATE_END_OF_LIST()
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|     }
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| };
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| 
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| static void allwinner_h3_sysctrl_class_init(ObjectClass *klass, void *data)
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| {
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|     DeviceClass *dc = DEVICE_CLASS(klass);
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| 
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|     dc->reset = allwinner_h3_sysctrl_reset;
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|     dc->vmsd = &allwinner_h3_sysctrl_vmstate;
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| }
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| 
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| static const TypeInfo allwinner_h3_sysctrl_info = {
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|     .name          = TYPE_AW_H3_SYSCTRL,
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|     .parent        = TYPE_SYS_BUS_DEVICE,
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|     .instance_init = allwinner_h3_sysctrl_init,
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|     .instance_size = sizeof(AwH3SysCtrlState),
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|     .class_init    = allwinner_h3_sysctrl_class_init,
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| };
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| 
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| static void allwinner_h3_sysctrl_register(void)
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| {
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|     type_register_static(&allwinner_h3_sysctrl_info);
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| }
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| 
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| type_init(allwinner_h3_sysctrl_register)
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