89b6b50892
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2114 c046a42c-6fe2-441c-8c8c-71466251a162
292 lines
7.7 KiB
C
292 lines
7.7 KiB
C
#include "vl.h"
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#define BIOS_FILENAME "mips_bios.bin"
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//#define BIOS_FILENAME "system.bin"
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#define KERNEL_LOAD_ADDR 0x80010000
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#define INITRD_LOAD_ADDR 0x80800000
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#define VIRT_TO_PHYS_ADDEND (-0x80000000LL)
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extern FILE *logfile;
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static PITState *pit;
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static void pic_irq_request(void *opaque, int level)
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{
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CPUState *env = first_cpu;
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if (level) {
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env->CP0_Cause |= 0x00000400;
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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} else {
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env->CP0_Cause &= ~0x00000400;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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}
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void cpu_mips_irqctrl_init (void)
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{
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}
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/* XXX: do not use a global */
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uint32_t cpu_mips_get_random (CPUState *env)
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{
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static uint32_t seed = 0;
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uint32_t idx;
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seed = seed * 314159 + 1;
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idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
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return idx;
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}
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/* MIPS R4K timer */
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uint32_t cpu_mips_get_count (CPUState *env)
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{
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return env->CP0_Count +
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(uint32_t)muldiv64(qemu_get_clock(vm_clock),
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100 * 1000 * 1000, ticks_per_sec);
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}
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static void cpu_mips_update_count (CPUState *env, uint32_t count,
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uint32_t compare)
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{
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uint64_t now, next;
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uint32_t tmp;
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tmp = count;
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if (count == compare)
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tmp++;
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now = qemu_get_clock(vm_clock);
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next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
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if (next == now)
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next++;
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#if 0
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if (logfile) {
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fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
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__func__, now, count, compare, next - now);
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}
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#endif
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/* Store new count and compare registers */
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env->CP0_Compare = compare;
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env->CP0_Count =
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count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
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/* Adjust timer */
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qemu_mod_timer(env->timer, next);
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}
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void cpu_mips_store_count (CPUState *env, uint32_t value)
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{
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cpu_mips_update_count(env, value, env->CP0_Compare);
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}
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void cpu_mips_store_compare (CPUState *env, uint32_t value)
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{
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cpu_mips_update_count(env, cpu_mips_get_count(env), value);
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env->CP0_Cause &= ~0x00008000;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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static void mips_timer_cb (void *opaque)
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{
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CPUState *env;
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env = opaque;
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#if 0
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if (logfile) {
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fprintf(logfile, "%s\n", __func__);
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}
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#endif
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cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
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env->CP0_Cause |= 0x00008000;
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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void cpu_mips_clock_init (CPUState *env)
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{
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env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
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env->CP0_Compare = 0;
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cpu_mips_update_count(env, 1, 0);
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}
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static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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#if 0
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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#endif
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cpu_outb(NULL, addr & 0xffff, value);
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}
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static uint32_t io_readb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inb(NULL, addr & 0xffff);
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#if 0
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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#endif
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return ret;
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}
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static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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#if 0
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap16(value);
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#endif
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cpu_outw(NULL, addr & 0xffff, value);
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}
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static uint32_t io_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inw(NULL, addr & 0xffff);
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap16(ret);
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#endif
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#if 0
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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#endif
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return ret;
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}
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static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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#if 0
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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cpu_outl(NULL, addr & 0xffff, value);
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}
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static uint32_t io_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inl(NULL, addr & 0xffff);
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap32(ret);
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#endif
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#if 0
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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#endif
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return ret;
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}
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CPUWriteMemoryFunc *io_write[] = {
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&io_writeb,
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&io_writew,
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&io_writel,
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};
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CPUReadMemoryFunc *io_read[] = {
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&io_readb,
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&io_readw,
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&io_readl,
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};
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void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename)
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{
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char buf[1024];
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int64_t entry = 0;
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unsigned long bios_offset;
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int io_memory;
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int ret;
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CPUState *env;
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long kernel_size;
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env = cpu_init();
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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/* Try to load a BIOS image. If this fails, we continue regardless,
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but initialize the hardware ourselves. When a kernel gets
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preloaded we also initialize the hardware, since the BIOS wasn't
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run. */
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bios_offset = ram_size + vga_ram_size;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
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ret = load_image(buf, phys_ram_base + bios_offset);
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if (ret == BIOS_SIZE) {
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cpu_register_physical_memory((uint32_t)(0x1fc00000),
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BIOS_SIZE, bios_offset | IO_MEM_ROM);
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} else {
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/* not fatal */
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fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
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buf);
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}
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kernel_size = 0;
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if (kernel_filename) {
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kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry);
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if (kernel_size >= 0)
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env->PC = entry;
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else {
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kernel_size = load_image(kernel_filename,
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phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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env->PC = KERNEL_LOAD_ADDR;
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}
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/* load initrd */
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if (initrd_filename) {
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if (load_image(initrd_filename,
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phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND)
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== (target_ulong) -1) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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}
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/* Store command line. */
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strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
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/* FIXME: little endian support */
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*(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
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*(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
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}
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/* Init internal devices */
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cpu_mips_clock_init(env);
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cpu_mips_irqctrl_init();
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/* Register 64 KB of ISA IO space at 0x14000000 */
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io_memory = cpu_register_io_memory(0, io_read, io_write, NULL);
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cpu_register_physical_memory(0x14000000, 0x00010000, io_memory);
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isa_mem_base = 0x10000000;
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isa_pic = pic_init(pic_irq_request, env);
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pit = pit_init(0x40, 0);
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serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
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isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
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vga_ram_size);
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if (nd_table[0].vlan) {
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if (nd_table[0].model == NULL
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|| strcmp(nd_table[0].model, "ne2k_isa") == 0) {
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isa_ne2000_init(0x300, 9, &nd_table[0]);
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
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exit (1);
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}
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}
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}
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QEMUMachine mips_machine = {
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"mips",
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"mips r4k platform",
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mips_r4k_init,
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};
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