9f70e83ae6
Documentation for IBM FSI model.
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg : - Removed source file list
- Fixed aspeed machine reference ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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4.9 KiB
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123 lines
4.9 KiB
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======================================
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IBM's Flexible Service Interface (FSI)
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======================================
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The QEMU FSI emulation implements hardware interfaces between ASPEED SOC, FSI
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master/slave and the end engine.
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FSI is a point-to-point two wire interface which is capable of supporting
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distances of up to 4 meters. FSI interfaces have been used successfully for
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many years in IBM servers to attach IBM Flexible Support Processors(FSP) to
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CPUs and IBM ASICs.
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FSI allows a service processor access to the internal buses of a host POWER
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processor to perform configuration or debugging. FSI has long existed in POWER
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processes and so comes with some baggage, including how it has been integrated
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into the ASPEED SoC.
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Working backwards from the POWER processor, the fundamental pieces of interest
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for the implementation are: (see the `FSI specification`_ for more details)
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1. The Common FRU Access Macro (CFAM), an address space containing various
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"engines" that drive accesses on buses internal and external to the POWER
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chip. Examples include the SBEFIFO and I2C masters. The engines hang off of
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an internal Local Bus (LBUS) which is described by the CFAM configuration
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block.
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2. The FSI slave: The slave is the terminal point of the FSI bus for FSI
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symbols addressed to it. Slaves can be cascaded off of one another. The
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slave's configuration registers appear in address space of the CFAM to
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which it is attached.
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3. The FSI master: A controller in the platform service processor (e.g. BMC)
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driving CFAM engine accesses into the POWER chip. At the hardware level
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FSI is a bit-based protocol supporting synchronous and DMA-driven accesses
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of engines in a CFAM.
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4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER
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processors. This now makes an appearance in the ASPEED SoC due to tight
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integration of the FSI master IP with the OPB, mainly the existence of an
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MMIO-mapping of the CFAM address straight onto a sub-region of the OPB
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address space.
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5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the
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AST2600. Hardware limitations prevent the OPB from being directly mapped
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into APB, so all accesses are indirect through the bridge.
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The LBUS is modelled to maintain the qdev bus hierarchy and to take advantages
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of the object model to automatically generate the CFAM configuration block.
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The configuration block presents engines in the order they are attached to the
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CFAM's LBUS. Engine implementations should subclass the LBusDevice and set the
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'config' member of LBusDeviceClass to match the engine's type.
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CFAM designs offer a lot of flexibility, for instance it is possible for a
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CFAM to be simultaneously driven from multiple FSI links. The modeling is not
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so complete; it's assumed that each CFAM is attached to a single FSI slave (as
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a consequence the CFAM subclasses the FSI slave).
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As for FSI, its symbols and wire-protocol are not modelled at all. This is not
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necessary to get FSI off the ground thanks to the mapping of the CFAM address
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space onto the OPB address space - the models follow this directly and map the
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CFAM memory region into the OPB's memory region.
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The following commands start the ``rainier-bmc`` machine with built-in FSI
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model. There are no model specific arguments. Please check this document to
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learn more about Aspeed ``rainier-bmc`` machine: (:doc:`../../system/arm/aspeed`)
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.. code-block:: console
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qemu-system-arm -M rainier-bmc -nographic \
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-kernel fitImage-linux.bin \
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-dtb aspeed-bmc-ibm-rainier.dtb \
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-initrd obmc-phosphor-initramfs.rootfs.cpio.xz \
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-drive file=obmc-phosphor-image.rootfs.wic.qcow2,if=sd,index=2 \
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-append "rootwait console=ttyS4,115200n8 root=PARTLABEL=rofs-a"
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The implementation appears as following in the qemu device tree:
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.. code-block:: console
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(qemu) info qtree
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bus: main-system-bus
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type System
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...
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dev: aspeed.apb2opb, id ""
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gpio-out "sysbus-irq" 1
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mmio 000000001e79b000/0000000000001000
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bus: opb.1
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type opb
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dev: fsi.master, id ""
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bus: fsi.bus.1
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type fsi.bus
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dev: cfam.config, id ""
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dev: cfam, id ""
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bus: lbus.1
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type lbus
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dev: scratchpad, id ""
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address = 0 (0x0)
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bus: opb.0
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type opb
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dev: fsi.master, id ""
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bus: fsi.bus.0
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type fsi.bus
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dev: cfam.config, id ""
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dev: cfam, id ""
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bus: lbus.0
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type lbus
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dev: scratchpad, id ""
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address = 0 (0x0)
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pdbg is a simple application to allow debugging of the host POWER processors
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from the BMC. (see the `pdbg source repository`_ for more details)
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.. code-block:: console
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root@p10bmc:~# pdbg -a getcfam 0x0
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p0: 0x0 = 0xc0022d15
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.. _FSI specification:
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https://openpowerfoundation.org/specifications/fsi/
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.. _pdbg source repository:
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https://github.com/open-power/pdbg
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