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		4f2fdb10b5
		
	
	
	
	
		
			
			pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset system/vl.c: Fix handling of '-serial none -serial something' target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array target/arm: Reinstate "vfp" property on AArch32 CPUs doc/sphinx/hxtool.py: add optional label argument to SRST directive hw/arm: Check for CPU types in machine_run_board_init() for various boards pci-host: designware: Limit value range of iATU viewport register hw/arm: Convert some DPRINTF macros to trace events and guest errors hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices hw/arm: Implement BCM2835 SPI Controller -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmW9C84ZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qS6D/wM0/JGEYfaadpuMEOAx4PG AnfScbPqVhx9J31P2Ks3VrB5F108aq/SaL2BmCb3BLF/ECChlhBXIjd7ukdHstts F1TvqtvLGDZQz6wSVUeB0YOvAjGa3vIskn+Xvk9e6Ne6PcXgVnxAof/cPsXUiYNy 6DJjNiLJ/a9Xgq9rjFO6vzW3AL95U6/FmD2F0pOotWXERhNhoyYVV6RtyeqKlDQP yFVk5h601YURk9PeNZn9zpOpZqjAM7PxyF3X50N3Sv+G0uoKSr6b+c3/fDJbJo3+ 0LXomEa8hdheQxm1dLY5OD0JX3bvYxwH41bDg9B0iEdjxUdXt6LfXI9Nvw9BAwix 8AcGJJUaL4XU4uPfHBpRJApM15+MRb0hqfv4ZcGk8e67IIqVeDbKL2clTQGoHSg1 KaB0POhtFx//M/uBOyk/FR2gb2eBNU8GuoCgxdDwh0K5ylcaK1YPiX4Tcglu4iS0 Frvazphb2pO1BK6JiJwN2/9ezzDkDJqTKoSqdc4g3ETVOGnxr+tXwcds3t2iK3g2 y+pgijDOAT3bJO5kYeGvhoEJPKqXwJ3UQ8zTJsU2XSYwBjIyv5V3oOn6elwYJaWq yUDTC3QEK61KfnQnfTyLfdGWX1aVzHnYLWmQdO+3cczuQU0s0MP246Z1GAgDtgvD jGjDBz6mryWvP2H0xSmERQ== =azdP -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target/arm: fix exception syndrome for AArch32 bkpt insn pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset system/vl.c: Fix handling of '-serial none -serial something' target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array target/arm: Reinstate "vfp" property on AArch32 CPUs doc/sphinx/hxtool.py: add optional label argument to SRST directive hw/arm: Check for CPU types in machine_run_board_init() for various boards pci-host: designware: Limit value range of iATU viewport register hw/arm: Convert some DPRINTF macros to trace events and guest errors hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices hw/arm: Implement BCM2835 SPI Controller # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmW9C84ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qS6D/wM0/JGEYfaadpuMEOAx4PG # AnfScbPqVhx9J31P2Ks3VrB5F108aq/SaL2BmCb3BLF/ECChlhBXIjd7ukdHstts # F1TvqtvLGDZQz6wSVUeB0YOvAjGa3vIskn+Xvk9e6Ne6PcXgVnxAof/cPsXUiYNy # 6DJjNiLJ/a9Xgq9rjFO6vzW3AL95U6/FmD2F0pOotWXERhNhoyYVV6RtyeqKlDQP # yFVk5h601YURk9PeNZn9zpOpZqjAM7PxyF3X50N3Sv+G0uoKSr6b+c3/fDJbJo3+ # 0LXomEa8hdheQxm1dLY5OD0JX3bvYxwH41bDg9B0iEdjxUdXt6LfXI9Nvw9BAwix # 8AcGJJUaL4XU4uPfHBpRJApM15+MRb0hqfv4ZcGk8e67IIqVeDbKL2clTQGoHSg1 # KaB0POhtFx//M/uBOyk/FR2gb2eBNU8GuoCgxdDwh0K5ylcaK1YPiX4Tcglu4iS0 # Frvazphb2pO1BK6JiJwN2/9ezzDkDJqTKoSqdc4g3ETVOGnxr+tXwcds3t2iK3g2 # y+pgijDOAT3bJO5kYeGvhoEJPKqXwJ3UQ8zTJsU2XSYwBjIyv5V3oOn6elwYJaWq # yUDTC3QEK61KfnQnfTyLfdGWX1aVzHnYLWmQdO+3cczuQU0s0MP246Z1GAgDtgvD # jGjDBz6mryWvP2H0xSmERQ== # =azdP # -----END PGP SIGNATURE----- # gpg: Signature made Fri 02 Feb 2024 15:35:42 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/arm: Connect SPI Controller to BCM2835 hw/ssi: Implement BCM2835 SPI Controller tests/qtest: Adding PCS Module test to GMAC Qtest hw/net: GMAC Tx Implementation hw/net: GMAC Rx Implementation tests/qtest: Creating qtest for GMAC Module hw/arm: Add GMAC devices to NPCM7XX SoC hw/net: Add NPCMXXX GMAC device hw/xen: convert stderr prints to error/warn reports hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports hw/arm/z2: convert DPRINTF to trace events and guest errors hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors pci-host: designware: Limit value range of iATU viewport register hw/arm/zynq: Check for CPU types in machine_run_board_init() hw/arm/vexpress: Check for CPU types in machine_run_board_init() hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[] hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[] hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[] ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
		
			
				
	
	
		
			202 lines
		
	
	
		
			6.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			202 lines
		
	
	
		
			6.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  *  Samsung exynos4 SoC based boards emulation
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|  *
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|  *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
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|  *    Maksim Kozlov <m.kozlov@samsung.com>
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|  *    Evgeny Voevodin <e.voevodin@samsung.com>
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|  *    Igor Mitsyanko  <i.mitsyanko@samsung.com>
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|  *
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|  *  This program is free software; you can redistribute it and/or modify it
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|  *  under the terms of the GNU General Public License as published by the
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|  *  Free Software Foundation; either version 2 of the License, or
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|  *  (at your option) any later version.
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|  *
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|  *  This program is distributed in the hope that it will be useful, but WITHOUT
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|  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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|  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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|  *  for more details.
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|  *
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|  *  You should have received a copy of the GNU General Public License along
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|  *  with this program; if not, see <http://www.gnu.org/licenses/>.
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|  *
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|  */
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| 
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| #include "qemu/osdep.h"
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| #include "qemu/units.h"
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| #include "qapi/error.h"
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| #include "qemu/error-report.h"
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| #include "hw/sysbus.h"
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| #include "net/net.h"
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| #include "hw/arm/boot.h"
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| #include "exec/address-spaces.h"
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| #include "hw/arm/exynos4210.h"
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| #include "hw/net/lan9118.h"
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| #include "hw/qdev-properties.h"
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| #include "hw/boards.h"
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| #include "hw/irq.h"
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| #include "target/arm/cpu-qom.h"
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| 
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| #define SMDK_LAN9118_BASE_ADDR      0x05000000
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| 
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| typedef enum Exynos4BoardType {
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|     EXYNOS4_BOARD_NURI,
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|     EXYNOS4_BOARD_SMDKC210,
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|     EXYNOS4_NUM_OF_BOARDS
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| } Exynos4BoardType;
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| 
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| typedef struct Exynos4BoardState {
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|     Exynos4210State soc;
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|     MemoryRegion dram0_mem;
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|     MemoryRegion dram1_mem;
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| } Exynos4BoardState;
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| 
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| static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = {
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|     [EXYNOS4_BOARD_NURI]     = 0xD33,
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|     [EXYNOS4_BOARD_SMDKC210] = 0xB16,
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| };
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| 
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| static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
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|     [EXYNOS4_BOARD_NURI]     = EXYNOS4210_SECOND_CPU_BOOTREG,
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|     [EXYNOS4_BOARD_SMDKC210] = EXYNOS4210_SECOND_CPU_BOOTREG,
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| };
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| 
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| static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
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|     [EXYNOS4_BOARD_NURI]     = 1 * GiB,
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|     [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
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| };
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| 
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| static struct arm_boot_info exynos4_board_binfo = {
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|     .loader_start     = EXYNOS4210_BASE_BOOT_ADDR,
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|     .smp_loader_start = EXYNOS4210_SMP_BOOT_ADDR,
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|     .write_secondary_boot = exynos4210_write_secondary,
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| };
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| 
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| static void lan9215_init(uint32_t base, qemu_irq irq)
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| {
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|     DeviceState *dev;
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|     SysBusDevice *s;
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| 
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|     /* This should be a 9215 but the 9118 is close enough */
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|     dev = qemu_create_nic_device(TYPE_LAN9118, true, NULL);
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|     if (dev) {
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|         qdev_prop_set_uint32(dev, "mode_16bit", 1);
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|         s = SYS_BUS_DEVICE(dev);
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|         sysbus_realize_and_unref(s, &error_fatal);
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|         sysbus_mmio_map(s, 0, base);
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|         sysbus_connect_irq(s, 0, irq);
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|     }
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| }
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| 
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| static void exynos4_boards_init_ram(Exynos4BoardState *s,
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|                                     MemoryRegion *system_mem,
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|                                     unsigned long ram_size)
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| {
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|     unsigned long mem_size = ram_size;
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| 
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|     if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
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|         memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
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|                                mem_size - EXYNOS4210_DRAM_MAX_SIZE,
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|                                &error_fatal);
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|         memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
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|                                     &s->dram1_mem);
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|         mem_size = EXYNOS4210_DRAM_MAX_SIZE;
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|     }
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| 
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|     memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
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|                            &error_fatal);
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|     memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
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|                                 &s->dram0_mem);
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| }
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| 
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| static Exynos4BoardState *
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| exynos4_boards_init_common(MachineState *machine,
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|                            Exynos4BoardType board_type)
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| {
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|     Exynos4BoardState *s = g_new(Exynos4BoardState, 1);
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| 
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|     exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
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|     exynos4_board_binfo.board_id = exynos4_board_id[board_type];
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|     exynos4_board_binfo.smp_bootreg_addr =
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|             exynos4_board_smp_bootreg_addr[board_type];
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|     exynos4_board_binfo.gic_cpu_if_addr =
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|             EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
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| 
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|     exynos4_boards_init_ram(s, get_system_memory(),
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|                             exynos4_board_ram_size[board_type]);
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| 
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|     object_initialize_child(OBJECT(machine), "soc", &s->soc,
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|                             TYPE_EXYNOS4210_SOC);
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|     sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
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| 
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|     return s;
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| }
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| 
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| static void nuri_init(MachineState *machine)
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| {
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|     Exynos4BoardState *s = exynos4_boards_init_common(machine,
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|                                                       EXYNOS4_BOARD_NURI);
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| 
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|     arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo);
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| }
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| 
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| static void smdkc210_init(MachineState *machine)
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| {
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|     Exynos4BoardState *s = exynos4_boards_init_common(machine,
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|                                                       EXYNOS4_BOARD_SMDKC210);
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| 
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|     lan9215_init(SMDK_LAN9118_BASE_ADDR,
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|             qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
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|     arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo);
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| }
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| 
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| static const char * const valid_cpu_types[] = {
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|     ARM_CPU_TYPE_NAME("cortex-a9"),
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|     NULL
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| };
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| 
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| static void nuri_class_init(ObjectClass *oc, void *data)
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| {
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|     MachineClass *mc = MACHINE_CLASS(oc);
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| 
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|     mc->desc = "Samsung NURI board (Exynos4210)";
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|     mc->init = nuri_init;
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|     mc->valid_cpu_types = valid_cpu_types;
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|     mc->max_cpus = EXYNOS4210_NCPUS;
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|     mc->min_cpus = EXYNOS4210_NCPUS;
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|     mc->default_cpus = EXYNOS4210_NCPUS;
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|     mc->ignore_memory_transaction_failures = true;
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| }
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| 
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| static const TypeInfo nuri_type = {
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|     .name = MACHINE_TYPE_NAME("nuri"),
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|     .parent = TYPE_MACHINE,
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|     .class_init = nuri_class_init,
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| };
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| 
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| static void smdkc210_class_init(ObjectClass *oc, void *data)
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| {
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|     MachineClass *mc = MACHINE_CLASS(oc);
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| 
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|     mc->desc = "Samsung SMDKC210 board (Exynos4210)";
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|     mc->init = smdkc210_init;
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|     mc->valid_cpu_types = valid_cpu_types;
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|     mc->max_cpus = EXYNOS4210_NCPUS;
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|     mc->min_cpus = EXYNOS4210_NCPUS;
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|     mc->default_cpus = EXYNOS4210_NCPUS;
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|     mc->ignore_memory_transaction_failures = true;
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| }
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| 
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| static const TypeInfo smdkc210_type = {
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|     .name = MACHINE_TYPE_NAME("smdkc210"),
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|     .parent = TYPE_MACHINE,
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|     .class_init = smdkc210_class_init,
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| };
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| 
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| static void exynos4_machines_init(void)
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| {
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|     type_register_static(&nuri_type);
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|     type_register_static(&smdkc210_type);
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| }
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| 
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| type_init(exynos4_machines_init)
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