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			The SYSCFG input GPIOs aren't connected yet. When the STM32L4x5 GPIO device will be implemented, its output GPIOs will be connected to the SYSCFG input GPIOs. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240109194438.70934-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
		
			
				
	
	
		
			63 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			63 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * STM32L4x5 SoC family
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|  *
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|  * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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|  * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
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|  *
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|  * SPDX-License-Identifier: GPL-2.0-or-later
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|  *
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|  * This work is licensed under the terms of the GNU GPL, version 2 or later.
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|  * See the COPYING file in the top-level directory.
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|  *
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|  * This work is heavily inspired by the stm32f405_soc by Alistair Francis.
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|  * Original code is licensed under the MIT License:
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|  *
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|  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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|  */
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| 
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| /*
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|  * The reference used is the STMicroElectronics RM0351 Reference manual
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|  * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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|  * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
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|  */
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| 
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| #ifndef HW_ARM_STM32L4x5_SOC_H
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| #define HW_ARM_STM32L4x5_SOC_H
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| 
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| #include "exec/memory.h"
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| #include "hw/arm/armv7m.h"
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| #include "hw/misc/stm32l4x5_syscfg.h"
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| #include "hw/misc/stm32l4x5_exti.h"
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| #include "qom/object.h"
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| 
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| #define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
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| #define TYPE_STM32L4X5XC_SOC "stm32l4x5xc-soc"
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| #define TYPE_STM32L4X5XE_SOC "stm32l4x5xe-soc"
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| #define TYPE_STM32L4X5XG_SOC "stm32l4x5xg-soc"
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| OBJECT_DECLARE_TYPE(Stm32l4x5SocState, Stm32l4x5SocClass, STM32L4X5_SOC)
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| 
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| struct Stm32l4x5SocState {
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|     SysBusDevice parent_obj;
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| 
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|     ARMv7MState armv7m;
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| 
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|     Stm32l4x5ExtiState exti;
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|     Stm32l4x5SyscfgState syscfg;
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| 
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|     MemoryRegion sram1;
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|     MemoryRegion sram2;
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|     MemoryRegion flash;
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|     MemoryRegion flash_alias;
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| 
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|     Clock *sysclk;
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|     Clock *refclk;
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| };
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| 
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| struct Stm32l4x5SocClass {
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|     SysBusDeviceClass parent_class;
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| 
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|     size_t flash_size;
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| };
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| 
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| #endif
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