642ba89672
The code already tries to do some endianness handling here, but currently fails badly: - While it already swaps the data when logging errors / tracing, it fails to byteswap the value before e.g. accessing entry->irte.present - entry->irte.source_id is swapped with le32_to_cpu(), though this is a 16-bit value - The whole union is apparently supposed to be swapped via the 64-bit data[2] array, but the struct is a mixture between 32 bit values (the first 8 bytes) and 64 bit values (the second 8 bytes), so this cannot work as expected. Fix it by converting the struct to two proper 64-bit bitfields, and by swapping the values only once for everybody right after reading the data from memory. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20230802135723.178083-3-thuth@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com>
321 lines
12 KiB
C
321 lines
12 KiB
C
/*
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* QEMU emulation of an Intel IOMMU (VT-d)
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* (DMA Remapping device)
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*
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* Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
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* Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef INTEL_IOMMU_H
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#define INTEL_IOMMU_H
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#include "hw/i386/x86-iommu.h"
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#include "qemu/iova-tree.h"
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#include "qom/object.h"
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#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
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OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_DEVICE)
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#define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
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/* DMAR Hardware Unit Definition address (IOMMU unit) */
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#define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
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#define VTD_PCI_BUS_MAX 256
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#define VTD_PCI_SLOT_MAX 32
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#define VTD_PCI_FUNC_MAX 8
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#define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
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#define VTD_PCI_FUNC(devfn) ((devfn) & 0x07)
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#define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff)
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#define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff)
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#define DMAR_REG_SIZE 0x230
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#define VTD_HOST_AW_39BIT 39
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#define VTD_HOST_AW_48BIT 48
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#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT
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#define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
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#define DMAR_REPORT_F_INTR (1)
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#define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL)
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#define VTD_MSI_ADDR_HI_SHIFT (32)
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#define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL)
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typedef struct VTDContextEntry VTDContextEntry;
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typedef struct VTDContextCacheEntry VTDContextCacheEntry;
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typedef struct VTDAddressSpace VTDAddressSpace;
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typedef struct VTDIOTLBEntry VTDIOTLBEntry;
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typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
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typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
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typedef struct VTDPASIDDirEntry VTDPASIDDirEntry;
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typedef struct VTDPASIDEntry VTDPASIDEntry;
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/* Context-Entry */
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struct VTDContextEntry {
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union {
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struct {
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uint64_t lo;
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uint64_t hi;
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};
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struct {
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uint64_t val[4];
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};
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};
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};
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struct VTDContextCacheEntry {
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/* The cache entry is obsolete if
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* context_cache_gen!=IntelIOMMUState.context_cache_gen
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*/
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uint32_t context_cache_gen;
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struct VTDContextEntry context_entry;
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};
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/* PASID Directory Entry */
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struct VTDPASIDDirEntry {
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uint64_t val;
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};
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/* PASID Table Entry */
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struct VTDPASIDEntry {
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uint64_t val[8];
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};
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struct VTDAddressSpace {
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PCIBus *bus;
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uint8_t devfn;
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uint32_t pasid;
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AddressSpace as;
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IOMMUMemoryRegion iommu;
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MemoryRegion root; /* The root container of the device */
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MemoryRegion nodmar; /* The alias of shared nodmar MR */
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MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */
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MemoryRegion iommu_ir_fault; /* Interrupt region for catching fault */
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IntelIOMMUState *iommu_state;
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VTDContextCacheEntry context_cache_entry;
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QLIST_ENTRY(VTDAddressSpace) next;
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/* Superset of notifier flags that this address space has */
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IOMMUNotifierFlag notifier_flags;
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/*
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* @iova_tree traces mapped IOVA ranges.
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*
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* The tree is not needed if no MAP notifier is registered with current
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* VTD address space, because all guest invalidate commands can be
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* directly passed to the IOMMU UNMAP notifiers without any further
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* reshuffling.
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*
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* The tree OTOH is required for MAP typed iommu notifiers for a few
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* reasons.
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*
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* Firstly, there's no way to identify whether an PSI (Page Selective
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* Invalidations) or DSI (Domain Selective Invalidations) event is an
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* MAP or UNMAP event within the message itself. Without having prior
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* knowledge of existing state vIOMMU doesn't know whether it should
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* notify MAP or UNMAP for a PSI message it received when caching mode
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* is enabled (for MAP notifiers).
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*
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* Secondly, PSI messages received from guest driver can be enlarged in
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* range, covers but not limited to what the guest driver wanted to
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* invalidate. When the range to invalidates gets bigger than the
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* limit of a PSI message, it can even become a DSI which will
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* invalidate the whole domain. If the vIOMMU directly notifies the
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* registered device with the unmodified range, it may confuse the
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* registered drivers (e.g. vfio-pci) on either:
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*
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* (1) Trying to map the same region more than once (for
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* VFIO_IOMMU_MAP_DMA, -EEXIST will trigger), or,
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*
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* (2) Trying to UNMAP a range that is still partially mapped.
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*
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* That accuracy is not required for UNMAP-only notifiers, but it is a
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* must-to-have for notifiers registered with MAP events, because the
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* vIOMMU needs to make sure the shadow page table is always in sync
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* with the guest IOMMU pgtables for a device.
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*/
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IOVATree *iova_tree;
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};
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struct VTDIOTLBEntry {
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uint64_t gfn;
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uint16_t domain_id;
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uint32_t pasid;
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uint64_t slpte;
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uint64_t mask;
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uint8_t access_flags;
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};
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/* VT-d Source-ID Qualifier types */
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enum {
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VTD_SQ_FULL = 0x00, /* Full SID verification */
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VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */
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VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */
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VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */
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VTD_SQ_MAX,
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};
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/* VT-d Source Validation Types */
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enum {
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VTD_SVT_NONE = 0x00, /* No validation */
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VTD_SVT_ALL = 0x01, /* Do full validation */
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VTD_SVT_BUS = 0x02, /* Validate bus range */
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VTD_SVT_MAX,
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};
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/* Interrupt Remapping Table Entry Definition */
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union VTD_IR_TableEntry {
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struct {
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#if HOST_BIG_ENDIAN
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uint64_t dest_id:32; /* Destination ID */
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uint64_t __reserved_1:8; /* Reserved 1 */
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uint64_t vector:8; /* Interrupt Vector */
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uint64_t irte_mode:1; /* IRTE Mode */
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uint64_t __reserved_0:3; /* Reserved 0 */
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uint64_t __avail:4; /* Available spaces for software */
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uint64_t delivery_mode:3; /* Delivery Mode */
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uint64_t trigger_mode:1; /* Trigger Mode */
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uint64_t redir_hint:1; /* Redirection Hint */
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uint64_t dest_mode:1; /* Destination Mode */
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uint64_t fault_disable:1; /* Fault Processing Disable */
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uint64_t present:1; /* Whether entry present/available */
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#else
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uint64_t present:1; /* Whether entry present/available */
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uint64_t fault_disable:1; /* Fault Processing Disable */
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uint64_t dest_mode:1; /* Destination Mode */
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uint64_t redir_hint:1; /* Redirection Hint */
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uint64_t trigger_mode:1; /* Trigger Mode */
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uint64_t delivery_mode:3; /* Delivery Mode */
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uint64_t __avail:4; /* Available spaces for software */
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uint64_t __reserved_0:3; /* Reserved 0 */
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uint64_t irte_mode:1; /* IRTE Mode */
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uint64_t vector:8; /* Interrupt Vector */
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uint64_t __reserved_1:8; /* Reserved 1 */
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uint64_t dest_id:32; /* Destination ID */
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#endif
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#if HOST_BIG_ENDIAN
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uint64_t __reserved_2:44; /* Reserved 2 */
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uint64_t sid_vtype:2; /* Source-ID Validation Type */
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uint64_t sid_q:2; /* Source-ID Qualifier */
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uint64_t source_id:16; /* Source-ID */
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#else
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uint64_t source_id:16; /* Source-ID */
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uint64_t sid_q:2; /* Source-ID Qualifier */
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uint64_t sid_vtype:2; /* Source-ID Validation Type */
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uint64_t __reserved_2:44; /* Reserved 2 */
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#endif
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} QEMU_PACKED irte;
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uint64_t data[2];
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};
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#define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */
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#define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */
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/* Programming format for MSI/MSI-X addresses */
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union VTD_IR_MSIAddress {
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struct {
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#if HOST_BIG_ENDIAN
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uint32_t __head:12; /* Should always be: 0x0fee */
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uint32_t index_l:15; /* Interrupt index bit 14-0 */
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uint32_t int_mode:1; /* Interrupt format */
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uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
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uint32_t index_h:1; /* Interrupt index bit 15 */
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uint32_t __not_care:2;
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#else
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uint32_t __not_care:2;
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uint32_t index_h:1; /* Interrupt index bit 15 */
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uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
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uint32_t int_mode:1; /* Interrupt format */
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uint32_t index_l:15; /* Interrupt index bit 14-0 */
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uint32_t __head:12; /* Should always be: 0x0fee */
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#endif
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} QEMU_PACKED addr;
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uint32_t data;
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};
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/* When IR is enabled, all MSI/MSI-X data bits should be zero */
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#define VTD_IR_MSI_DATA (0)
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/* The iommu (DMAR) device state struct */
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struct IntelIOMMUState {
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X86IOMMUState x86_iommu;
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MemoryRegion csrmem;
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MemoryRegion mr_nodmar;
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MemoryRegion mr_ir;
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MemoryRegion mr_sys_alias;
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uint8_t csr[DMAR_REG_SIZE]; /* register values */
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uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */
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uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
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uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */
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uint32_t version;
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bool caching_mode; /* RO - is cap CM enabled? */
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bool scalable_mode; /* RO - is Scalable Mode supported? */
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bool snoop_control; /* RO - is SNP filed supported? */
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dma_addr_t root; /* Current root table pointer */
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bool root_scalable; /* Type of root table (scalable or not) */
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bool dmar_enabled; /* Set if DMA remapping is enabled */
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uint16_t iq_head; /* Current invalidation queue head */
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uint16_t iq_tail; /* Current invalidation queue tail */
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dma_addr_t iq; /* Current invalidation queue pointer */
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uint16_t iq_size; /* IQ Size in number of entries */
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bool iq_dw; /* IQ descriptor width 256bit or not */
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bool qi_enabled; /* Set if the QI is enabled */
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uint8_t iq_last_desc_type; /* The type of last completed descriptor */
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/* The index of the Fault Recording Register to be used next.
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* Wraps around from N-1 to 0, where N is the number of FRCD_REG.
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*/
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uint16_t next_frcd_reg;
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uint64_t cap; /* The value of capability reg */
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uint64_t ecap; /* The value of extended capability reg */
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uint32_t context_cache_gen; /* Should be in [1,MAX] */
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GHashTable *iotlb; /* IOTLB */
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GHashTable *vtd_address_spaces; /* VTD address spaces */
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VTDAddressSpace *vtd_as_cache[VTD_PCI_BUS_MAX]; /* VTD address space cache */
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/* list of registered notifiers */
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QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;
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/* interrupt remapping */
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bool intr_enabled; /* Whether guest enabled IR */
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dma_addr_t intr_root; /* Interrupt remapping table pointer */
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uint32_t intr_size; /* Number of IR table entries */
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bool intr_eime; /* Extended interrupt mode enabled */
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OnOffAuto intr_eim; /* Toggle for EIM cabability */
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bool buggy_eim; /* Force buggy EIM unless eim=off */
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uint8_t aw_bits; /* Host/IOVA address width (in bits) */
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bool dma_drain; /* Whether DMA r/w draining enabled */
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bool dma_translation; /* Whether DMA translation supported */
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bool pasid; /* Whether to support PASID */
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/*
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* Protects IOMMU states in general. Currently it protects the
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* per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.
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*/
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QemuMutex iommu_lock;
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};
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/* Find the VTD Address space associated with the given bus pointer,
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* create a new one if none exists
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*/
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VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus,
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int devfn, unsigned int pasid);
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#endif
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