2152e48b50
Move some macros out of `vector_helper` and into `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20230711165917.2629866-8-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
229 lines
8.1 KiB
C
229 lines
8.1 KiB
C
/*
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* RISC-V Vector Extension Internals
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*
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* Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TARGET_RISCV_VECTOR_INTERNALS_H
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#define TARGET_RISCV_VECTOR_INTERNALS_H
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "cpu.h"
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#include "tcg/tcg-gvec-desc.h"
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#include "internals.h"
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static inline uint32_t vext_nf(uint32_t desc)
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{
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return FIELD_EX32(simd_data(desc), VDATA, NF);
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}
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/*
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* Note that vector data is stored in host-endian 64-bit chunks,
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* so addressing units smaller than that needs a host-endian fixup.
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*/
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#if HOST_BIG_ENDIAN
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#define H1(x) ((x) ^ 7)
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#define H1_2(x) ((x) ^ 6)
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#define H1_4(x) ((x) ^ 4)
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#define H2(x) ((x) ^ 3)
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#define H4(x) ((x) ^ 1)
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#define H8(x) ((x))
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#else
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#define H1(x) (x)
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#define H1_2(x) (x)
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#define H1_4(x) (x)
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#define H2(x) (x)
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#define H4(x) (x)
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#define H8(x) (x)
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#endif
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/*
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* Encode LMUL to lmul as following:
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* LMUL vlmul lmul
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* 1 000 0
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* 2 001 1
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* 4 010 2
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* 8 011 3
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* - 100 -
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* 1/8 101 -3
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* 1/4 110 -2
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* 1/2 111 -1
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*/
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static inline int32_t vext_lmul(uint32_t desc)
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{
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return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
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}
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static inline uint32_t vext_vm(uint32_t desc)
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{
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return FIELD_EX32(simd_data(desc), VDATA, VM);
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}
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static inline uint32_t vext_vma(uint32_t desc)
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{
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return FIELD_EX32(simd_data(desc), VDATA, VMA);
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}
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static inline uint32_t vext_vta(uint32_t desc)
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{
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return FIELD_EX32(simd_data(desc), VDATA, VTA);
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}
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static inline uint32_t vext_vta_all_1s(uint32_t desc)
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{
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return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S);
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}
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/*
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* Earlier designs (pre-0.9) had a varying number of bits
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* per mask value (MLEN). In the 0.9 design, MLEN=1.
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* (Section 4.5)
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*/
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static inline int vext_elem_mask(void *v0, int index)
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{
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int idx = index / 64;
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int pos = index % 64;
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return (((uint64_t *)v0)[idx] >> pos) & 1;
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}
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/*
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* Get number of total elements, including prestart, body and tail elements.
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* Note that when LMUL < 1, the tail includes the elements past VLMAX that
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* are held in the same vector register.
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*/
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static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
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uint32_t esz)
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{
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uint32_t vlenb = simd_maxsz(desc);
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uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
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int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 :
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ctzl(esz) - ctzl(sew) + vext_lmul(desc);
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return (vlenb << emul) / esz;
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}
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/* set agnostic elements to 1s */
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void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
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uint32_t tot);
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/* expand macro args before macro */
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#define RVVCALL(macro, ...) macro(__VA_ARGS__)
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/* (TD, T2, TX2) */
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#define OP_UU_B uint8_t, uint8_t, uint8_t
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#define OP_UU_H uint16_t, uint16_t, uint16_t
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#define OP_UU_W uint32_t, uint32_t, uint32_t
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#define OP_UU_D uint64_t, uint64_t, uint64_t
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/* (TD, T1, T2, TX1, TX2) */
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#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t
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#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
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#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
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#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
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#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
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static void do_##NAME(void *vd, void *vs2, int i) \
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{ \
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TX2 s2 = *((T2 *)vs2 + HS2(i)); \
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*((TD *)vd + HD(i)) = OP(s2); \
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}
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#define GEN_VEXT_V(NAME, ESZ) \
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void HELPER(NAME)(void *vd, void *v0, void *vs2, \
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CPURISCVState *env, uint32_t desc) \
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{ \
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uint32_t vm = vext_vm(desc); \
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uint32_t vl = env->vl; \
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uint32_t total_elems = \
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vext_get_total_elems(env, desc, ESZ); \
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uint32_t vta = vext_vta(desc); \
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uint32_t vma = vext_vma(desc); \
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uint32_t i; \
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\
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for (i = env->vstart; i < vl; i++) { \
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if (!vm && !vext_elem_mask(v0, i)) { \
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/* set masked-off elements to 1s */ \
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vext_set_elems_1s(vd, vma, i * ESZ, \
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(i + 1) * ESZ); \
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continue; \
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} \
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do_##NAME(vd, vs2, i); \
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} \
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env->vstart = 0; \
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/* set tail elements to 1s */ \
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vext_set_elems_1s(vd, vta, vl * ESZ, \
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total_elems * ESZ); \
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}
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/* operation of two vector elements */
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typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
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#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
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static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
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{ \
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TX1 s1 = *((T1 *)vs1 + HS1(i)); \
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TX2 s2 = *((T2 *)vs2 + HS2(i)); \
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*((TD *)vd + HD(i)) = OP(s2, s1); \
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}
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void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
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CPURISCVState *env, uint32_t desc,
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opivv2_fn *fn, uint32_t esz);
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/* generate the helpers for OPIVV */
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#define GEN_VEXT_VV(NAME, ESZ) \
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void HELPER(NAME)(void *vd, void *v0, void *vs1, \
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void *vs2, CPURISCVState *env, \
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uint32_t desc) \
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{ \
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do_vext_vv(vd, v0, vs1, vs2, env, desc, \
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do_##NAME, ESZ); \
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}
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typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
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/*
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* (T1)s1 gives the real operator type.
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* (TX1)(T1)s1 expands the operator type of widen or narrow operations.
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*/
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#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
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static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \
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{ \
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TX2 s2 = *((T2 *)vs2 + HS2(i)); \
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*((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \
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}
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void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
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CPURISCVState *env, uint32_t desc,
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opivx2_fn fn, uint32_t esz);
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/* generate the helpers for OPIVX */
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#define GEN_VEXT_VX(NAME, ESZ) \
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void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
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void *vs2, CPURISCVState *env, \
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uint32_t desc) \
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{ \
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do_vext_vx(vd, v0, s1, vs2, env, desc, \
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do_##NAME, ESZ); \
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}
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/* Three of the widening shortening macros: */
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/* (TD, T1, T2, TX1, TX2) */
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#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
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#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
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#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
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#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
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