ca4d5d862d
In CPUSparcState we define the fprs field as uint64_t. However we then refer to it in translate.c via a TCGv_i32 which we set up with tcg_global_mem_new_ptr(). This means that on a big-endian host when the guest does something to writo te the FPRS register this value ends up in the wrong half of the uint64_t, and the QEMU C code that refers to env->fprs sees the wrong value. The effect of this is that guest code that enables the FPU crashes with spurious FPU Disabled exceptions. In particular, this is why tests/avocado/machine_sparc64_sun4u.py:Sun4uMachine.test_sparc64_sun4u times out on an s390 host. There are multiple ways we could fix this; since there are actually only three bits in the FPRS register and the code in translate.c would be a bit painful to convert to dealing with a TCGv_i64, change the type of the CPU state struct field to match what translate.c is expecting. (None of the other fields referenced by the r32[] array in sparc_tcg_init() have the wrong type.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20230717103544.637453-1-peter.maydell@linaro.org>
166 lines
6.5 KiB
C
166 lines
6.5 KiB
C
/*
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* QEMU monitor
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "monitor/monitor.h"
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#include "monitor/hmp-target.h"
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#include "monitor/hmp.h"
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void hmp_info_tlb(Monitor *mon, const QDict *qdict)
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{
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CPUArchState *env1 = mon_get_cpu_env(mon);
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if (!env1) {
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monitor_printf(mon, "No CPU available\n");
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return;
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}
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dump_mmu(env1);
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}
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#ifndef TARGET_SPARC64
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static target_long monitor_get_psr(Monitor *mon, const struct MonitorDef *md,
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int val)
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{
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CPUArchState *env = mon_get_cpu_env(mon);
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return cpu_get_psr(env);
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}
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#endif
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static target_long monitor_get_reg(Monitor *mon, const struct MonitorDef *md,
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int val)
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{
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CPUArchState *env = mon_get_cpu_env(mon);
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return env->regwptr[val];
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}
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const MonitorDef monitor_defs[] = {
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{ "g0", offsetof(CPUSPARCState, gregs[0]) },
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{ "g1", offsetof(CPUSPARCState, gregs[1]) },
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{ "g2", offsetof(CPUSPARCState, gregs[2]) },
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{ "g3", offsetof(CPUSPARCState, gregs[3]) },
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{ "g4", offsetof(CPUSPARCState, gregs[4]) },
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{ "g5", offsetof(CPUSPARCState, gregs[5]) },
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{ "g6", offsetof(CPUSPARCState, gregs[6]) },
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{ "g7", offsetof(CPUSPARCState, gregs[7]) },
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{ "o0", 0, monitor_get_reg },
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{ "o1", 1, monitor_get_reg },
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{ "o2", 2, monitor_get_reg },
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{ "o3", 3, monitor_get_reg },
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{ "o4", 4, monitor_get_reg },
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{ "o5", 5, monitor_get_reg },
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{ "o6", 6, monitor_get_reg },
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{ "o7", 7, monitor_get_reg },
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{ "l0", 8, monitor_get_reg },
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{ "l1", 9, monitor_get_reg },
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{ "l2", 10, monitor_get_reg },
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{ "l3", 11, monitor_get_reg },
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{ "l4", 12, monitor_get_reg },
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{ "l5", 13, monitor_get_reg },
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{ "l6", 14, monitor_get_reg },
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{ "l7", 15, monitor_get_reg },
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{ "i0", 16, monitor_get_reg },
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{ "i1", 17, monitor_get_reg },
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{ "i2", 18, monitor_get_reg },
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{ "i3", 19, monitor_get_reg },
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{ "i4", 20, monitor_get_reg },
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{ "i5", 21, monitor_get_reg },
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{ "i6", 22, monitor_get_reg },
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{ "i7", 23, monitor_get_reg },
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{ "pc", offsetof(CPUSPARCState, pc) },
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{ "npc", offsetof(CPUSPARCState, npc) },
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{ "y", offsetof(CPUSPARCState, y) },
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#ifndef TARGET_SPARC64
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{ "psr", 0, &monitor_get_psr, },
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{ "wim", offsetof(CPUSPARCState, wim) },
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#endif
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{ "tbr", offsetof(CPUSPARCState, tbr) },
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{ "fsr", offsetof(CPUSPARCState, fsr) },
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{ "f0", offsetof(CPUSPARCState, fpr[0].l.upper) },
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{ "f1", offsetof(CPUSPARCState, fpr[0].l.lower) },
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{ "f2", offsetof(CPUSPARCState, fpr[1].l.upper) },
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{ "f3", offsetof(CPUSPARCState, fpr[1].l.lower) },
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{ "f4", offsetof(CPUSPARCState, fpr[2].l.upper) },
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{ "f5", offsetof(CPUSPARCState, fpr[2].l.lower) },
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{ "f6", offsetof(CPUSPARCState, fpr[3].l.upper) },
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{ "f7", offsetof(CPUSPARCState, fpr[3].l.lower) },
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{ "f8", offsetof(CPUSPARCState, fpr[4].l.upper) },
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{ "f9", offsetof(CPUSPARCState, fpr[4].l.lower) },
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{ "f10", offsetof(CPUSPARCState, fpr[5].l.upper) },
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{ "f11", offsetof(CPUSPARCState, fpr[5].l.lower) },
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{ "f12", offsetof(CPUSPARCState, fpr[6].l.upper) },
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{ "f13", offsetof(CPUSPARCState, fpr[6].l.lower) },
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{ "f14", offsetof(CPUSPARCState, fpr[7].l.upper) },
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{ "f15", offsetof(CPUSPARCState, fpr[7].l.lower) },
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{ "f16", offsetof(CPUSPARCState, fpr[8].l.upper) },
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{ "f17", offsetof(CPUSPARCState, fpr[8].l.lower) },
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{ "f18", offsetof(CPUSPARCState, fpr[9].l.upper) },
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{ "f19", offsetof(CPUSPARCState, fpr[9].l.lower) },
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{ "f20", offsetof(CPUSPARCState, fpr[10].l.upper) },
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{ "f21", offsetof(CPUSPARCState, fpr[10].l.lower) },
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{ "f22", offsetof(CPUSPARCState, fpr[11].l.upper) },
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{ "f23", offsetof(CPUSPARCState, fpr[11].l.lower) },
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{ "f24", offsetof(CPUSPARCState, fpr[12].l.upper) },
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{ "f25", offsetof(CPUSPARCState, fpr[12].l.lower) },
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{ "f26", offsetof(CPUSPARCState, fpr[13].l.upper) },
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{ "f27", offsetof(CPUSPARCState, fpr[13].l.lower) },
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{ "f28", offsetof(CPUSPARCState, fpr[14].l.upper) },
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{ "f29", offsetof(CPUSPARCState, fpr[14].l.lower) },
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{ "f30", offsetof(CPUSPARCState, fpr[15].l.upper) },
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{ "f31", offsetof(CPUSPARCState, fpr[15].l.lower) },
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#ifdef TARGET_SPARC64
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{ "f32", offsetof(CPUSPARCState, fpr[16]) },
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{ "f34", offsetof(CPUSPARCState, fpr[17]) },
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{ "f36", offsetof(CPUSPARCState, fpr[18]) },
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{ "f38", offsetof(CPUSPARCState, fpr[19]) },
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{ "f40", offsetof(CPUSPARCState, fpr[20]) },
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{ "f42", offsetof(CPUSPARCState, fpr[21]) },
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{ "f44", offsetof(CPUSPARCState, fpr[22]) },
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{ "f46", offsetof(CPUSPARCState, fpr[23]) },
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{ "f48", offsetof(CPUSPARCState, fpr[24]) },
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{ "f50", offsetof(CPUSPARCState, fpr[25]) },
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{ "f52", offsetof(CPUSPARCState, fpr[26]) },
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{ "f54", offsetof(CPUSPARCState, fpr[27]) },
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{ "f56", offsetof(CPUSPARCState, fpr[28]) },
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{ "f58", offsetof(CPUSPARCState, fpr[29]) },
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{ "f60", offsetof(CPUSPARCState, fpr[30]) },
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{ "f62", offsetof(CPUSPARCState, fpr[31]) },
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{ "asi", offsetof(CPUSPARCState, asi) },
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{ "pstate", offsetof(CPUSPARCState, pstate) },
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{ "cansave", offsetof(CPUSPARCState, cansave) },
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{ "canrestore", offsetof(CPUSPARCState, canrestore) },
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{ "otherwin", offsetof(CPUSPARCState, otherwin) },
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{ "wstate", offsetof(CPUSPARCState, wstate) },
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{ "cleanwin", offsetof(CPUSPARCState, cleanwin) },
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{ "fprs", offsetof(CPUSPARCState, fprs), NULL, MD_I32 },
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#endif
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{ NULL },
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};
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const MonitorDef *target_monitor_defs(void)
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{
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return monitor_defs;
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}
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