444fa22549
Do a basic conversion of the acpi_cpu_hotplug spec document to rST. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20210727170414.3368-2-peter.maydell@linaro.org
236 lines
7.0 KiB
ReStructuredText
236 lines
7.0 KiB
ReStructuredText
QEMU<->ACPI BIOS CPU hotplug interface
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======================================
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QEMU supports CPU hotplug via ACPI. This document
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describes the interface between QEMU and the ACPI BIOS.
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ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
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and hot-remove events.
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Legacy ACPI CPU hotplug interface registers
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-------------------------------------------
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CPU present bitmap for:
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- ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
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- PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
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- One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
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- The first DWORD in bitmap is used in write mode to switch from legacy
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to modern CPU hotplug interface, write 0 into it to do switch.
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QEMU sets corresponding CPU bit on hot-add event and issues SCI
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with GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler
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to notify OS about CPU hot-add events. CPU hot-remove isn't supported.
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Modern ACPI CPU hotplug interface registers
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-------------------------------------------
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Register block base address:
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- ICH9-LPC IO port 0x0cd8
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- PIIX-PM IO port 0xaf00
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Register block size:
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- ACPI_CPU_HOTPLUG_REG_LEN = 12
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All accesses to registers described below, imply little-endian byte order.
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Reserved registers behavior:
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- write accesses are ignored
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- read accesses return all bits set to 0.
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The last stored value in 'CPU selector' must refer to a possible CPU, otherwise
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- reads from any register return 0
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- writes to any other register are ignored until valid value is stored into it
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On QEMU start, 'CPU selector' is initialized to a valid value, on reset it
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keeps the current value.
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Read access behavior
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^^^^^^^^^^^^^^^^^^^^
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offset [0x0-0x3]
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Command data 2: (DWORD access)
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If value last stored in 'Command field' is:
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0:
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reads as 0x0
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3:
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upper 32 bits of architecture specific CPU ID value
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other values:
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reserved
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offset [0x4]
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CPU device status fields: (1 byte access)
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bits:
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0:
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Device is enabled and may be used by guest
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1:
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Device insert event, used to distinguish device for which
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no device check event to OSPM was issued.
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It's valid only when bit 0 is set.
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2:
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Device remove event, used to distinguish device for which
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no device eject request to OSPM was issued. Firmware must
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ignore this bit.
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3:
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reserved and should be ignored by OSPM
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4:
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if set to 1, OSPM requests firmware to perform device eject.
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5-7:
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reserved and should be ignored by OSPM
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offset [0x5-0x7]
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reserved
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offset [0x8]
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Command data: (DWORD access)
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If value last stored in 'Command field' is one of:
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0:
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contains 'CPU selector' value of a CPU with pending event[s]
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3:
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lower 32 bits of architecture specific CPU ID value
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(in x86 case: APIC ID)
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otherwise:
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contains 0
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Write access behavior
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^^^^^^^^^^^^^^^^^^^^^
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offset [0x0-0x3]
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CPU selector: (DWORD access)
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Selects active CPU device. All following accesses to other
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registers will read/store data from/to selected CPU.
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Valid values: [0 .. max_cpus)
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offset [0x4]
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CPU device control fields: (1 byte access)
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bits:
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0:
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reserved, OSPM must clear it before writing to register.
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1:
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if set to 1 clears device insert event, set by OSPM
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after it has emitted device check event for the
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selected CPU device
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2:
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if set to 1 clears device remove event, set by OSPM
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after it has emitted device eject request for the
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selected CPU device.
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3:
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if set to 1 initiates device eject, set by OSPM when it
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triggers CPU device removal and calls _EJ0 method or by firmware
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when bit #4 is set. In case bit #4 were set, it's cleared as
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part of device eject.
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4:
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if set to 1, OSPM hands over device eject to firmware.
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Firmware shall issue device eject request as described above
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(bit #3) and OSPM should not touch device eject bit (#3) in case
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it's asked firmware to perform CPU device eject.
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5-7:
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reserved, OSPM must clear them before writing to register
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offset[0x5]
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Command field: (1 byte access)
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value:
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0:
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selects a CPU device with inserting/removing events and
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following reads from 'Command data' register return
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selected CPU ('CPU selector' value).
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If no CPU with events found, the current 'CPU selector' doesn't
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change and corresponding insert/remove event flags are not modified.
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1:
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following writes to 'Command data' register set OST event
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register in QEMU
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2:
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following writes to 'Command data' register set OST status
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register in QEMU
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3:
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following reads from 'Command data' and 'Command data 2' return
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architecture specific CPU ID value for currently selected CPU.
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other values:
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reserved
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offset [0x6-0x7]
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reserved
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offset [0x8]
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Command data: (DWORD access)
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If last stored 'Command field' value is:
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1:
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stores value into OST event register
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2:
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stores value into OST status register, triggers
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ACPI_DEVICE_OST QMP event from QEMU to external applications
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with current values of OST event and status registers.
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other values:
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reserved
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Typical usecases
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----------------
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(x86) Detecting and enabling modern CPU hotplug interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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QEMU starts with legacy CPU hotplug interface enabled. Detecting and
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switching to modern interface is based on the 2 legacy CPU hotplug features:
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#. Writes into CPU bitmap are ignored.
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#. CPU bitmap always has bit #0 set, corresponding to boot CPU.
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Use following steps to detect and enable modern CPU hotplug interface:
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#. Store 0x0 to the 'CPU selector' register, attempting to switch to modern mode
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#. Store 0x0 to the 'CPU selector' register, to ensure valid selector value
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#. Store 0x0 to the 'Command field' register
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#. Read the 'Command data 2' register.
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If read value is 0x0, the modern interface is enabled.
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Otherwise legacy or no CPU hotplug interface available
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Get a cpu with pending event
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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#. Store 0x0 to the 'CPU selector' register.
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#. Store 0x0 to the 'Command field' register.
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#. Read the 'CPU device status fields' register.
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#. If both bit #1 and bit #2 are clear in the value read, there is no CPU
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with a pending event and selected CPU remains unchanged.
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#. Otherwise, read the 'Command data' register. The value read is the
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selector of the CPU with the pending event (which is already selected).
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Enumerate CPUs present/non present CPUs
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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#. Set the present CPU count to 0.
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#. Set the iterator to 0.
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#. Store 0x0 to the 'CPU selector' register, to ensure that it's in
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a valid state and that access to other registers won't be ignored.
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#. Store 0x0 to the 'Command field' register to make 'Command data'
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register return 'CPU selector' value of selected CPU
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#. Read the 'CPU device status fields' register.
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#. If bit #0 is set, increment the present CPU count.
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#. Increment the iterator.
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#. Store the iterator to the 'CPU selector' register.
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#. Read the 'Command data' register.
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#. If the value read is not zero, goto 05.
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#. Otherwise store 0x0 to the 'CPU selector' register, to put it
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into a valid state and exit.
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The iterator at this point equals "max_cpus".
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