83c9f9d39f
This struct has been unused since
Commit f932093ae165 ("hw/arm/bcm2836: Split out common part of BCM283X
classes")
Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
246 lines
8.2 KiB
C
246 lines
8.2 KiB
C
/*
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* Raspberry Pi emulation (c) 2012 Gregory Estrade
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* Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
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*
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* Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/arm/bcm2836.h"
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#include "hw/arm/raspi_platform.h"
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#include "hw/sysbus.h"
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#include "target/arm/cpu-qom.h"
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#include "target/arm/gtimer.h"
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static Property bcm2836_enabled_cores_property =
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DEFINE_PROP_UINT32("enabled-cpus", BCM283XBaseState, enabled_cpus, 0);
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static void bcm283x_base_init(Object *obj)
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{
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BCM283XBaseState *s = BCM283X_BASE(obj);
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BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(obj);
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int n;
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for (n = 0; n < bc->core_count; n++) {
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object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
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bc->cpu_type);
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}
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if (bc->core_count > 1) {
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qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
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qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
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}
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if (bc->ctrl_base) {
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object_initialize_child(obj, "control", &s->control,
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TYPE_BCM2836_CONTROL);
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}
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}
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static void bcm283x_init(Object *obj)
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{
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BCM283XState *s = BCM283X(obj);
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object_initialize_child(obj, "peripherals", &s->peripherals,
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TYPE_BCM2835_PERIPHERALS);
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object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals),
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"board-rev");
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object_property_add_alias(obj, "command-line", OBJECT(&s->peripherals),
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"command-line");
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object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals),
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"vcram-size");
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object_property_add_alias(obj, "vcram-base", OBJECT(&s->peripherals),
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"vcram-base");
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}
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bool bcm283x_common_realize(DeviceState *dev, BCMSocPeripheralBaseState *ps,
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Error **errp)
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{
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BCM283XBaseState *s = BCM283X_BASE(dev);
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BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(dev);
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Object *obj;
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/* common peripherals from bcm2835 */
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obj = object_property_get_link(OBJECT(dev), "ram", &error_abort);
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object_property_add_const_link(OBJECT(ps), "ram", obj);
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if (!sysbus_realize(SYS_BUS_DEVICE(ps), errp)) {
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return false;
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}
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object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(ps), "sd-bus");
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sysbus_mmio_map_overlap(SYS_BUS_DEVICE(ps), 0, bc->peri_base, 1);
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return true;
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}
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static void bcm2835_realize(DeviceState *dev, Error **errp)
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{
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BCM283XState *s = BCM283X(dev);
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BCM283XBaseState *s_base = BCM283X_BASE(dev);
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BCMSocPeripheralBaseState *ps_base
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= BCM_SOC_PERIPHERALS_BASE(&s->peripherals);
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if (!bcm283x_common_realize(dev, ps_base, errp)) {
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return;
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}
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if (!qdev_realize(DEVICE(&s_base->cpu[0].core), NULL, errp)) {
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return;
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}
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/* Connect irq/fiq outputs from the interrupt controller. */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
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qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
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qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_FIQ));
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}
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static void bcm2836_realize(DeviceState *dev, Error **errp)
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{
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int n;
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BCM283XState *s = BCM283X(dev);
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BCM283XBaseState *s_base = BCM283X_BASE(dev);
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BCM283XBaseClass *bc = BCM283X_BASE_GET_CLASS(dev);
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BCMSocPeripheralBaseState *ps_base
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= BCM_SOC_PERIPHERALS_BASE(&s->peripherals);
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if (!bcm283x_common_realize(dev, ps_base, errp)) {
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return;
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}
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/* bcm2836 interrupt controller (and mailboxes, etc.) */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s_base->control), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s_base->control), 0, bc->ctrl_base);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
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qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-irq", 0));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
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qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-fiq", 0));
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for (n = 0; n < BCM283X_NCPUS; n++) {
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object_property_set_int(OBJECT(&s_base->cpu[n].core), "mp-affinity",
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(bc->clusterid << 8) | n, &error_abort);
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/* set periphbase/CBAR value for CPU-local registers */
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object_property_set_int(OBJECT(&s_base->cpu[n].core), "reset-cbar",
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bc->peri_base, &error_abort);
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/* start powered off if not enabled */
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object_property_set_bool(OBJECT(&s_base->cpu[n].core),
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"start-powered-off",
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n >= s_base->enabled_cpus, &error_abort);
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if (!qdev_realize(DEVICE(&s_base->cpu[n].core), NULL, errp)) {
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return;
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}
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/* Connect irq/fiq outputs from the interrupt controller. */
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qdev_connect_gpio_out_named(DEVICE(&s_base->control), "irq", n,
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qdev_get_gpio_in(DEVICE(&s_base->cpu[n].core), ARM_CPU_IRQ));
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qdev_connect_gpio_out_named(DEVICE(&s_base->control), "fiq", n,
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qdev_get_gpio_in(DEVICE(&s_base->cpu[n].core), ARM_CPU_FIQ));
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/* Connect timers from the CPU to the interrupt controller */
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qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_PHYS,
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qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntpnsirq", n));
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qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_VIRT,
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qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntvirq", n));
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qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_HYP,
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qdev_get_gpio_in_named(DEVICE(&s_base->control), "cnthpirq", n));
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qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_SEC,
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qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntpsirq", n));
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}
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}
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static void bcm283x_base_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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/* Reason: Must be wired up in code (see raspi_init() function) */
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dc->user_creatable = false;
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}
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static void bcm2835_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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BCM283XBaseClass *bc = BCM283X_BASE_CLASS(oc);
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bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
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bc->core_count = 1;
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bc->peri_base = 0x20000000;
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dc->realize = bcm2835_realize;
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};
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static void bcm2836_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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BCM283XBaseClass *bc = BCM283X_BASE_CLASS(oc);
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bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
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bc->core_count = BCM283X_NCPUS;
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bc->peri_base = 0x3f000000;
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bc->ctrl_base = 0x40000000;
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bc->clusterid = 0xf;
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dc->realize = bcm2836_realize;
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};
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#ifdef TARGET_AARCH64
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static void bcm2837_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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BCM283XBaseClass *bc = BCM283X_BASE_CLASS(oc);
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bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
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bc->core_count = BCM283X_NCPUS;
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bc->peri_base = 0x3f000000;
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bc->ctrl_base = 0x40000000;
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bc->clusterid = 0x0;
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dc->realize = bcm2836_realize;
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};
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#endif
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static const TypeInfo bcm283x_types[] = {
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{
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.name = TYPE_BCM2835,
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.parent = TYPE_BCM283X,
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.class_init = bcm2835_class_init,
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}, {
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.name = TYPE_BCM2836,
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.parent = TYPE_BCM283X,
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.class_init = bcm2836_class_init,
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#ifdef TARGET_AARCH64
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}, {
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.name = TYPE_BCM2837,
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.parent = TYPE_BCM283X,
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.class_init = bcm2837_class_init,
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#endif
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}, {
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.name = TYPE_BCM283X,
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.parent = TYPE_BCM283X_BASE,
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.instance_size = sizeof(BCM283XState),
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.instance_init = bcm283x_init,
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.abstract = true,
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}, {
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.name = TYPE_BCM283X_BASE,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(BCM283XBaseState),
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.instance_init = bcm283x_base_init,
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.class_size = sizeof(BCM283XBaseClass),
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.class_init = bcm283x_base_class_init,
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.abstract = true,
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}
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};
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DEFINE_TYPES(bcm283x_types)
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