d4f7804bac
Add an additional test to further exercise the IOMMU where we attempt to initialize the command, fault and page-request queues. These steps are taken from chapter 6.2 of the RISC-V IOMMU spec, "Guidelines for initialization". It emulates what we expect from the software/OS when initializing the IOMMU. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241016204038.649340-12-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
102 lines
3.4 KiB
C
102 lines
3.4 KiB
C
/*
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* libqos driver riscv-iommu-pci framework
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*
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* Copyright (c) 2024 Ventana Micro Systems Inc.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at your
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* option) any later version. See the COPYING file in the top-level directory.
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*
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*/
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#ifndef TESTS_LIBQOS_RISCV_IOMMU_H
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#define TESTS_LIBQOS_RISCV_IOMMU_H
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#include "qgraph.h"
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#include "pci.h"
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#include "qemu/bitops.h"
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#ifndef GENMASK_ULL
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#define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l))
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#endif
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/*
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* RISC-V IOMMU uses PCI_VENDOR_ID_REDHAT 0x1b36 and
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* PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014.
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*/
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#define RISCV_IOMMU_PCI_VENDOR_ID 0x1b36
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#define RISCV_IOMMU_PCI_DEVICE_ID 0x0014
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#define RISCV_IOMMU_PCI_DEVICE_CLASS 0x0806
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/* Common field positions */
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#define RISCV_IOMMU_QUEUE_ENABLE BIT(0)
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#define RISCV_IOMMU_QUEUE_INTR_ENABLE BIT(1)
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#define RISCV_IOMMU_QUEUE_MEM_FAULT BIT(8)
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#define RISCV_IOMMU_QUEUE_ACTIVE BIT(16)
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#define RISCV_IOMMU_QUEUE_BUSY BIT(17)
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#define RISCV_IOMMU_REG_CAP 0x0000
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#define RISCV_IOMMU_CAP_VERSION GENMASK_ULL(7, 0)
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#define RISCV_IOMMU_REG_DDTP 0x0010
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#define RISCV_IOMMU_DDTP_BUSY BIT_ULL(4)
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#define RISCV_IOMMU_DDTP_MODE GENMASK_ULL(3, 0)
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#define RISCV_IOMMU_DDTP_MODE_OFF 0
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#define RISCV_IOMMU_REG_CQCSR 0x0048
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#define RISCV_IOMMU_CQCSR_CQEN RISCV_IOMMU_QUEUE_ENABLE
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#define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE
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#define RISCV_IOMMU_CQCSR_CQON RISCV_IOMMU_QUEUE_ACTIVE
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#define RISCV_IOMMU_CQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY
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#define RISCV_IOMMU_REG_FQCSR 0x004C
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#define RISCV_IOMMU_FQCSR_FQEN RISCV_IOMMU_QUEUE_ENABLE
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#define RISCV_IOMMU_FQCSR_FIE RISCV_IOMMU_QUEUE_INTR_ENABLE
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#define RISCV_IOMMU_FQCSR_FQON RISCV_IOMMU_QUEUE_ACTIVE
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#define RISCV_IOMMU_FQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY
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#define RISCV_IOMMU_REG_PQCSR 0x0050
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#define RISCV_IOMMU_PQCSR_PQEN RISCV_IOMMU_QUEUE_ENABLE
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#define RISCV_IOMMU_PQCSR_PIE RISCV_IOMMU_QUEUE_INTR_ENABLE
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#define RISCV_IOMMU_PQCSR_PQON RISCV_IOMMU_QUEUE_ACTIVE
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#define RISCV_IOMMU_PQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY
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#define RISCV_IOMMU_REG_IPSR 0x0054
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#define RISCV_IOMMU_REG_IVEC 0x02F8
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#define RISCV_IOMMU_REG_IVEC_CIV GENMASK_ULL(3, 0)
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#define RISCV_IOMMU_REG_IVEC_FIV GENMASK_ULL(7, 4)
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#define RISCV_IOMMU_REG_IVEC_PMIV GENMASK_ULL(11, 8)
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#define RISCV_IOMMU_REG_IVEC_PIV GENMASK_ULL(15, 12)
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#define RISCV_IOMMU_REG_CQB 0x0018
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#define RISCV_IOMMU_CQB_PPN_START 10
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#define RISCV_IOMMU_CQB_PPN_LEN 44
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#define RISCV_IOMMU_CQB_LOG2SZ_START 0
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#define RISCV_IOMMU_CQB_LOG2SZ_LEN 5
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#define RISCV_IOMMU_REG_CQT 0x0024
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#define RISCV_IOMMU_REG_FQB 0x0028
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#define RISCV_IOMMU_FQB_PPN_START 10
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#define RISCV_IOMMU_FQB_PPN_LEN 44
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#define RISCV_IOMMU_FQB_LOG2SZ_START 0
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#define RISCV_IOMMU_FQB_LOG2SZ_LEN 5
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#define RISCV_IOMMU_REG_FQT 0x0034
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#define RISCV_IOMMU_REG_PQB 0x0038
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#define RISCV_IOMMU_PQB_PPN_START 10
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#define RISCV_IOMMU_PQB_PPN_LEN 44
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#define RISCV_IOMMU_PQB_LOG2SZ_START 0
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#define RISCV_IOMMU_PQB_LOG2SZ_LEN 5
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#define RISCV_IOMMU_REG_PQT 0x0044
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typedef struct QRISCVIOMMU {
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QOSGraphObject obj;
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QPCIDevice dev;
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QPCIBar reg_bar;
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} QRISCVIOMMU;
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#endif
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