0c40daf038
"kvm_arm.h" contains external and internal prototype declarations. Files under the hw/ directory should only access the KVM external API. In order to avoid machine / device models to include "kvm_arm.h" simply to get the QOM GIC/ITS class name, un-inline each class name getter to the proper device model file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230405160454.97436-4-philmd@linaro.org>
92 lines
3.2 KiB
C
92 lines
3.2 KiB
C
/*
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* ARM GIC support
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*
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* Copyright (c) 2012 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* QEMU interface:
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* + QOM property "num-cpu": number of CPUs to support
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* + QOM property "num-irq": number of IRQs (including both SPIs and PPIs)
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* + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore GIC
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* + QOM property "has-security-extensions": set true if the GIC should
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* implement the security extensions
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* + QOM property "has-virtualization-extensions": set true if the GIC should
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* implement the virtualization extensions
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* + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32)
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* [0..P-1] SPIs
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* [P..P+31] PPIs for CPU 0
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* [P+32..P+63] PPIs for CPU 1
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* ...
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* + sysbus IRQs: (in order; number will vary depending on number of cores)
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* - IRQ for CPU 0
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* - IRQ for CPU 1
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* ...
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* - FIQ for CPU 0
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* - FIQ for CPU 1
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* ...
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* - VIRQ for CPU 0 (exists even if virt extensions not present)
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* - VIRQ for CPU 1 (exists even if virt extensions not present)
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* ...
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* - VFIQ for CPU 0 (exists even if virt extensions not present)
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* - VFIQ for CPU 1 (exists even if virt extensions not present)
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* ...
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* - maintenance IRQ for CPU i/f 0 (only if virt extensions present)
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* - maintenance IRQ for CPU i/f 1 (only if virt extensions present)
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* + sysbus MMIO regions: (in order; numbers will vary depending on
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* whether virtualization extensions are present and on number of cores)
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* - distributor registers (GICD*)
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* - CPU interface for the accessing core (GICC*)
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* - virtual interface control registers (GICH*) (only if virt extns present)
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* - virtual CPU interface for the accessing core (GICV*) (only if virt)
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* - CPU 0 CPU interface registers
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* - CPU 1 CPU interface registers
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* ...
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* - CPU 0 virtual interface control registers (only if virt extns present)
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* - CPU 1 virtual interface control registers (only if virt extns present)
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* ...
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*/
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#ifndef HW_ARM_GIC_H
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#define HW_ARM_GIC_H
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#include "arm_gic_common.h"
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#include "qom/object.h"
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/* Number of SGI target-list bits */
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#define GIC_TARGETLIST_BITS 8
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#define GIC_MAX_PRIORITY_BITS 8
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#define GIC_MIN_PRIORITY_BITS 4
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#define TYPE_ARM_GIC "arm_gic"
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typedef struct ARMGICClass ARMGICClass;
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/* This is reusing the GICState typedef from TYPE_ARM_GIC_COMMON */
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DECLARE_OBJ_CHECKERS(GICState, ARMGICClass,
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ARM_GIC, TYPE_ARM_GIC)
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struct ARMGICClass {
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/*< private >*/
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ARMGICCommonClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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};
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const char *gic_class_name(void);
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#endif
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