9951133e46
Changes in commit 533eb415df2e ("arm/aspeed: actually check RAM size")
introduced a 'valid_ram_sizes' array which can be used to compute the
associated bit field value encoding the RAM size. The field is simply
the index of the array.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-19-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
523 lines
15 KiB
C
523 lines
15 KiB
C
/*
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* ASPEED SDRAM Memory Controller
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/error-report.h"
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#include "hw/misc/aspeed_sdmc.h"
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#include "hw/misc/aspeed_scu.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "qemu/units.h"
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#include "qemu/cutils.h"
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#include "qapi/visitor.h"
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/* Protection Key Register */
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#define R_PROT (0x00 / 4)
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#define PROT_UNLOCKED 0x01
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#define PROT_HARDLOCKED 0x10 /* AST2600 */
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#define PROT_SOFTLOCKED 0x00
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#define PROT_KEY_UNLOCK 0xFC600309
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#define PROT_KEY_HARDLOCK 0xDEADDEAD /* AST2600 */
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/* Configuration Register */
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#define R_CONF (0x04 / 4)
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/* Interrupt control/status */
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#define R_ISR (0x50 / 4)
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/* Control/Status Register #1 (ast2500) */
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#define R_STATUS1 (0x60 / 4)
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#define PHY_BUSY_STATE BIT(0)
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#define PHY_PLL_LOCK_STATUS BIT(4)
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/* Reserved */
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#define R_MCR6C (0x6c / 4)
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#define R_ECC_TEST_CTRL (0x70 / 4)
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#define ECC_TEST_FINISHED BIT(12)
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#define ECC_TEST_FAIL BIT(13)
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#define R_TEST_START_LEN (0x74 / 4)
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#define R_TEST_FAIL_DQ (0x78 / 4)
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#define R_TEST_INIT_VAL (0x7c / 4)
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#define R_DRAM_SW (0x88 / 4)
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#define R_DRAM_TIME (0x8c / 4)
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#define R_ECC_ERR_INJECT (0xb4 / 4)
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/*
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* Configuration register Ox4 (for Aspeed AST2400 SOC)
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*
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* These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
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* what we care about right now as it is checked by U-Boot to
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* determine the RAM size.
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*/
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#define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */
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#define ASPEED_SDMC_AST2300_COMPAT (1 << 10)
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#define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9)
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#define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8)
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#define ASPEED_SDMC_ECC_ENABLE (1 << 7)
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#define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */
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#define ASPEED_SDMC_DRAM_BANK (1 << 5)
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#define ASPEED_SDMC_DRAM_BURST (1 << 4)
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#define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */
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#define ASPEED_SDMC_VGA_8MB 0x0
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#define ASPEED_SDMC_VGA_16MB 0x1
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#define ASPEED_SDMC_VGA_32MB 0x2
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#define ASPEED_SDMC_VGA_64MB 0x3
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#define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3)
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#define ASPEED_SDMC_DRAM_64MB 0x0
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#define ASPEED_SDMC_DRAM_128MB 0x1
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#define ASPEED_SDMC_DRAM_256MB 0x2
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#define ASPEED_SDMC_DRAM_512MB 0x3
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#define ASPEED_SDMC_READONLY_MASK \
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(ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
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ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
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/*
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* Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
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*
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* Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
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* should be set to 1 for the AST2500 SOC.
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*/
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#define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */
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#define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20)
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#define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */
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#define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */
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#define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13)
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#define ASPEED_SDMC_CACHE_INITIAL (1 << 12)
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#define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11)
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#define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */
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#define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */
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/* DRAM size definitions differs */
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#define ASPEED_SDMC_AST2500_128MB 0x0
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#define ASPEED_SDMC_AST2500_256MB 0x1
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#define ASPEED_SDMC_AST2500_512MB 0x2
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#define ASPEED_SDMC_AST2500_1024MB 0x3
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#define ASPEED_SDMC_AST2600_256MB 0x0
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#define ASPEED_SDMC_AST2600_512MB 0x1
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#define ASPEED_SDMC_AST2600_1024MB 0x2
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#define ASPEED_SDMC_AST2600_2048MB 0x3
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#define ASPEED_SDMC_AST2500_READONLY_MASK \
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(ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \
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ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
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ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
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static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
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{
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AspeedSDMCState *s = ASPEED_SDMC(opaque);
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addr >>= 2;
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if (addr >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
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__func__, addr * 4);
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return 0;
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}
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return s->regs[addr];
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}
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static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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AspeedSDMCState *s = ASPEED_SDMC(opaque);
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AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
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addr >>= 2;
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if (addr >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return;
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}
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asc->write(s, addr, data);
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}
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static const MemoryRegionOps aspeed_sdmc_ops = {
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.read = aspeed_sdmc_read,
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.write = aspeed_sdmc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void aspeed_sdmc_reset(DeviceState *dev)
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{
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AspeedSDMCState *s = ASPEED_SDMC(dev);
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AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
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memset(s->regs, 0, sizeof(s->regs));
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/* Set ram size bit and defaults values */
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s->regs[R_CONF] = asc->compute_conf(s, 0);
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/*
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* PHY status:
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* - set phy status ok (set bit 1)
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* - initial PVT calibration ok (clear bit 3)
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* - runtime calibration ok (clear bit 5)
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*/
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s->regs[0x100] = BIT(1);
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/* PHY eye window: set all as passing */
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s->regs[0x100 | (0x68 / 4)] = 0xff;
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s->regs[0x100 | (0x7c / 4)] = 0xff;
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s->regs[0x100 | (0x50 / 4)] = 0xfffffff;
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}
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static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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AspeedSDMCState *s = ASPEED_SDMC(obj);
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int64_t value = s->ram_size;
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visit_type_int(v, name, &value, errp);
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}
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static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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int i;
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char *sz;
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int64_t value;
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AspeedSDMCState *s = ASPEED_SDMC(obj);
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AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
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if (!visit_type_int(v, name, &value, errp)) {
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return;
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}
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for (i = 0; asc->valid_ram_sizes[i]; i++) {
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if (value == asc->valid_ram_sizes[i]) {
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s->ram_size = value;
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return;
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}
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}
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sz = size_to_str(value);
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error_setg(errp, "Invalid RAM size %s", sz);
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g_free(sz);
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}
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static void aspeed_sdmc_initfn(Object *obj)
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{
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object_property_add(obj, "ram-size", "int",
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aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size,
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NULL, NULL);
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}
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static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedSDMCState *s = ASPEED_SDMC(dev);
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AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
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assert(asc->max_ram_size < 4 * GiB); /* 32-bit address bus */
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s->max_ram_size = asc->max_ram_size;
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
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TYPE_ASPEED_SDMC, 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription vmstate_aspeed_sdmc = {
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.name = "aspeed.sdmc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property aspeed_sdmc_properties[] = {
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DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = aspeed_sdmc_realize;
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dc->reset = aspeed_sdmc_reset;
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dc->desc = "ASPEED SDRAM Memory Controller";
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dc->vmsd = &vmstate_aspeed_sdmc;
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device_class_set_props(dc, aspeed_sdmc_properties);
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}
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static const TypeInfo aspeed_sdmc_info = {
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.name = TYPE_ASPEED_SDMC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedSDMCState),
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.instance_init = aspeed_sdmc_initfn,
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.class_init = aspeed_sdmc_class_init,
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.class_size = sizeof(AspeedSDMCClass),
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.abstract = true,
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};
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static int aspeed_sdmc_get_ram_bits(AspeedSDMCState *s)
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{
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AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
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int i;
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/*
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* The bitfield value encoding the RAM size is the index of the
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* possible RAM size array
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*/
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for (i = 0; asc->valid_ram_sizes[i]; i++) {
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if (s->ram_size == asc->valid_ram_sizes[i]) {
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return i;
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}
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}
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/*
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* Invalid RAM sizes should have been excluded when setting the
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* SoC RAM size.
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*/
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g_assert_not_reached();
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}
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static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
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{
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uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT |
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ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s));
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/* Make sure readonly bits are kept */
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data &= ~ASPEED_SDMC_READONLY_MASK;
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return data | fixed_conf;
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}
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static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
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uint32_t data)
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{
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if (reg == R_PROT) {
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s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
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return;
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}
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if (!s->regs[R_PROT]) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
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return;
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}
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switch (reg) {
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case R_CONF:
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data = aspeed_2400_sdmc_compute_conf(s, data);
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break;
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default:
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break;
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}
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s->regs[reg] = data;
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}
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static const uint64_t
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aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0};
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static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
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dc->desc = "ASPEED 2400 SDRAM Memory Controller";
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asc->max_ram_size = 512 * MiB;
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asc->compute_conf = aspeed_2400_sdmc_compute_conf;
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asc->write = aspeed_2400_sdmc_write;
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asc->valid_ram_sizes = aspeed_2400_ram_sizes;
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}
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static const TypeInfo aspeed_2400_sdmc_info = {
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.name = TYPE_ASPEED_2400_SDMC,
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.parent = TYPE_ASPEED_SDMC,
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.class_init = aspeed_2400_sdmc_class_init,
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};
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static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
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{
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uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
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ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
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ASPEED_SDMC_CACHE_INITIAL_DONE |
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ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s));
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/* Make sure readonly bits are kept */
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data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
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return data | fixed_conf;
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}
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static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
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uint32_t data)
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{
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if (reg == R_PROT) {
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s->regs[reg] = (data == PROT_KEY_UNLOCK) ? PROT_UNLOCKED : PROT_SOFTLOCKED;
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return;
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}
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if (!s->regs[R_PROT]) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
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return;
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}
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switch (reg) {
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case R_CONF:
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data = aspeed_2500_sdmc_compute_conf(s, data);
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break;
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case R_STATUS1:
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/* Will never return 'busy' */
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data &= ~PHY_BUSY_STATE;
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break;
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case R_ECC_TEST_CTRL:
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/* Always done, always happy */
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data |= ECC_TEST_FINISHED;
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data &= ~ECC_TEST_FAIL;
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break;
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default:
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break;
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}
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s->regs[reg] = data;
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}
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static const uint64_t
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aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0};
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static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
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dc->desc = "ASPEED 2500 SDRAM Memory Controller";
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asc->max_ram_size = 1 * GiB;
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asc->compute_conf = aspeed_2500_sdmc_compute_conf;
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asc->write = aspeed_2500_sdmc_write;
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asc->valid_ram_sizes = aspeed_2500_ram_sizes;
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}
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static const TypeInfo aspeed_2500_sdmc_info = {
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.name = TYPE_ASPEED_2500_SDMC,
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.parent = TYPE_ASPEED_SDMC,
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.class_init = aspeed_2500_sdmc_class_init,
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};
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static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
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{
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uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) |
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ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
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ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s));
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/* Make sure readonly bits are kept (use ast2500 mask) */
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data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
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return data | fixed_conf;
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}
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static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
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uint32_t data)
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{
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/* Unprotected registers */
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switch (reg) {
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case R_ISR:
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case R_MCR6C:
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case R_TEST_START_LEN:
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case R_TEST_FAIL_DQ:
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case R_TEST_INIT_VAL:
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case R_DRAM_SW:
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case R_DRAM_TIME:
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case R_ECC_ERR_INJECT:
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s->regs[reg] = data;
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return;
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}
|
|
|
|
if (s->regs[R_PROT] == PROT_HARDLOCKED) {
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
|
|
__func__);
|
|
return;
|
|
}
|
|
|
|
if (reg != R_PROT && s->regs[R_PROT] == PROT_SOFTLOCKED) {
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"%s: SDMC is locked! (write to MCR%02x blocked)\n",
|
|
__func__, reg * 4);
|
|
return;
|
|
}
|
|
|
|
switch (reg) {
|
|
case R_PROT:
|
|
if (data == PROT_KEY_UNLOCK) {
|
|
data = PROT_UNLOCKED;
|
|
} else if (data == PROT_KEY_HARDLOCK) {
|
|
data = PROT_HARDLOCKED;
|
|
} else {
|
|
data = PROT_SOFTLOCKED;
|
|
}
|
|
break;
|
|
case R_CONF:
|
|
data = aspeed_2600_sdmc_compute_conf(s, data);
|
|
break;
|
|
case R_STATUS1:
|
|
/* Will never return 'busy'. 'lock status' is always set */
|
|
data &= ~PHY_BUSY_STATE;
|
|
data |= PHY_PLL_LOCK_STATUS;
|
|
break;
|
|
case R_ECC_TEST_CTRL:
|
|
/* Always done, always happy */
|
|
data |= ECC_TEST_FINISHED;
|
|
data &= ~ECC_TEST_FAIL;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
s->regs[reg] = data;
|
|
}
|
|
|
|
static const uint64_t
|
|
aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0};
|
|
|
|
static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
|
|
|
|
dc->desc = "ASPEED 2600 SDRAM Memory Controller";
|
|
asc->max_ram_size = 2 * GiB;
|
|
asc->compute_conf = aspeed_2600_sdmc_compute_conf;
|
|
asc->write = aspeed_2600_sdmc_write;
|
|
asc->valid_ram_sizes = aspeed_2600_ram_sizes;
|
|
}
|
|
|
|
static const TypeInfo aspeed_2600_sdmc_info = {
|
|
.name = TYPE_ASPEED_2600_SDMC,
|
|
.parent = TYPE_ASPEED_SDMC,
|
|
.class_init = aspeed_2600_sdmc_class_init,
|
|
};
|
|
|
|
static void aspeed_sdmc_register_types(void)
|
|
{
|
|
type_register_static(&aspeed_sdmc_info);
|
|
type_register_static(&aspeed_2400_sdmc_info);
|
|
type_register_static(&aspeed_2500_sdmc_info);
|
|
type_register_static(&aspeed_2600_sdmc_info);
|
|
}
|
|
|
|
type_init(aspeed_sdmc_register_types);
|