00f82b8a31
Anthony Liguori. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4265 c046a42c-6fe2-441c-8c8c-71466251a162
605 lines
18 KiB
C
605 lines
18 KiB
C
/*
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* internal execution defines for qemu
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* allow to see translation results - the slowdown should be negligible, so we leave it */
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#define DEBUG_DISAS
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/* is_jmp field values */
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#define DISAS_NEXT 0 /* next instruction can be analyzed */
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#define DISAS_JUMP 1 /* only pc was modified dynamically */
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#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
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#define DISAS_TB_JUMP 3 /* only pc was modified statically */
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struct TranslationBlock;
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/* XXX: make safe guess about sizes */
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#define MAX_OP_PER_INSTR 32
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/* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
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#define MAX_OPC_PARAM 10
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#define OPC_BUF_SIZE 512
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#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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/* Maximum size a TCG op can expand to. This is complicated because a
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single op may require several host instructions and regirster reloads.
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For now take a wild guess at 128 bytes, which should allow at least
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a couple of fixup instructions per argument. */
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#define TCG_MAX_OP_SIZE 128
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#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
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extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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extern target_ulong gen_opc_jump_pc[2];
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extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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typedef void (GenOpFunc)(void);
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typedef void (GenOpFunc1)(long);
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typedef void (GenOpFunc2)(long, long);
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typedef void (GenOpFunc3)(long, long, long);
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#if defined(TARGET_I386)
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void optimize_flags_init(void);
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#endif
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extern FILE *logfile;
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extern int loglevel;
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int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
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int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
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unsigned long code_gen_max_block_size(void);
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void cpu_gen_init(void);
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int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
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int *gen_code_size_ptr);
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int cpu_restore_state(struct TranslationBlock *tb,
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CPUState *env, unsigned long searched_pc,
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void *puc);
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int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
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int max_code_size, int *gen_code_size_ptr);
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int cpu_restore_state_copy(struct TranslationBlock *tb,
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CPUState *env, unsigned long searched_pc,
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void *puc);
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void cpu_resume_from_signal(CPUState *env1, void *puc);
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void cpu_exec_init(CPUState *env);
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int page_unprotect(target_ulong address, unsigned long pc, void *puc);
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void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
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int is_cpu_write_access);
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void tb_invalidate_page_range(target_ulong start, target_ulong end);
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void tlb_flush_page(CPUState *env, target_ulong addr);
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void tlb_flush(CPUState *env, int flush_global);
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int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
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target_phys_addr_t paddr, int prot,
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int mmu_idx, int is_softmmu);
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static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
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target_phys_addr_t paddr, int prot,
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int mmu_idx, int is_softmmu)
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{
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if (prot & PAGE_READ)
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prot |= PAGE_EXEC;
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return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
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}
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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#define CODE_GEN_PHYS_HASH_BITS 15
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#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
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/* maximum total translate dcode allocated */
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/* NOTE: the translated code area cannot be too big because on some
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archs the range of "fast" function calls is limited. Here is a
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summary of the ranges:
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i386 : signed 32 bits
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arm : signed 26 bits
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ppc : signed 24 bits
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sparc : signed 32 bits
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alpha : signed 23 bits
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*/
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#if defined(__alpha__)
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#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
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#elif defined(__ia64)
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#define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */
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#elif defined(__powerpc__)
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#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
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#else
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/* XXX: make it dynamic on x86 */
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#define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024)
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#endif
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//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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/* estimated block size for TB allocation */
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/* XXX: use a per code average code fragment size and modulate it
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according to the host CPU */
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#if defined(CONFIG_SOFTMMU)
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#define CODE_GEN_AVG_BLOCK_SIZE 128
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#else
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#define CODE_GEN_AVG_BLOCK_SIZE 64
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#endif
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#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
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#if defined(__powerpc__) || defined(__x86_64__)
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#define USE_DIRECT_JUMP
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#endif
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#if defined(__i386__) && !defined(_WIN32)
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#define USE_DIRECT_JUMP
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#endif
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typedef struct TranslationBlock {
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target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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target_ulong cs_base; /* CS base for this block */
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uint64_t flags; /* flags defining in which context the code was generated */
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uint16_t size; /* size of target code for this block (1 <=
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size <= TARGET_PAGE_SIZE) */
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uint16_t cflags; /* compile flags */
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#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
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#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
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#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
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#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
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uint8_t *tc_ptr; /* pointer to the translated code */
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/* next matching tb for physical address. */
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struct TranslationBlock *phys_hash_next;
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/* first and second physical page containing code. The lower bit
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of the pointer tells the index in page_next[] */
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struct TranslationBlock *page_next[2];
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target_ulong page_addr[2];
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/* the following data are used to directly call another TB from
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the code of this one. */
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uint16_t tb_next_offset[2]; /* offset of original jump target */
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#ifdef USE_DIRECT_JUMP
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uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
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#else
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unsigned long tb_next[2]; /* address of jump generated code */
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#endif
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/* list of TBs jumping to this one. This is a circular list using
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the two least significant bits of the pointers to tell what is
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the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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jmp_first */
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struct TranslationBlock *jmp_next[2];
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struct TranslationBlock *jmp_first;
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} TranslationBlock;
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static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
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{
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target_ulong tmp;
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tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
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}
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static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
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{
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target_ulong tmp;
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tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
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(tmp & TB_JMP_ADDR_MASK));
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}
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static inline unsigned int tb_phys_hash_func(unsigned long pc)
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{
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return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
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}
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TranslationBlock *tb_alloc(target_ulong pc);
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void tb_flush(CPUState *env);
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void tb_link_phys(TranslationBlock *tb,
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target_ulong phys_pc, target_ulong phys_page2);
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extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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extern uint8_t *code_gen_ptr;
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#if defined(USE_DIRECT_JUMP)
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#if defined(__powerpc__)
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static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
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{
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uint32_t val, *ptr;
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/* patch the branch destination */
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ptr = (uint32_t *)jmp_addr;
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val = *ptr;
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val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
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*ptr = val;
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/* flush icache */
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asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
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asm volatile ("sync" : : : "memory");
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asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
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asm volatile ("sync" : : : "memory");
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asm volatile ("isync" : : : "memory");
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}
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#elif defined(__i386__) || defined(__x86_64__)
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static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
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{
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/* patch the branch destination */
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*(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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/* no need to flush icache explicitely */
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}
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#endif
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static inline void tb_set_jmp_target(TranslationBlock *tb,
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int n, unsigned long addr)
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{
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unsigned long offset;
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offset = tb->tb_jmp_offset[n];
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tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
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offset = tb->tb_jmp_offset[n + 2];
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if (offset != 0xffff)
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tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
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}
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#else
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/* set the jump target */
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static inline void tb_set_jmp_target(TranslationBlock *tb,
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int n, unsigned long addr)
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{
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tb->tb_next[n] = addr;
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}
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#endif
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static inline void tb_add_jump(TranslationBlock *tb, int n,
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TranslationBlock *tb_next)
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{
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/* NOTE: this test is only needed for thread safety */
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if (!tb->jmp_next[n]) {
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/* patch the native jump address */
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tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
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/* add in TB jmp circular list */
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tb->jmp_next[n] = tb_next->jmp_first;
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tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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}
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}
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TranslationBlock *tb_find_pc(unsigned long pc_ptr);
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#ifndef offsetof
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#define offsetof(type, field) ((size_t) &((type *)0)->field)
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#endif
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#if defined(_WIN32)
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#define ASM_DATA_SECTION ".section \".data\"\n"
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#define ASM_PREVIOUS_SECTION ".section .text\n"
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#elif defined(__APPLE__)
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#define ASM_DATA_SECTION ".data\n"
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#define ASM_PREVIOUS_SECTION ".text\n"
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#else
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#define ASM_DATA_SECTION ".section \".data\"\n"
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#define ASM_PREVIOUS_SECTION ".previous\n"
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#endif
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#define ASM_OP_LABEL_NAME(n, opname) \
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ASM_NAME(__op_label) #n "." ASM_NAME(opname)
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extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
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extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
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extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
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#if defined(__hppa__)
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typedef int spinlock_t[4];
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#define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 }
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static inline void resetlock (spinlock_t *p)
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{
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(*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1;
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}
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#else
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typedef int spinlock_t;
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#define SPIN_LOCK_UNLOCKED 0
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static inline void resetlock (spinlock_t *p)
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{
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*p = SPIN_LOCK_UNLOCKED;
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}
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#endif
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#if defined(__powerpc__)
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__ (
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"0: lwarx %0,0,%1\n"
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" xor. %0,%3,%0\n"
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" bne 1f\n"
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" stwcx. %2,0,%1\n"
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" bne- 0b\n"
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"1: "
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: "=&r" (ret)
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: "r" (p), "r" (1), "r" (0)
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: "cr0", "memory");
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return ret;
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}
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#elif defined(__i386__)
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static inline int testandset (int *p)
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{
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long int readval = 0;
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__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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: "+m" (*p), "+a" (readval)
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: "r" (1)
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: "cc");
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return readval;
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}
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#elif defined(__x86_64__)
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static inline int testandset (int *p)
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{
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long int readval = 0;
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__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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: "+m" (*p), "+a" (readval)
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: "r" (1)
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: "cc");
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return readval;
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}
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#elif defined(__s390__)
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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" jl 0b"
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: "=&d" (ret)
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: "r" (1), "a" (p), "0" (*p)
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: "cc", "memory" );
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return ret;
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}
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#elif defined(__alpha__)
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static inline int testandset (int *p)
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{
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int ret;
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unsigned long one;
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__asm__ __volatile__ ("0: mov 1,%2\n"
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" ldl_l %0,%1\n"
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" stl_c %2,%1\n"
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" beq %2,1f\n"
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".subsection 2\n"
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"1: br 0b\n"
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".previous"
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: "=r" (ret), "=m" (*p), "=r" (one)
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: "m" (*p));
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return ret;
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}
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#elif defined(__sparc__)
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__("ldstub [%1], %0"
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: "=r" (ret)
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: "r" (p)
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: "memory");
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return (ret ? 1 : 0);
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}
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#elif defined(__arm__)
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static inline int testandset (int *spinlock)
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{
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register unsigned int ret;
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__asm__ __volatile__("swp %0, %1, [%2]"
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: "=r"(ret)
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: "0"(1), "r"(spinlock));
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return ret;
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}
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#elif defined(__mc68000)
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static inline int testandset (int *p)
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{
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char ret;
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__asm__ __volatile__("tas %1; sne %0"
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: "=r" (ret)
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: "m" (p)
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: "cc","memory");
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return ret;
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}
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#elif defined(__hppa__)
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/* Because malloc only guarantees 8-byte alignment for malloc'd data,
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and GCC only guarantees 8-byte alignment for stack locals, we can't
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be assured of 16-byte alignment for atomic lock data even if we
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specify "__attribute ((aligned(16)))" in the type declaration. So,
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we use a struct containing an array of four ints for the atomic lock
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type and dynamically select the 16-byte aligned int from the array
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for the semaphore. */
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#define __PA_LDCW_ALIGNMENT 16
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static inline void *ldcw_align (void *p) {
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unsigned long a = (unsigned long)p;
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a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1);
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return (void *)a;
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}
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static inline int testandset (spinlock_t *p)
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{
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unsigned int ret;
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p = ldcw_align(p);
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__asm__ __volatile__("ldcw 0(%1),%0"
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: "=r" (ret)
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: "r" (p)
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: "memory" );
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return !ret;
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}
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#elif defined(__ia64)
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#include <ia64intrin.h>
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static inline int testandset (int *p)
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{
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return __sync_lock_test_and_set (p, 1);
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}
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#elif defined(__mips__)
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__ (
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" .set push \n"
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" .set noat \n"
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" .set mips2 \n"
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"1: li $1, 1 \n"
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" ll %0, %1 \n"
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" sc $1, %1 \n"
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" beqz $1, 1b \n"
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" .set pop "
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: "=r" (ret), "+R" (*p)
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:
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: "memory");
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return ret;
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}
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#else
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#error unimplemented CPU support
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#endif
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#if defined(CONFIG_USER_ONLY)
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|
static inline void spin_lock(spinlock_t *lock)
|
|
{
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|
while (testandset(lock));
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|
}
|
|
|
|
static inline void spin_unlock(spinlock_t *lock)
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|
{
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|
resetlock(lock);
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|
}
|
|
|
|
static inline int spin_trylock(spinlock_t *lock)
|
|
{
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|
return !testandset(lock);
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|
}
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|
#else
|
|
static inline void spin_lock(spinlock_t *lock)
|
|
{
|
|
}
|
|
|
|
static inline void spin_unlock(spinlock_t *lock)
|
|
{
|
|
}
|
|
|
|
static inline int spin_trylock(spinlock_t *lock)
|
|
{
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|
return 1;
|
|
}
|
|
#endif
|
|
|
|
extern spinlock_t tb_lock;
|
|
|
|
extern int tb_invalidated_flag;
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
|
|
void *retaddr);
|
|
|
|
#define ACCESS_TYPE (NB_MMU_MODES + 1)
|
|
#define MEMSUFFIX _code
|
|
#define env cpu_single_env
|
|
|
|
#define DATA_SIZE 1
|
|
#include "softmmu_header.h"
|
|
|
|
#define DATA_SIZE 2
|
|
#include "softmmu_header.h"
|
|
|
|
#define DATA_SIZE 4
|
|
#include "softmmu_header.h"
|
|
|
|
#define DATA_SIZE 8
|
|
#include "softmmu_header.h"
|
|
|
|
#undef ACCESS_TYPE
|
|
#undef MEMSUFFIX
|
|
#undef env
|
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
|
|
{
|
|
return addr;
|
|
}
|
|
#else
|
|
/* NOTE: this function can trigger an exception */
|
|
/* NOTE2: the returned address is not exactly the physical address: it
|
|
is the offset relative to phys_ram_base */
|
|
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
|
|
{
|
|
int mmu_idx, index, pd;
|
|
|
|
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
|
mmu_idx = cpu_mmu_index(env);
|
|
if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
|
|
(addr & TARGET_PAGE_MASK), 0)) {
|
|
ldub_code(addr);
|
|
}
|
|
pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK;
|
|
if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
|
|
#if defined(TARGET_SPARC) || defined(TARGET_MIPS)
|
|
do_unassigned_access(addr, 0, 1, 0);
|
|
#else
|
|
cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
|
|
#endif
|
|
}
|
|
return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base;
|
|
}
|
|
#endif
|
|
|
|
#ifdef USE_KQEMU
|
|
#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
|
|
|
|
int kqemu_init(CPUState *env);
|
|
int kqemu_cpu_exec(CPUState *env);
|
|
void kqemu_flush_page(CPUState *env, target_ulong addr);
|
|
void kqemu_flush(CPUState *env, int global);
|
|
void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
|
|
void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
|
|
void kqemu_cpu_interrupt(CPUState *env);
|
|
void kqemu_record_dump(void);
|
|
|
|
static inline int kqemu_is_ok(CPUState *env)
|
|
{
|
|
return(env->kqemu_enabled &&
|
|
(env->cr[0] & CR0_PE_MASK) &&
|
|
!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
|
|
(env->eflags & IF_MASK) &&
|
|
!(env->eflags & VM_MASK) &&
|
|
(env->kqemu_enabled == 2 ||
|
|
((env->hflags & HF_CPL_MASK) == 3 &&
|
|
(env->eflags & IOPL_MASK) != IOPL_MASK)));
|
|
}
|
|
|
|
#endif
|