bc72ad6754
This is an autogenerated patch using scripts/switch-timer-api. Switch the entire code base to using the new timer API. Note this patch may introduce some line length issues. Signed-off-by: Alex Bligh <alex@alex.org.uk> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
796 lines
21 KiB
C
796 lines
21 KiB
C
/*
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* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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*
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* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h"
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#include "hw/timer/m48t59.h"
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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#include "hw/sysbus.h"
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#include "hw/isa/isa.h"
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#include "exec/address-spaces.h"
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//#define DEBUG_NVRAM
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#if defined(DEBUG_NVRAM)
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#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
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#else
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#define NVRAM_PRINTF(fmt, ...) do { } while (0)
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#endif
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/*
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* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
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* alarm and a watchdog timer and related control registers. In the
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* PPC platform there is also a nvram lock function.
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*/
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/*
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* Chipset docs:
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* http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
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* http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
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* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
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*/
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struct M48t59State {
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/* Hardware parameters */
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qemu_irq IRQ;
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MemoryRegion iomem;
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uint32_t io_base;
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uint32_t size;
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/* RTC management */
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time_t time_offset;
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time_t stop_time;
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/* Alarm & watchdog */
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struct tm alarm;
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struct QEMUTimer *alrm_timer;
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struct QEMUTimer *wd_timer;
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/* NVRAM storage */
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uint8_t *buffer;
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/* Model parameters */
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uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
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/* NVRAM storage */
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uint16_t addr;
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uint8_t lock;
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};
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#define TYPE_ISA_M48T59 "m48t59_isa"
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#define ISA_M48T59(obj) \
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OBJECT_CHECK(M48t59ISAState, (obj), TYPE_ISA_M48T59)
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typedef struct M48t59ISAState {
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ISADevice parent_obj;
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M48t59State state;
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MemoryRegion io;
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} M48t59ISAState;
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#define SYSBUS_M48T59(obj) \
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OBJECT_CHECK(M48t59SysBusState, (obj), TYPE_SYSBUS_M48T59)
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typedef struct M48t59SysBusState {
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SysBusDevice parent_obj;
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M48t59State state;
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MemoryRegion io;
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} M48t59SysBusState;
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/* Fake timer functions */
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/* Alarm management */
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static void alarm_cb (void *opaque)
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{
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struct tm tm;
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uint64_t next_time;
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M48t59State *NVRAM = opaque;
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qemu_set_irq(NVRAM->IRQ, 1);
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if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once a month */
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qemu_get_timedate(&tm, NVRAM->time_offset);
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tm.tm_mon++;
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if (tm.tm_mon == 13) {
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tm.tm_mon = 1;
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tm.tm_year++;
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}
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next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once a day */
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next_time = 24 * 60 * 60;
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once an hour */
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next_time = 60 * 60;
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once a minute */
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next_time = 60;
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} else {
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/* Repeat once a second */
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next_time = 1;
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}
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timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +
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next_time * 1000);
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qemu_set_irq(NVRAM->IRQ, 0);
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}
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static void set_alarm(M48t59State *NVRAM)
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{
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int diff;
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if (NVRAM->alrm_timer != NULL) {
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timer_del(NVRAM->alrm_timer);
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diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
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if (diff > 0)
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timer_mod(NVRAM->alrm_timer, diff * 1000);
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}
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}
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/* RTC management helpers */
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static inline void get_time(M48t59State *NVRAM, struct tm *tm)
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{
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qemu_get_timedate(tm, NVRAM->time_offset);
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}
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static void set_time(M48t59State *NVRAM, struct tm *tm)
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{
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NVRAM->time_offset = qemu_timedate_diff(tm);
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set_alarm(NVRAM);
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}
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/* Watchdog management */
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static void watchdog_cb (void *opaque)
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{
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M48t59State *NVRAM = opaque;
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NVRAM->buffer[0x1FF0] |= 0x80;
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if (NVRAM->buffer[0x1FF7] & 0x80) {
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NVRAM->buffer[0x1FF7] = 0x00;
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NVRAM->buffer[0x1FFC] &= ~0x40;
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/* May it be a hw CPU Reset instead ? */
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qemu_system_reset_request();
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} else {
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qemu_set_irq(NVRAM->IRQ, 1);
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qemu_set_irq(NVRAM->IRQ, 0);
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}
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}
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static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
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{
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uint64_t interval; /* in 1/16 seconds */
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NVRAM->buffer[0x1FF0] &= ~0x80;
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if (NVRAM->wd_timer != NULL) {
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timer_del(NVRAM->wd_timer);
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if (value != 0) {
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interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
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timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
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((interval * 1000) >> 4));
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}
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}
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}
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/* Direct access to NVRAM */
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void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
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{
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M48t59State *NVRAM = opaque;
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struct tm tm;
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int tmp;
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if (addr > 0x1FF8 && addr < 0x2000)
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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/* check for NVRAM access */
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if ((NVRAM->model == 2 && addr < 0x7f8) ||
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(NVRAM->model == 8 && addr < 0x1ff8) ||
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(NVRAM->model == 59 && addr < 0x1ff0)) {
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goto do_write;
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}
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/* TOD access */
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switch (addr) {
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case 0x1FF0:
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/* flags register : read-only */
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break;
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case 0x1FF1:
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/* unused */
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break;
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case 0x1FF2:
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/* alarm seconds */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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NVRAM->alarm.tm_sec = tmp;
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NVRAM->buffer[0x1FF2] = val;
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set_alarm(NVRAM);
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}
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break;
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case 0x1FF3:
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/* alarm minutes */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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NVRAM->alarm.tm_min = tmp;
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NVRAM->buffer[0x1FF3] = val;
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set_alarm(NVRAM);
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}
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break;
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case 0x1FF4:
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/* alarm hours */
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tmp = from_bcd(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) {
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NVRAM->alarm.tm_hour = tmp;
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NVRAM->buffer[0x1FF4] = val;
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set_alarm(NVRAM);
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}
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break;
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case 0x1FF5:
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/* alarm date */
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tmp = from_bcd(val & 0x3F);
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if (tmp != 0) {
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NVRAM->alarm.tm_mday = tmp;
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NVRAM->buffer[0x1FF5] = val;
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set_alarm(NVRAM);
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}
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break;
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case 0x1FF6:
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/* interrupts */
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NVRAM->buffer[0x1FF6] = val;
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break;
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case 0x1FF7:
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/* watchdog */
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NVRAM->buffer[0x1FF7] = val;
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set_up_watchdog(NVRAM, val);
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break;
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case 0x1FF8:
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case 0x07F8:
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/* control */
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NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
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break;
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case 0x1FF9:
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case 0x07F9:
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/* seconds (BCD) */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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get_time(NVRAM, &tm);
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tm.tm_sec = tmp;
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set_time(NVRAM, &tm);
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}
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if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
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if (val & 0x80) {
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NVRAM->stop_time = time(NULL);
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} else {
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NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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NVRAM->stop_time = 0;
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}
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}
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NVRAM->buffer[addr] = val & 0x80;
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break;
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case 0x1FFA:
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case 0x07FA:
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/* minutes (BCD) */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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get_time(NVRAM, &tm);
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tm.tm_min = tmp;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFB:
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case 0x07FB:
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/* hours (BCD) */
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tmp = from_bcd(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) {
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get_time(NVRAM, &tm);
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tm.tm_hour = tmp;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFC:
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case 0x07FC:
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/* day of the week / century */
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tmp = from_bcd(val & 0x07);
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get_time(NVRAM, &tm);
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tm.tm_wday = tmp;
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set_time(NVRAM, &tm);
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NVRAM->buffer[addr] = val & 0x40;
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break;
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case 0x1FFD:
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case 0x07FD:
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/* date (BCD) */
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tmp = from_bcd(val & 0x3F);
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if (tmp != 0) {
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get_time(NVRAM, &tm);
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tm.tm_mday = tmp;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFE:
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case 0x07FE:
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/* month */
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tmp = from_bcd(val & 0x1F);
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if (tmp >= 1 && tmp <= 12) {
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get_time(NVRAM, &tm);
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tm.tm_mon = tmp - 1;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFF:
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case 0x07FF:
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/* year */
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tmp = from_bcd(val);
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if (tmp >= 0 && tmp <= 99) {
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get_time(NVRAM, &tm);
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if (NVRAM->model == 8) {
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tm.tm_year = from_bcd(val) + 68; // Base year is 1968
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} else {
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tm.tm_year = from_bcd(val);
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}
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set_time(NVRAM, &tm);
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}
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break;
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default:
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/* Check lock registers state */
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if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
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break;
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if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
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break;
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do_write:
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if (addr < NVRAM->size) {
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NVRAM->buffer[addr] = val & 0xFF;
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}
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break;
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}
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}
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uint32_t m48t59_read (void *opaque, uint32_t addr)
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{
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M48t59State *NVRAM = opaque;
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struct tm tm;
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uint32_t retval = 0xFF;
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/* check for NVRAM access */
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if ((NVRAM->model == 2 && addr < 0x078f) ||
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(NVRAM->model == 8 && addr < 0x1ff8) ||
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(NVRAM->model == 59 && addr < 0x1ff0)) {
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goto do_read;
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}
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/* TOD access */
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switch (addr) {
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case 0x1FF0:
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/* flags register */
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goto do_read;
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case 0x1FF1:
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/* unused */
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retval = 0;
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break;
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case 0x1FF2:
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/* alarm seconds */
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goto do_read;
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case 0x1FF3:
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/* alarm minutes */
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goto do_read;
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case 0x1FF4:
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/* alarm hours */
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goto do_read;
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case 0x1FF5:
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/* alarm date */
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goto do_read;
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case 0x1FF6:
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/* interrupts */
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goto do_read;
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case 0x1FF7:
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/* A read resets the watchdog */
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set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
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goto do_read;
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case 0x1FF8:
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case 0x07F8:
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/* control */
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goto do_read;
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case 0x1FF9:
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case 0x07F9:
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/* seconds (BCD) */
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get_time(NVRAM, &tm);
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retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
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break;
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case 0x1FFA:
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case 0x07FA:
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/* minutes (BCD) */
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get_time(NVRAM, &tm);
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retval = to_bcd(tm.tm_min);
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break;
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case 0x1FFB:
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case 0x07FB:
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/* hours (BCD) */
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get_time(NVRAM, &tm);
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retval = to_bcd(tm.tm_hour);
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break;
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case 0x1FFC:
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case 0x07FC:
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/* day of the week / century */
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get_time(NVRAM, &tm);
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retval = NVRAM->buffer[addr] | tm.tm_wday;
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break;
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case 0x1FFD:
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case 0x07FD:
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/* date */
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get_time(NVRAM, &tm);
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retval = to_bcd(tm.tm_mday);
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break;
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case 0x1FFE:
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case 0x07FE:
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/* month */
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get_time(NVRAM, &tm);
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retval = to_bcd(tm.tm_mon + 1);
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break;
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case 0x1FFF:
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case 0x07FF:
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/* year */
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get_time(NVRAM, &tm);
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if (NVRAM->model == 8) {
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retval = to_bcd(tm.tm_year - 68); // Base year is 1968
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} else {
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retval = to_bcd(tm.tm_year);
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}
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break;
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default:
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/* Check lock registers state */
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if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
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break;
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if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
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break;
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do_read:
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if (addr < NVRAM->size) {
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retval = NVRAM->buffer[addr];
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}
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break;
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}
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if (addr > 0x1FF9 && addr < 0x2000)
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NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
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return retval;
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}
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void m48t59_toggle_lock (void *opaque, int lock)
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{
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M48t59State *NVRAM = opaque;
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NVRAM->lock ^= 1 << lock;
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}
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/* IO access to NVRAM */
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static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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M48t59State *NVRAM = opaque;
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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switch (addr) {
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case 0:
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NVRAM->addr &= ~0x00FF;
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NVRAM->addr |= val;
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break;
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case 1:
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NVRAM->addr &= ~0xFF00;
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NVRAM->addr |= val << 8;
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break;
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case 3:
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m48t59_write(NVRAM, NVRAM->addr, val);
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NVRAM->addr = 0x0000;
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break;
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default:
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break;
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}
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}
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static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)
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{
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M48t59State *NVRAM = opaque;
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uint32_t retval;
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switch (addr) {
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case 3:
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retval = m48t59_read(NVRAM, NVRAM->addr);
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break;
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default:
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retval = -1;
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break;
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}
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NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
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return retval;
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}
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static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value)
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{
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M48t59State *NVRAM = opaque;
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m48t59_write(NVRAM, addr, value & 0xff);
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}
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static void nvram_writew (void *opaque, hwaddr addr, uint32_t value)
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{
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M48t59State *NVRAM = opaque;
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m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
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m48t59_write(NVRAM, addr + 1, value & 0xff);
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}
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static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)
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{
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M48t59State *NVRAM = opaque;
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m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
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m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
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m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
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m48t59_write(NVRAM, addr + 3, value & 0xff);
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}
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static uint32_t nvram_readb (void *opaque, hwaddr addr)
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{
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M48t59State *NVRAM = opaque;
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uint32_t retval;
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retval = m48t59_read(NVRAM, addr);
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return retval;
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}
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static uint32_t nvram_readw (void *opaque, hwaddr addr)
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{
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M48t59State *NVRAM = opaque;
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uint32_t retval;
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retval = m48t59_read(NVRAM, addr) << 8;
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retval |= m48t59_read(NVRAM, addr + 1);
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return retval;
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}
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static uint32_t nvram_readl (void *opaque, hwaddr addr)
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{
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M48t59State *NVRAM = opaque;
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uint32_t retval;
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retval = m48t59_read(NVRAM, addr) << 24;
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retval |= m48t59_read(NVRAM, addr + 1) << 16;
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retval |= m48t59_read(NVRAM, addr + 2) << 8;
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retval |= m48t59_read(NVRAM, addr + 3);
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return retval;
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}
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static const MemoryRegionOps nvram_ops = {
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.old_mmio = {
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.read = { nvram_readb, nvram_readw, nvram_readl, },
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.write = { nvram_writeb, nvram_writew, nvram_writel, },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_m48t59 = {
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.name = "m48t59",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(lock, M48t59State),
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VMSTATE_UINT16(addr, M48t59State),
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VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size),
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VMSTATE_END_OF_LIST()
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}
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};
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static void m48t59_reset_common(M48t59State *NVRAM)
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{
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NVRAM->addr = 0;
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NVRAM->lock = 0;
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if (NVRAM->alrm_timer != NULL)
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timer_del(NVRAM->alrm_timer);
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if (NVRAM->wd_timer != NULL)
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timer_del(NVRAM->wd_timer);
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}
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static void m48t59_reset_isa(DeviceState *d)
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{
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M48t59ISAState *isa = ISA_M48T59(d);
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M48t59State *NVRAM = &isa->state;
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m48t59_reset_common(NVRAM);
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}
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static void m48t59_reset_sysbus(DeviceState *d)
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{
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M48t59SysBusState *sys = SYSBUS_M48T59(d);
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M48t59State *NVRAM = &sys->state;
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m48t59_reset_common(NVRAM);
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}
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static const MemoryRegionOps m48t59_io_ops = {
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.read = NVRAM_readb,
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.write = NVRAM_writeb,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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/* Initialisation routine */
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M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
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uint32_t io_base, uint16_t size, int model)
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{
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DeviceState *dev;
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SysBusDevice *s;
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M48t59SysBusState *d;
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M48t59State *state;
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dev = qdev_create(NULL, TYPE_SYSBUS_M48T59);
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qdev_prop_set_uint32(dev, "model", model);
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qdev_prop_set_uint32(dev, "size", size);
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qdev_prop_set_uint32(dev, "io_base", io_base);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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d = SYSBUS_M48T59(dev);
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state = &d->state;
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sysbus_connect_irq(s, 0, IRQ);
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memory_region_init_io(&d->io, OBJECT(d), &m48t59_io_ops, state,
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"m48t59", 4);
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if (io_base != 0) {
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memory_region_add_subregion(get_system_io(), io_base, &d->io);
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}
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if (mem_base != 0) {
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sysbus_mmio_map(s, 0, mem_base);
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}
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return state;
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}
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M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
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int model)
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{
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M48t59ISAState *d;
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ISADevice *isadev;
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DeviceState *dev;
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M48t59State *s;
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isadev = isa_create(bus, TYPE_ISA_M48T59);
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dev = DEVICE(isadev);
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qdev_prop_set_uint32(dev, "model", model);
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qdev_prop_set_uint32(dev, "size", size);
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qdev_prop_set_uint32(dev, "io_base", io_base);
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qdev_init_nofail(dev);
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d = ISA_M48T59(isadev);
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s = &d->state;
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memory_region_init_io(&d->io, OBJECT(d), &m48t59_io_ops, s, "m48t59", 4);
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if (io_base != 0) {
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isa_register_ioport(isadev, &d->io, io_base);
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}
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return s;
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}
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static void m48t59_realize_common(M48t59State *s, Error **errp)
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{
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s->buffer = g_malloc0(s->size);
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if (s->model == 59) {
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s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);
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s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
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}
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qemu_get_timedate(&s->alarm, 0);
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vmstate_register(NULL, -1, &vmstate_m48t59, s);
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}
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static void m48t59_isa_realize(DeviceState *dev, Error **errp)
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{
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ISADevice *isadev = ISA_DEVICE(dev);
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M48t59ISAState *d = ISA_M48T59(dev);
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M48t59State *s = &d->state;
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isa_init_irq(isadev, &s->IRQ, 8);
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m48t59_realize_common(s, errp);
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}
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static int m48t59_init1(SysBusDevice *dev)
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{
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M48t59SysBusState *d = SYSBUS_M48T59(dev);
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M48t59State *s = &d->state;
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Error *err = NULL;
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sysbus_init_irq(dev, &s->IRQ);
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memory_region_init_io(&s->iomem, OBJECT(d), &nvram_ops, s,
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"m48t59.nvram", s->size);
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sysbus_init_mmio(dev, &s->iomem);
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m48t59_realize_common(s, &err);
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if (err != NULL) {
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error_free(err);
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return -1;
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}
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return 0;
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}
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static Property m48t59_isa_properties[] = {
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DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1),
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DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1),
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DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void m48t59_isa_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = m48t59_isa_realize;
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dc->no_user = 1;
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dc->reset = m48t59_reset_isa;
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dc->props = m48t59_isa_properties;
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}
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static const TypeInfo m48t59_isa_info = {
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.name = TYPE_ISA_M48T59,
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(M48t59ISAState),
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.class_init = m48t59_isa_class_init,
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};
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static Property m48t59_properties[] = {
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DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1),
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DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1),
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DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void m48t59_class_init(ObjectClass *klass, void *data)
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{
|
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = m48t59_init1;
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dc->reset = m48t59_reset_sysbus;
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dc->props = m48t59_properties;
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}
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static const TypeInfo m48t59_info = {
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.name = TYPE_SYSBUS_M48T59,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(M48t59SysBusState),
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.class_init = m48t59_class_init,
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};
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static void m48t59_register_types(void)
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{
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type_register_static(&m48t59_info);
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type_register_static(&m48t59_isa_info);
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}
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type_init(m48t59_register_types)
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