445416e301
Currently the only implementers of ARI is SR-IOV devices, and they behave similar. Share the ARI next function number. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Ani Sinha <anisinha@redhat.com> Message-Id: <20230710153838.33917-2-akihiko.odaki@daynix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
321 lines
9.3 KiB
C
321 lines
9.3 KiB
C
/*
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* QEMU Intel 82576 SR/IOV Ethernet Controller Emulation
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*
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* Datasheet:
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* https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf
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*
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* Copyright (c) 2020-2023 Red Hat, Inc.
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* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
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* Developed by Daynix Computing LTD (http://www.daynix.com)
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*
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* Authors:
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* Akihiko Odaki <akihiko.odaki@daynix.com>
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* Gal Hammmer <gal.hammer@sap.com>
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* Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
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* Dmitry Fleytman <dmitry@daynix.com>
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* Leonid Bloch <leonid@daynix.com>
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* Yan Vugenfirer <yan@daynix.com>
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*
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* Based on work done by:
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* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
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* Copyright (c) 2008 Qumranet
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* Based on work done by:
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* Copyright (c) 2007 Dan Aloni
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* Copyright (c) 2004 Antony T Curtis
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/net/mii.h"
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#include "hw/pci/pci_device.h"
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#include "hw/pci/pcie.h"
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#include "hw/pci/msix.h"
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#include "net/eth.h"
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#include "net/net.h"
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#include "igb_common.h"
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#include "igb_core.h"
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#include "trace.h"
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#include "qapi/error.h"
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OBJECT_DECLARE_SIMPLE_TYPE(IgbVfState, IGBVF)
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struct IgbVfState {
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PCIDevice parent_obj;
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MemoryRegion mmio;
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MemoryRegion msix;
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};
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static hwaddr vf_to_pf_addr(hwaddr addr, uint16_t vfn, bool write)
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{
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switch (addr) {
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case E1000_CTRL:
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case E1000_CTRL_DUP:
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return E1000_PVTCTRL(vfn);
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case E1000_EICS:
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return E1000_PVTEICS(vfn);
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case E1000_EIMS:
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return E1000_PVTEIMS(vfn);
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case E1000_EIMC:
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return E1000_PVTEIMC(vfn);
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case E1000_EIAC:
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return E1000_PVTEIAC(vfn);
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case E1000_EIAM:
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return E1000_PVTEIAM(vfn);
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case E1000_EICR:
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return E1000_PVTEICR(vfn);
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case E1000_EITR(0):
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case E1000_EITR(1):
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case E1000_EITR(2):
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return E1000_EITR(22) + (addr - E1000_EITR(0)) - vfn * 0xC;
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case E1000_IVAR0:
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return E1000_VTIVAR + vfn * 4;
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case E1000_IVAR_MISC:
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return E1000_VTIVAR_MISC + vfn * 4;
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case 0x0F04: /* PBACL */
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return E1000_PBACLR;
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case 0x0F0C: /* PSRTYPE */
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return E1000_PSRTYPE(vfn);
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case E1000_V2PMAILBOX(0):
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return E1000_V2PMAILBOX(vfn);
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case E1000_VMBMEM(0) ... E1000_VMBMEM(0) + 0x3F:
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return addr + vfn * 0x40;
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case E1000_RDBAL_A(0):
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return E1000_RDBAL(vfn);
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case E1000_RDBAL_A(1):
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return E1000_RDBAL(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_RDBAH_A(0):
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return E1000_RDBAH(vfn);
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case E1000_RDBAH_A(1):
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return E1000_RDBAH(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_RDLEN_A(0):
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return E1000_RDLEN(vfn);
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case E1000_RDLEN_A(1):
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return E1000_RDLEN(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_SRRCTL_A(0):
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return E1000_SRRCTL(vfn);
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case E1000_SRRCTL_A(1):
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return E1000_SRRCTL(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_RDH_A(0):
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return E1000_RDH(vfn);
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case E1000_RDH_A(1):
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return E1000_RDH(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_RXCTL_A(0):
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return E1000_RXCTL(vfn);
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case E1000_RXCTL_A(1):
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return E1000_RXCTL(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_RDT_A(0):
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return E1000_RDT(vfn);
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case E1000_RDT_A(1):
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return E1000_RDT(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_RXDCTL_A(0):
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return E1000_RXDCTL(vfn);
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case E1000_RXDCTL_A(1):
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return E1000_RXDCTL(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_RQDPC_A(0):
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return E1000_RQDPC(vfn);
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case E1000_RQDPC_A(1):
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return E1000_RQDPC(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_TDBAL_A(0):
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return E1000_TDBAL(vfn);
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case E1000_TDBAL_A(1):
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return E1000_TDBAL(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_TDBAH_A(0):
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return E1000_TDBAH(vfn);
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case E1000_TDBAH_A(1):
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return E1000_TDBAH(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_TDLEN_A(0):
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return E1000_TDLEN(vfn);
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case E1000_TDLEN_A(1):
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return E1000_TDLEN(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_TDH_A(0):
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return E1000_TDH(vfn);
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case E1000_TDH_A(1):
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return E1000_TDH(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_TXCTL_A(0):
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return E1000_TXCTL(vfn);
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case E1000_TXCTL_A(1):
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return E1000_TXCTL(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_TDT_A(0):
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return E1000_TDT(vfn);
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case E1000_TDT_A(1):
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return E1000_TDT(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_TXDCTL_A(0):
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return E1000_TXDCTL(vfn);
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case E1000_TXDCTL_A(1):
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return E1000_TXDCTL(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_TDWBAL_A(0):
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return E1000_TDWBAL(vfn);
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case E1000_TDWBAL_A(1):
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return E1000_TDWBAL(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_TDWBAH_A(0):
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return E1000_TDWBAH(vfn);
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case E1000_TDWBAH_A(1):
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return E1000_TDWBAH(vfn + IGB_MAX_VF_FUNCTIONS);
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case E1000_VFGPRC:
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return E1000_PVFGPRC(vfn);
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case E1000_VFGPTC:
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return E1000_PVFGPTC(vfn);
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case E1000_VFGORC:
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return E1000_PVFGORC(vfn);
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case E1000_VFGOTC:
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return E1000_PVFGOTC(vfn);
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case E1000_VFMPRC:
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return E1000_PVFMPRC(vfn);
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case E1000_VFGPRLBC:
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return E1000_PVFGPRLBC(vfn);
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case E1000_VFGPTLBC:
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return E1000_PVFGPTLBC(vfn);
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case E1000_VFGORLBC:
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return E1000_PVFGORLBC(vfn);
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case E1000_VFGOTLBC:
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return E1000_PVFGOTLBC(vfn);
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case E1000_STATUS:
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case E1000_FRTIMER:
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if (write) {
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return HWADDR_MAX;
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}
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/* fallthrough */
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case 0x34E8: /* PBTWAC */
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case 0x24E8: /* PBRWAC */
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return addr;
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}
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trace_igbvf_wrn_io_addr_unknown(addr);
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return HWADDR_MAX;
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}
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static void igbvf_write_config(PCIDevice *dev, uint32_t addr, uint32_t val,
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int len)
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{
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trace_igbvf_write_config(addr, val, len);
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pci_default_write_config(dev, addr, val, len);
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}
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static uint64_t igbvf_mmio_read(void *opaque, hwaddr addr, unsigned size)
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{
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PCIDevice *vf = PCI_DEVICE(opaque);
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PCIDevice *pf = pcie_sriov_get_pf(vf);
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addr = vf_to_pf_addr(addr, pcie_sriov_vf_number(vf), false);
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return addr == HWADDR_MAX ? 0 : igb_mmio_read(pf, addr, size);
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}
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static void igbvf_mmio_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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PCIDevice *vf = PCI_DEVICE(opaque);
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PCIDevice *pf = pcie_sriov_get_pf(vf);
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addr = vf_to_pf_addr(addr, pcie_sriov_vf_number(vf), true);
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if (addr != HWADDR_MAX) {
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igb_mmio_write(pf, addr, val, size);
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}
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}
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static const MemoryRegionOps mmio_ops = {
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.read = igbvf_mmio_read,
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.write = igbvf_mmio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void igbvf_pci_realize(PCIDevice *dev, Error **errp)
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{
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IgbVfState *s = IGBVF(dev);
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int ret;
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int i;
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dev->config_write = igbvf_write_config;
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memory_region_init_io(&s->mmio, OBJECT(dev), &mmio_ops, s, "igbvf-mmio",
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IGBVF_MMIO_SIZE);
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pcie_sriov_vf_register_bar(dev, IGBVF_MMIO_BAR_IDX, &s->mmio);
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memory_region_init(&s->msix, OBJECT(dev), "igbvf-msix", IGBVF_MSIX_SIZE);
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pcie_sriov_vf_register_bar(dev, IGBVF_MSIX_BAR_IDX, &s->msix);
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ret = msix_init(dev, IGBVF_MSIX_VEC_NUM, &s->msix, IGBVF_MSIX_BAR_IDX, 0,
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&s->msix, IGBVF_MSIX_BAR_IDX, 0x2000, 0x70, errp);
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if (ret) {
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return;
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}
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for (i = 0; i < IGBVF_MSIX_VEC_NUM; i++) {
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msix_vector_use(dev, i);
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}
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if (pcie_endpoint_cap_init(dev, 0xa0) < 0) {
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hw_error("Failed to initialize PCIe capability");
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}
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if (pcie_aer_init(dev, 1, 0x100, 0x40, errp) < 0) {
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hw_error("Failed to initialize AER capability");
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}
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pcie_ari_init(dev, 0x150);
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}
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static void igbvf_pci_uninit(PCIDevice *dev)
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{
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IgbVfState *s = IGBVF(dev);
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pcie_aer_exit(dev);
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pcie_cap_exit(dev);
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msix_unuse_all_vectors(dev);
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msix_uninit(dev, &s->msix, &s->msix);
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}
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static void igbvf_class_init(ObjectClass *class, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(class);
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PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
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c->realize = igbvf_pci_realize;
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c->exit = igbvf_pci_uninit;
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c->vendor_id = PCI_VENDOR_ID_INTEL;
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c->device_id = E1000_DEV_ID_82576_VF;
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c->revision = 1;
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c->class_id = PCI_CLASS_NETWORK_ETHERNET;
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dc->desc = "Intel 82576 Virtual Function";
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dc->user_creatable = false;
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set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
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}
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static const TypeInfo igbvf_info = {
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.name = TYPE_IGBVF,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(IgbVfState),
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.class_init = igbvf_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ }
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},
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};
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static void igb_register_types(void)
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{
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type_register_static(&igbvf_info);
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}
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type_init(igb_register_types)
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