4a58330343
CXL switch CCIs were added in CXL r3.0. They are a PCI function, identified by class code that provides a CXL mailbox (identical to that previously defined for CXL type 3 memory devices) over which various FM-API commands may be used. Whilst the intent of this feature is enable switch control from a BMC attached to a switch upstream port, it is also useful to allow emulation of this feature on the upstream port connected to a host using the CXL devices as this greatly simplifies testing. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20231023160806.13206-7-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
257 lines
10 KiB
C
257 lines
10 KiB
C
/*
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* QEMU CXL Component
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*
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* Copyright (c) 2020 Intel
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef CXL_COMPONENT_H
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#define CXL_COMPONENT_H
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/* CXL 2.0 - 8.2.4 */
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#define CXL2_COMPONENT_IO_REGION_SIZE 0x1000
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#define CXL2_COMPONENT_CM_REGION_SIZE 0x1000
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#define CXL2_COMPONENT_BLOCK_SIZE 0x10000
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#include "qemu/range.h"
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#include "hw/cxl/cxl_cdat.h"
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#include "hw/register.h"
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#include "qapi/error.h"
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enum reg_type {
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CXL2_DEVICE,
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CXL2_TYPE3_DEVICE,
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CXL2_LOGICAL_DEVICE,
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CXL2_ROOT_PORT,
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CXL2_UPSTREAM_PORT,
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CXL2_DOWNSTREAM_PORT,
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CXL3_SWITCH_MAILBOX_CCI,
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};
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/*
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* Capability registers are defined at the top of the CXL.cache/mem region and
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* are packed. For our purposes we will always define the caps in the same
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* order.
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* CXL 2.0 - 8.2.5 Table 142 for details.
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*/
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/* CXL 2.0 - 8.2.5.1 */
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REG32(CXL_CAPABILITY_HEADER, 0)
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FIELD(CXL_CAPABILITY_HEADER, ID, 0, 16)
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FIELD(CXL_CAPABILITY_HEADER, VERSION, 16, 4)
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FIELD(CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 20, 4)
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FIELD(CXL_CAPABILITY_HEADER, ARRAY_SIZE, 24, 8)
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#define CXLx_CAPABILITY_HEADER(type, offset) \
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REG32(CXL_##type##_CAPABILITY_HEADER, offset) \
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FIELD(CXL_##type##_CAPABILITY_HEADER, ID, 0, 16) \
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FIELD(CXL_##type##_CAPABILITY_HEADER, VERSION, 16, 4) \
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FIELD(CXL_##type##_CAPABILITY_HEADER, PTR, 20, 12)
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CXLx_CAPABILITY_HEADER(RAS, 0x4)
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CXLx_CAPABILITY_HEADER(LINK, 0x8)
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CXLx_CAPABILITY_HEADER(HDM, 0xc)
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CXLx_CAPABILITY_HEADER(EXTSEC, 0x10)
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CXLx_CAPABILITY_HEADER(SNOOP, 0x14)
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/*
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* Capability structures contain the actual registers that the CXL component
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* implements. Some of these are specific to certain types of components, but
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* this implementation leaves enough space regardless.
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*/
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/* 8.2.5.9 - CXL RAS Capability Structure */
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/* Give ample space for caps before this */
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#define CXL_RAS_REGISTERS_OFFSET 0x80
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#define CXL_RAS_REGISTERS_SIZE 0x58
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REG32(CXL_RAS_UNC_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET)
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#define CXL_RAS_UNC_ERR_CACHE_DATA_PARITY 0
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#define CXL_RAS_UNC_ERR_CACHE_ADDRESS_PARITY 1
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#define CXL_RAS_UNC_ERR_CACHE_BE_PARITY 2
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#define CXL_RAS_UNC_ERR_CACHE_DATA_ECC 3
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#define CXL_RAS_UNC_ERR_MEM_DATA_PARITY 4
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#define CXL_RAS_UNC_ERR_MEM_ADDRESS_PARITY 5
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#define CXL_RAS_UNC_ERR_MEM_BE_PARITY 6
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#define CXL_RAS_UNC_ERR_MEM_DATA_ECC 7
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#define CXL_RAS_UNC_ERR_REINIT_THRESHOLD 8
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#define CXL_RAS_UNC_ERR_RSVD_ENCODING 9
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#define CXL_RAS_UNC_ERR_POISON_RECEIVED 10
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#define CXL_RAS_UNC_ERR_RECEIVER_OVERFLOW 11
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#define CXL_RAS_UNC_ERR_INTERNAL 14
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#define CXL_RAS_UNC_ERR_CXL_IDE_TX 15
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#define CXL_RAS_UNC_ERR_CXL_IDE_RX 16
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#define CXL_RAS_UNC_ERR_CXL_UNUSED 63 /* Magic value */
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REG32(CXL_RAS_UNC_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x4)
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REG32(CXL_RAS_UNC_ERR_SEVERITY, CXL_RAS_REGISTERS_OFFSET + 0x8)
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REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc)
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#define CXL_RAS_COR_ERR_CACHE_DATA_ECC 0
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#define CXL_RAS_COR_ERR_MEM_DATA_ECC 1
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#define CXL_RAS_COR_ERR_CRC_THRESHOLD 2
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#define CXL_RAS_COR_ERR_RETRY_THRESHOLD 3
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#define CXL_RAS_COR_ERR_CACHE_POISON_RECEIVED 4
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#define CXL_RAS_COR_ERR_MEM_POISON_RECEIVED 5
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#define CXL_RAS_COR_ERR_PHYSICAL 6
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REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10)
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REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14)
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FIELD(CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER, 0, 6)
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REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18)
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#define CXL_RAS_ERR_HEADER_NUM 32
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/* Offset 0x18 - 0x58 reserved for RAS logs */
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/* 8.2.5.10 - CXL Security Capability Structure */
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#define CXL_SEC_REGISTERS_OFFSET \
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(CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE)
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#define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream ports */
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/* 8.2.5.11 - CXL Link Capability Structure */
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#define CXL_LINK_REGISTERS_OFFSET \
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(CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE)
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#define CXL_LINK_REGISTERS_SIZE 0x38
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/* 8.2.5.12 - CXL HDM Decoder Capability Structure */
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#define HDM_DECODE_MAX 10 /* 8.2.5.12.1 */
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#define CXL_HDM_REGISTERS_OFFSET \
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(CXL_LINK_REGISTERS_OFFSET + CXL_LINK_REGISTERS_SIZE)
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#define CXL_HDM_REGISTERS_SIZE (0x10 + 0x20 * HDM_DECODE_MAX)
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#define HDM_DECODER_INIT(n) \
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REG32(CXL_HDM_DECODER##n##_BASE_LO, \
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CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x10) \
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FIELD(CXL_HDM_DECODER##n##_BASE_LO, L, 28, 4) \
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REG32(CXL_HDM_DECODER##n##_BASE_HI, \
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CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x14) \
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REG32(CXL_HDM_DECODER##n##_SIZE_LO, \
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CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x18) \
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REG32(CXL_HDM_DECODER##n##_SIZE_HI, \
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CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x1C) \
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REG32(CXL_HDM_DECODER##n##_CTRL, \
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CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x20) \
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FIELD(CXL_HDM_DECODER##n##_CTRL, IG, 0, 4) \
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FIELD(CXL_HDM_DECODER##n##_CTRL, IW, 4, 4) \
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FIELD(CXL_HDM_DECODER##n##_CTRL, LOCK_ON_COMMIT, 8, 1) \
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FIELD(CXL_HDM_DECODER##n##_CTRL, COMMIT, 9, 1) \
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FIELD(CXL_HDM_DECODER##n##_CTRL, COMMITTED, 10, 1) \
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FIELD(CXL_HDM_DECODER##n##_CTRL, ERR, 11, 1) \
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FIELD(CXL_HDM_DECODER##n##_CTRL, TYPE, 12, 1) \
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REG32(CXL_HDM_DECODER##n##_TARGET_LIST_LO, \
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CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \
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REG32(CXL_HDM_DECODER##n##_TARGET_LIST_HI, \
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CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28) \
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REG32(CXL_HDM_DECODER##n##_DPA_SKIP_LO, \
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CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \
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REG32(CXL_HDM_DECODER##n##_DPA_SKIP_HI, \
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CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28)
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REG32(CXL_HDM_DECODER_CAPABILITY, CXL_HDM_REGISTERS_OFFSET)
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FIELD(CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, 0, 4)
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FIELD(CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 4, 4)
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FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 8, 1)
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FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 9, 1)
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FIELD(CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 10, 1)
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REG32(CXL_HDM_DECODER_GLOBAL_CONTROL, CXL_HDM_REGISTERS_OFFSET + 4)
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FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, POISON_ON_ERR_EN, 0, 1)
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FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 1, 1)
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/* Support 4 decoders at all levels of topology */
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#define CXL_HDM_DECODER_COUNT 4
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HDM_DECODER_INIT(0);
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HDM_DECODER_INIT(1);
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HDM_DECODER_INIT(2);
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HDM_DECODER_INIT(3);
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/* 8.2.5.13 - CXL Extended Security Capability Structure (Root complex only) */
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#define EXTSEC_ENTRY_MAX 256
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#define CXL_EXTSEC_REGISTERS_OFFSET \
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(CXL_HDM_REGISTERS_OFFSET + CXL_HDM_REGISTERS_SIZE)
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#define CXL_EXTSEC_REGISTERS_SIZE (8 * EXTSEC_ENTRY_MAX + 4)
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/* 8.2.5.14 - CXL IDE Capability Structure */
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#define CXL_IDE_REGISTERS_OFFSET \
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(CXL_EXTSEC_REGISTERS_OFFSET + CXL_EXTSEC_REGISTERS_SIZE)
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#define CXL_IDE_REGISTERS_SIZE 0x20
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/* 8.2.5.15 - CXL Snoop Filter Capability Structure */
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#define CXL_SNOOP_REGISTERS_OFFSET \
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(CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE)
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#define CXL_SNOOP_REGISTERS_SIZE 0x8
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QEMU_BUILD_BUG_MSG((CXL_SNOOP_REGISTERS_OFFSET +
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CXL_SNOOP_REGISTERS_SIZE) >= 0x1000,
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"No space for registers");
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typedef struct component_registers {
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/*
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* Main memory region to be registered with QEMU core.
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*/
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MemoryRegion component_registers;
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/*
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* 8.2.4 Table 141:
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* 0x0000 - 0x0fff CXL.io registers
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* 0x1000 - 0x1fff CXL.cache and CXL.mem
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* 0x2000 - 0xdfff Implementation specific
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* 0xe000 - 0xe3ff CXL ARB/MUX registers
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* 0xe400 - 0xffff RSVD
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*/
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uint32_t io_registers[CXL2_COMPONENT_IO_REGION_SIZE >> 2];
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MemoryRegion io;
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uint32_t cache_mem_registers[CXL2_COMPONENT_CM_REGION_SIZE >> 2];
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uint32_t cache_mem_regs_write_mask[CXL2_COMPONENT_CM_REGION_SIZE >> 2];
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MemoryRegion cache_mem;
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MemoryRegion impl_specific;
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MemoryRegion arb_mux;
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MemoryRegion rsvd;
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/* special_ops is used for any component that needs any specific handling */
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MemoryRegionOps *special_ops;
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} ComponentRegisters;
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/*
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* A CXL component represents all entities in a CXL hierarchy. This includes,
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* host bridges, root ports, upstream/downstream switch ports, and devices
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*/
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typedef struct cxl_component {
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ComponentRegisters crb;
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union {
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struct {
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Range dvsecs[CXL20_MAX_DVSEC];
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uint16_t dvsec_offset;
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struct PCIDevice *pdev;
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};
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};
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CDATObject cdat;
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} CXLComponentState;
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void cxl_component_register_block_init(Object *obj,
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CXLComponentState *cxl_cstate,
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const char *type);
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void cxl_component_register_init_common(uint32_t *reg_state,
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uint32_t *write_msk,
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enum reg_type type);
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void cxl_component_create_dvsec(CXLComponentState *cxl_cstate,
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enum reg_type cxl_dev_type, uint16_t length,
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uint16_t type, uint8_t rev, uint8_t *body);
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int cxl_decoder_count_enc(int count);
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int cxl_decoder_count_dec(int enc_cnt);
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uint8_t cxl_interleave_ways_enc(int iw, Error **errp);
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int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp);
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uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp);
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hwaddr cxl_decode_ig(int ig);
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CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb);
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bool cxl_get_hb_passthrough(PCIHostState *hb);
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void cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp);
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void cxl_doe_cdat_release(CXLComponentState *cxl_cstate);
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void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp);
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#endif
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