 c04274f49e
			
		
	
	
		c04274f49e
		
	
	
	
	
		
			
			To have a clean separation between s390-pci-bus.h and s390-pci-inst.h headers we export the PCI CLP instructions in a dedicated header. Signed-off-by: Pierre Morel <pmorel@linux.ibm.com> Signed-off-by: Matthew Rosato <mjrosato@linux.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
		
			
				
	
	
		
			120 lines
		
	
	
		
			4.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			120 lines
		
	
	
		
			4.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * s390 PCI instruction definitions
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|  *
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|  * Copyright 2014 IBM Corp.
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|  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
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|  *            Hong Bo Li <lihbbj@cn.ibm.com>
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|  *            Yi Min Zhao <zyimin@cn.ibm.com>
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|  *
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|  * This work is licensed under the terms of the GNU GPL, version 2 or (at
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|  * your option) any later version. See the COPYING file in the top-level
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|  * directory.
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|  */
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| 
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| #ifndef HW_S390_PCI_INST_H
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| #define HW_S390_PCI_INST_H
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| 
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| #include "s390-pci-bus.h"
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| #include "sysemu/dma.h"
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| 
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| /* Load/Store status codes */
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| #define ZPCI_PCI_ST_FUNC_NOT_ENABLED        4
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| #define ZPCI_PCI_ST_FUNC_IN_ERR             8
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| #define ZPCI_PCI_ST_BLOCKED                 12
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| #define ZPCI_PCI_ST_INSUF_RES               16
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| #define ZPCI_PCI_ST_INVAL_AS                20
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| #define ZPCI_PCI_ST_FUNC_ALREADY_ENABLED    24
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| #define ZPCI_PCI_ST_DMA_AS_NOT_ENABLED      28
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| #define ZPCI_PCI_ST_2ND_OP_IN_INV_AS        36
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| #define ZPCI_PCI_ST_FUNC_NOT_AVAIL          40
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| #define ZPCI_PCI_ST_ALREADY_IN_RQ_STATE     44
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| 
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| /* Load/Store return codes */
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| #define ZPCI_PCI_LS_OK              0
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| #define ZPCI_PCI_LS_ERR             1
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| #define ZPCI_PCI_LS_BUSY            2
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| #define ZPCI_PCI_LS_INVAL_HANDLE    3
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| 
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| /* Modify PCI status codes */
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| #define ZPCI_MOD_ST_RES_NOT_AVAIL 4
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| #define ZPCI_MOD_ST_INSUF_RES     16
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| #define ZPCI_MOD_ST_SEQUENCE      24
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| #define ZPCI_MOD_ST_DMAAS_INVAL   28
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| #define ZPCI_MOD_ST_FRAME_INVAL   32
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| #define ZPCI_MOD_ST_ERROR_RECOVER 40
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| 
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| /* Modify PCI Function Controls */
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| #define ZPCI_MOD_FC_REG_INT     2
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| #define ZPCI_MOD_FC_DEREG_INT   3
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| #define ZPCI_MOD_FC_REG_IOAT    4
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| #define ZPCI_MOD_FC_DEREG_IOAT  5
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| #define ZPCI_MOD_FC_REREG_IOAT  6
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| #define ZPCI_MOD_FC_RESET_ERROR 7
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| #define ZPCI_MOD_FC_RESET_BLOCK 9
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| #define ZPCI_MOD_FC_SET_MEASURE 10
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| 
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| /* Store PCI Function Controls status codes */
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| #define ZPCI_STPCIFC_ST_PERM_ERROR    8
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| #define ZPCI_STPCIFC_ST_INVAL_DMAAS   28
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| #define ZPCI_STPCIFC_ST_ERROR_RECOVER 40
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| 
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| /* Refresh PCI Translations status codes */
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| #define ZPCI_RPCIT_ST_INSUFF_RES      16
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| 
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| /* FIB function controls */
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| #define ZPCI_FIB_FC_ENABLED     0x80
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| #define ZPCI_FIB_FC_ERROR       0x40
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| #define ZPCI_FIB_FC_LS_BLOCKED  0x20
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| #define ZPCI_FIB_FC_DMAAS_REG   0x10
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| 
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| /* FIB function controls */
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| #define ZPCI_FIB_FC_ENABLED     0x80
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| #define ZPCI_FIB_FC_ERROR       0x40
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| #define ZPCI_FIB_FC_LS_BLOCKED  0x20
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| #define ZPCI_FIB_FC_DMAAS_REG   0x10
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| 
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| /* Function Information Block */
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| typedef struct ZpciFib {
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|     uint8_t fmt;   /* format */
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|     uint8_t reserved1[7];
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|     uint8_t fc;                  /* function controls */
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|     uint8_t reserved2;
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|     uint16_t reserved3;
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|     uint32_t reserved4;
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|     uint64_t pba;                /* PCI base address */
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|     uint64_t pal;                /* PCI address limit */
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|     uint64_t iota;               /* I/O Translation Anchor */
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| #define FIB_DATA_ISC(x)    (((x) >> 28) & 0x7)
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| #define FIB_DATA_NOI(x)    (((x) >> 16) & 0xfff)
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| #define FIB_DATA_AIBVO(x) (((x) >> 8) & 0x3f)
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| #define FIB_DATA_SUM(x)    (((x) >> 7) & 0x1)
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| #define FIB_DATA_AISBO(x)  ((x) & 0x3f)
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|     uint32_t data;
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|     uint32_t reserved5;
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|     uint64_t aibv;               /* Adapter int bit vector address */
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|     uint64_t aisb;               /* Adapter int summary bit address */
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|     uint64_t fmb_addr;           /* Function measurement address and key */
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|     uint32_t reserved6;
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|     uint32_t gd;
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| } QEMU_PACKED ZpciFib;
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| 
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| int pci_dereg_irqs(S390PCIBusDevice *pbdev);
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| void pci_dereg_ioat(S390PCIIOMMU *iommu);
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| int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra);
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| int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra);
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| int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra);
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| int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra);
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| int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
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|                         uint8_t ar, uintptr_t ra);
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| int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
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|                         uintptr_t ra);
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| int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
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|                          uintptr_t ra);
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| void fmb_timer_free(S390PCIBusDevice *pbdev);
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| 
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| #define ZPCI_IO_BAR_MIN 0
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| #define ZPCI_IO_BAR_MAX 5
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| #define ZPCI_CONFIG_BAR 15
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| 
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| #endif
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