89ece6f76f
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_e_prci model to hw/misc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
126 lines
3.8 KiB
C
126 lines
3.8 KiB
C
/*
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* QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt)
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* Simple model of the PRCI to emulate register reads made by the SDK BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/hw.h"
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#include "hw/misc/sifive_e_prci.h"
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static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
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{
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SiFiveEPRCIState *s = opaque;
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switch (addr) {
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case SIFIVE_E_PRCI_HFROSCCFG:
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return s->hfrosccfg;
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case SIFIVE_E_PRCI_HFXOSCCFG:
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return s->hfxosccfg;
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case SIFIVE_E_PRCI_PLLCFG:
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return s->pllcfg;
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case SIFIVE_E_PRCI_PLLOUTDIV:
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return s->plloutdiv;
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}
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qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n",
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__func__, (int)addr);
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return 0;
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}
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static void sifive_e_prci_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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SiFiveEPRCIState *s = opaque;
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switch (addr) {
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case SIFIVE_E_PRCI_HFROSCCFG:
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s->hfrosccfg = (uint32_t) val64;
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/* OSC stays ready */
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s->hfrosccfg |= SIFIVE_E_PRCI_HFROSCCFG_RDY;
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break;
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case SIFIVE_E_PRCI_HFXOSCCFG:
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s->hfxosccfg = (uint32_t) val64;
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/* OSC stays ready */
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s->hfxosccfg |= SIFIVE_E_PRCI_HFXOSCCFG_RDY;
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break;
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case SIFIVE_E_PRCI_PLLCFG:
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s->pllcfg = (uint32_t) val64;
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/* PLL stays locked */
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s->pllcfg |= SIFIVE_E_PRCI_PLLCFG_LOCK;
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break;
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case SIFIVE_E_PRCI_PLLOUTDIV:
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s->plloutdiv = (uint32_t) val64;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
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__func__, (int)addr, (int)val64);
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}
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}
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static const MemoryRegionOps sifive_e_prci_ops = {
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.read = sifive_e_prci_read,
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.write = sifive_e_prci_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
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}
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};
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static void sifive_e_prci_init(Object *obj)
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{
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SiFiveEPRCIState *s = SIFIVE_E_PRCI(obj);
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memory_region_init_io(&s->mmio, obj, &sifive_e_prci_ops, s,
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TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
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s->hfxosccfg = (SIFIVE_E_PRCI_HFXOSCCFG_RDY | SIFIVE_E_PRCI_HFXOSCCFG_EN);
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s->pllcfg = (SIFIVE_E_PRCI_PLLCFG_REFSEL | SIFIVE_E_PRCI_PLLCFG_BYPASS |
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SIFIVE_E_PRCI_PLLCFG_LOCK);
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s->plloutdiv = SIFIVE_E_PRCI_PLLOUTDIV_DIV1;
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}
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static const TypeInfo sifive_e_prci_info = {
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.name = TYPE_SIFIVE_E_PRCI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SiFiveEPRCIState),
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.instance_init = sifive_e_prci_init,
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};
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static void sifive_e_prci_register_types(void)
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{
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type_register_static(&sifive_e_prci_info);
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}
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type_init(sifive_e_prci_register_types)
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/*
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* Create PRCI device.
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*/
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DeviceState *sifive_e_prci_create(hwaddr addr)
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{
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DeviceState *dev = qdev_new(TYPE_SIFIVE_E_PRCI);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
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return dev;
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}
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