FRET-qemu

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Richard Henderson c80a339587 target-arm queue:

* tests/avocado: update firmware for sbsa-ref and use all cores
  * hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdev
  * arm: Fix VCMLA Dd, Dn, Dm[idx]
  * arm: Fix SQDMULH (by element) with Q=0
  * arm: Fix FJCVTZS vs flush-to-zero
  * arm: More conversion of A64 AdvSIMD to decodetree
  * arm: Enable FEAT_Debugv8p8 for -cpu max
  * MAINTAINERS: Update family name for Patrick Leis
  * hw/arm/xilinx_zynq: Add boot-mode property
  * docs/system/arm: Add a doc for zynq board
  * hw/misc: In STM32L4x5 EXTI, correct configurable interrupts
  * tests/qtest: fix minor issues in STM32L4x5 tests
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Merge tag 'pull-target-arm-20240701' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * tests/avocado: update firmware for sbsa-ref and use all cores
 * hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdev
 * arm: Fix VCMLA Dd, Dn, Dm[idx]
 * arm: Fix SQDMULH (by element) with Q=0
 * arm: Fix FJCVTZS vs flush-to-zero
 * arm: More conversion of A64 AdvSIMD to decodetree
 * arm: Enable FEAT_Debugv8p8 for -cpu max
 * MAINTAINERS: Update family name for Patrick Leis
 * hw/arm/xilinx_zynq: Add boot-mode property
 * docs/system/arm: Add a doc for zynq board
 * hw/misc: In STM32L4x5 EXTI, correct configurable interrupts
 * tests/qtest: fix minor issues in STM32L4x5 tests

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# gpg: Signature made Mon 01 Jul 2024 09:06:43 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]

* tag 'pull-target-arm-20240701' of https://git.linaro.org/people/pmaydell/qemu-arm: (29 commits)
  tests/qtest: Ensure STM32L4x5 EXTI state is correct at the end of QTests
  hw/misc: In STM32L4x5 EXTI, correct configurable interrupts
  tests/qtest: Fix STM32L4x5 SYSCFG irq line 15 state assumption
  docs/system/arm: Add a doc for zynq board
  hw/arm/xilinx_zynq: Add boot-mode property
  hw/misc/zynq_slcr: Add boot-mode property
  MAINTAINERS: Update my family name
  target/arm: Enable FEAT_Debugv8p8 for -cpu max
  target/arm: Move initialization of debug ID registers
  target/arm: Fix indentation
  target/arm: Delete dead code from disas_simd_indexed
  target/arm: Convert FCMLA to decodetree
  target/arm: Convert FCADD to decodetree
  target/arm: Add data argument to do_fp3_vector
  target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree
  target/arm: Convert BFMLALB, BFMLALT to decodetree
  target/arm: Convert BFDOT to decodetree
  target/arm: Convert SUDOT, USDOT to decodetree
  target/arm: Convert SDOT, UDOT to decodetree
  target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

2024-07-01 10:41:45 -07:00

acpi

hw/acpi: Implement the SRAT GI affinity structure

2024-03-12 17:56:55 -04:00

adc

…

arm

hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdev

2024-07-01 12:48:55 +01:00

audio

virtio-snd: rewrite invalid tx/rx message handling

2024-04-09 02:31:16 -04:00