 e2e7168a21
			
		
	
	
		e2e7168a21
		
	
	
	
	
		
			
			With larger vector sizes, it turns out oprsz == maxsz, and we only need to represent mismatch for oprsz <= 32. We do, however, need to represent larger oprsz and do so without reducing SIMD_DATA_BITS. Reduce the size of the oprsz field and increase the maxsz field. Steal the oprsz value of 24 to indicate equality with maxsz. Tested-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
		
			
				
	
	
		
			67 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			67 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Generic vector operation descriptor
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|  *
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|  * Copyright (c) 2018 Linaro
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|  *
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|  * This library is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU Lesser General Public
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|  * License as published by the Free Software Foundation; either
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|  * version 2.1 of the License, or (at your option) any later version.
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|  *
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|  * This library is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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|  * Lesser General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU Lesser General Public
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|  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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|  */
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| 
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| #ifndef TCG_TCG_GVEC_DESC_H
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| #define TCG_TCG_GVEC_DESC_H
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| 
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| /*
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|  * This configuration allows MAXSZ to represent 2048 bytes, and
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|  * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32.
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|  *
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|  * Encode this with:
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|  *   0, 1, 3 -> 8, 16, 32
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|  *   2       -> maxsz
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|  *
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|  * This steals the input that would otherwise map to 24 to match maxsz.
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|  */
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| #define SIMD_MAXSZ_SHIFT   0
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| #define SIMD_MAXSZ_BITS    8
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| 
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| #define SIMD_OPRSZ_SHIFT   (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
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| #define SIMD_OPRSZ_BITS    2
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| 
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| #define SIMD_DATA_SHIFT    (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
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| #define SIMD_DATA_BITS     (32 - SIMD_DATA_SHIFT)
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| 
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| /* Create a descriptor from components.  */
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| uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
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| 
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| /* Extract the max vector size from a descriptor.  */
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| static inline intptr_t simd_maxsz(uint32_t desc)
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| {
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|     return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8;
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| }
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| 
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| /* Extract the operation size from a descriptor.  */
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| static inline intptr_t simd_oprsz(uint32_t desc)
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| {
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|     uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS);
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|     intptr_t o = f * 8 + 8;
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|     intptr_t m = simd_maxsz(desc);
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|     return f == 2 ? m : o;
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| }
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| 
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| /* Extract the operation-specific data from a descriptor.  */
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| static inline int32_t simd_data(uint32_t desc)
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| {
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|     return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS);
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| }
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| 
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| #endif
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