ec150c7e09
Back in 2016, we discussed[1] rules for headers, and these were
generally liked:
1. Have a carefully curated header that's included everywhere first. We
got that already thanks to Peter: osdep.h.
2. Headers should normally include everything they need beyond osdep.h.
If exceptions are needed for some reason, they must be documented in
the header. If all that's needed from a header is typedefs, put
those into qemu/typedefs.h instead of including the header.
3. Cyclic inclusion is forbidden.
This patch gets include/ closer to obeying 2.
It's actually extracted from my "[RFC] Baby steps towards saner
headers" series[2], which demonstrates a possible path towards
checking 2 automatically. It passes the RFC test there.
[1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org>
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html
[2] Message-Id: <20190711122827.18970-1-armbru@redhat.com>
https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.html
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190812052359.30071-2-armbru@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
83 lines
2.2 KiB
C
83 lines
2.2 KiB
C
#ifndef SH_INTC_H
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#define SH_INTC_H
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#include "exec/memory.h"
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#include "hw/irq.h"
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typedef unsigned char intc_enum;
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struct intc_vect {
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intc_enum enum_id;
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unsigned short vect;
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};
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#define INTC_VECT(enum_id, vect) { enum_id, vect }
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struct intc_group {
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intc_enum enum_id;
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intc_enum enum_ids[32];
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};
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#define INTC_GROUP(enum_id, ...) { enum_id, { __VA_ARGS__ } }
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struct intc_mask_reg {
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unsigned long set_reg, clr_reg, reg_width;
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intc_enum enum_ids[32];
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unsigned long value;
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};
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struct intc_prio_reg {
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unsigned long set_reg, clr_reg, reg_width, field_width;
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intc_enum enum_ids[16];
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unsigned long value;
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};
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#define _INTC_ARRAY(a) a, ARRAY_SIZE(a)
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struct intc_source {
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unsigned short vect;
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intc_enum next_enum_id;
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int asserted; /* emulates the interrupt signal line from device to intc */
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int enable_count;
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int enable_max;
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int pending; /* emulates the result of signal and masking */
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struct intc_desc *parent;
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};
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struct intc_desc {
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MemoryRegion iomem;
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MemoryRegion *iomem_aliases;
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qemu_irq *irqs;
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struct intc_source *sources;
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int nr_sources;
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struct intc_mask_reg *mask_regs;
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int nr_mask_regs;
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struct intc_prio_reg *prio_regs;
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int nr_prio_regs;
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int pending; /* number of interrupt sources that has pending set */
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};
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int sh_intc_get_pending_vector(struct intc_desc *desc, int imask);
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struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id);
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void sh_intc_toggle_source(struct intc_source *source,
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int enable_adj, int assert_adj);
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void sh_intc_register_sources(struct intc_desc *desc,
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struct intc_vect *vectors,
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int nr_vectors,
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struct intc_group *groups,
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int nr_groups);
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int sh_intc_init(MemoryRegion *sysmem,
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struct intc_desc *desc,
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int nr_sources,
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struct intc_mask_reg *mask_regs,
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int nr_mask_regs,
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struct intc_prio_reg *prio_regs,
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int nr_prio_regs);
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void sh_intc_set_irl(void *opaque, int n, int level);
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#endif /* SH_INTC_H */
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