139 lines
		
	
	
		
			4.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			139 lines
		
	
	
		
			4.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Cortex-A9MPCore internal peripheral emulation.
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|  *
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|  * Copyright (c) 2009 CodeSourcery.
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|  * Copyright (c) 2011 Linaro Limited.
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|  * Written by Paul Brook, Peter Maydell.
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|  *
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|  * This code is licensed under the GPL.
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|  */
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| 
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| #include "hw/sysbus.h"
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| 
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| typedef struct A9MPPrivState {
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|     SysBusDevice busdev;
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|     uint32_t num_cpu;
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|     MemoryRegion container;
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|     DeviceState *mptimer;
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|     DeviceState *wdt;
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|     DeviceState *gic;
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|     DeviceState *scu;
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|     uint32_t num_irq;
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| } A9MPPrivState;
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| 
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| static void a9mp_priv_set_irq(void *opaque, int irq, int level)
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| {
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|     A9MPPrivState *s = (A9MPPrivState *)opaque;
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|     qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
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| }
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| 
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| static int a9mp_priv_init(SysBusDevice *dev)
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| {
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|     A9MPPrivState *s = FROM_SYSBUS(A9MPPrivState, dev);
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|     SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev;
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|     int i;
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| 
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|     s->gic = qdev_create(NULL, "arm_gic");
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|     qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
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|     qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
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|     qdev_init_nofail(s->gic);
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|     gicbusdev = SYS_BUS_DEVICE(s->gic);
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| 
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|     /* Pass through outbound IRQ lines from the GIC */
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|     sysbus_pass_irq(dev, gicbusdev);
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| 
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|     /* Pass through inbound GPIO lines to the GIC */
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|     qdev_init_gpio_in(&s->busdev.qdev, a9mp_priv_set_irq, s->num_irq - 32);
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| 
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|     s->scu = qdev_create(NULL, "a9-scu");
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|     qdev_prop_set_uint32(s->scu, "num-cpu", s->num_cpu);
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|     qdev_init_nofail(s->scu);
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|     scubusdev = SYS_BUS_DEVICE(s->scu);
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| 
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|     s->mptimer = qdev_create(NULL, "arm_mptimer");
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|     qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
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|     qdev_init_nofail(s->mptimer);
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|     timerbusdev = SYS_BUS_DEVICE(s->mptimer);
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| 
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|     s->wdt = qdev_create(NULL, "arm_mptimer");
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|     qdev_prop_set_uint32(s->wdt, "num-cpu", s->num_cpu);
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|     qdev_init_nofail(s->wdt);
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|     wdtbusdev = SYS_BUS_DEVICE(s->wdt);
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| 
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|     /* Memory map (addresses are offsets from PERIPHBASE):
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|      *  0x0000-0x00ff -- Snoop Control Unit
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|      *  0x0100-0x01ff -- GIC CPU interface
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|      *  0x0200-0x02ff -- Global Timer
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|      *  0x0300-0x05ff -- nothing
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|      *  0x0600-0x06ff -- private timers and watchdogs
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|      *  0x0700-0x0fff -- nothing
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|      *  0x1000-0x1fff -- GIC Distributor
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|      *
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|      * We should implement the global timer but don't currently do so.
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|      */
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|     memory_region_init(&s->container, "a9mp-priv-container", 0x2000);
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|     memory_region_add_subregion(&s->container, 0,
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|                                 sysbus_mmio_get_region(scubusdev, 0));
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|     /* GIC CPU interface */
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|     memory_region_add_subregion(&s->container, 0x100,
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|                                 sysbus_mmio_get_region(gicbusdev, 1));
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|     /* Note that the A9 exposes only the "timer/watchdog for this core"
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|      * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
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|      */
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|     memory_region_add_subregion(&s->container, 0x600,
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|                                 sysbus_mmio_get_region(timerbusdev, 0));
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|     memory_region_add_subregion(&s->container, 0x620,
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|                                 sysbus_mmio_get_region(wdtbusdev, 0));
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|     memory_region_add_subregion(&s->container, 0x1000,
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|                                 sysbus_mmio_get_region(gicbusdev, 0));
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| 
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|     sysbus_init_mmio(dev, &s->container);
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| 
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|     /* Wire up the interrupt from each watchdog and timer.
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|      * For each core the timer is PPI 29 and the watchdog PPI 30.
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|      */
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|     for (i = 0; i < s->num_cpu; i++) {
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|         int ppibase = (s->num_irq - 32) + i * 32;
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|         sysbus_connect_irq(timerbusdev, i,
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|                            qdev_get_gpio_in(s->gic, ppibase + 29));
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|         sysbus_connect_irq(wdtbusdev, i,
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|                            qdev_get_gpio_in(s->gic, ppibase + 30));
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|     }
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|     return 0;
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| }
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| 
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| static Property a9mp_priv_properties[] = {
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|     DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
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|     /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
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|      * IRQ lines (with another 32 internal). We default to 64+32, which
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|      * is the number provided by the Cortex-A9MP test chip in the
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|      * Realview PBX-A9 and Versatile Express A9 development boards.
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|      * Other boards may differ and should set this property appropriately.
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|      */
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|     DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96),
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|     DEFINE_PROP_END_OF_LIST(),
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| };
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| 
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| static void a9mp_priv_class_init(ObjectClass *klass, void *data)
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| {
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|     DeviceClass *dc = DEVICE_CLASS(klass);
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|     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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| 
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|     k->init = a9mp_priv_init;
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|     dc->props = a9mp_priv_properties;
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| }
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| 
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| static const TypeInfo a9mp_priv_info = {
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|     .name          = "a9mpcore_priv",
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|     .parent        = TYPE_SYS_BUS_DEVICE,
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|     .instance_size = sizeof(A9MPPrivState),
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|     .class_init    = a9mp_priv_class_init,
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| };
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| 
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| static void a9mp_register_types(void)
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| {
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|     type_register_static(&a9mp_priv_info);
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| }
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| 
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| type_init(a9mp_register_types)
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