alwin.berger/FRET-FreeRTOS
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Compare commits

base: alwin.berger:wcet-demo
Branches Tags
alwin.berger:wcet-demo
alwin.berger:eval-24-11-11
alwin.berger:eval-24-10-30
alwin.berger:submitted
alwin.berger:exp02
..
compare: alwin.berger:exp02
Branches Tags
alwin.berger:wcet-demo
alwin.berger:eval-24-11-11
alwin.berger:eval-24-10-30
alwin.berger:submitted
alwin.berger:exp02

No commits in common. "wcet-demo" and "exp02" have entirely different histories.
wcet-demo ... exp02

10487 changed files with 6717896 additions and 8158 deletions
Show Stats Expand all files Collapse all files

707
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/AT91R40008.h Normal file
View File

@ -0,0 +1,707 @@
// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// The software is delivered "AS IS" without warranty or condition of any
// kind, either express, implied or statutory. This includes without
// limitation any warranty or condition with respect to merchantability or
// fitness for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ----------------------------------------------------------------------------
// File Name : AT91R40008.h
// Object : AT91R40008 definitions
// Generated : AT91 SW Application Group 02/19/2003 (11:13:31)
//
// CVS Reference : /AT91R40008.pl/1.3/Tue Nov 12 16:01:52 2002//
// CVS Reference : /AIC_1246F.pl/1.4/Mon Nov 04 17:51:00 2002//
// CVS Reference : /WD_1241B.pl/1.1/Mon Nov 04 17:51:00 2002//
// CVS Reference : /PS_x40.pl/1.2/Tue Nov 12 16:01:52 2002//
// CVS Reference : /PIO_1321C.pl/1.5/Tue Oct 29 15:50:24 2002//
// CVS Reference : /TC_1243B.pl/1.4/Tue Nov 05 12:43:10 2002//
// CVS Reference : /PDC_1363D.pl/1.3/Wed Oct 23 14:49:48 2002//
// CVS Reference : /US_1242E.pl/1.5/Thu Nov 21 13:37:56 2002//
// CVS Reference : /SF_x40.pl/1.1/Tue Nov 12 13:27:20 2002//
// CVS Reference : /EBI_x40.pl/1.5/Wed Feb 19 09:25:22 2003//
// ----------------------------------------------------------------------------
#ifndef AT91R40008_H
#define AT91R40008_H
/* AT91 Register type */
typedef volatile unsigned int AT91_REG; // Hardware register definition
typedef volatile unsigned int at91_reg;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode egister
AT91_REG AIC_SVR[32]; // Source Vector egister
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command egister
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
} AT91S_AIC, *AT91PS_AIC;
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Interface
// *****************************************************************************
typedef struct _AT91S_WD {
AT91_REG WD_OMR; // Overflow Mode Register
AT91_REG WD_CMR; // Clock Mode Register
AT91_REG WD_CR; // Control Register
AT91_REG WD_SR; // Status Register
} AT91S_WD, *AT91PS_WD;
// -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register --------
#define AT91C_WD_WDEN ((unsigned int) 0x1 << 0) // (WD) Watchdog Enable
#define AT91C_WD_RSTEN ((unsigned int) 0x1 << 1) // (WD) Reset Enable
#define AT91C_WD_IRQEN ((unsigned int) 0x1 << 2) // (WD) Interrupt Enable
#define AT91C_WD_EXTEN ((unsigned int) 0x1 << 3) // (WD) External Signal Enable
#define AT91C_WD_OKEY ((unsigned int) 0xFFF << 4) // (WD) Watchdog Enable
// -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register --------
#define AT91C_WD_WDCLKS ((unsigned int) 0x3 << 0) // (WD) Clock Selection
#define AT91C_WD_WDCLKS_MCK32 ((unsigned int) 0x0) // (WD) Master Clock divided by 32
#define AT91C_WD_WDCLKS_MCK128 ((unsigned int) 0x1) // (WD) Master Clock divided by 128
#define AT91C_WD_WDCLKS_MCK1024 ((unsigned int) 0x2) // (WD) Master Clock divided by 1024
#define AT91C_WD_WDCLKS_MCK4096 ((unsigned int) 0x3) // (WD) Master Clock divided by 4096
#define AT91C_WD_HPCV ((unsigned int) 0xF << 2) // (WD) High Pre-load Counter Value
#define AT91C_WD_CKEY ((unsigned int) 0x1FF << 7) // (WD) Clock Access Key
// -------- WD_CR : (WD Offset: 0x8) Control Register --------
#define AT91C_WD_RSTKEY ((unsigned int) 0xFFFF << 0) // (WD) Restart Key
// -------- WD_SR : (WD Offset: 0xc) Status Register --------
#define AT91C_WD_WDOVF ((unsigned int) 0x1 << 0) // (WD) Watchdog Overflow
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Saving Controler
// *****************************************************************************
typedef struct _AT91S_PS {
AT91_REG PS_CR; // Control Register
AT91_REG PS_PCER; // Peripheral Clock Enable Register
AT91_REG PS_PCDR; // Peripheral Clock Disable Register
AT91_REG PS_PCSR; // Peripheral Clock Status Register
} AT91S_PS, *AT91PS_PS;
// -------- PS_PCER : (PS Offset: 0x4) Peripheral Clock Enable Register --------
#define AT91C_PS_US0 ((unsigned int) 0x1 << 2) // (PS) Usart 0 Clock
#define AT91C_PS_US1 ((unsigned int) 0x1 << 3) // (PS) Usart 1 Clock
#define AT91C_PS_TC0 ((unsigned int) 0x1 << 4) // (PS) Timer Counter 0 Clock
#define AT91C_PS_TC1 ((unsigned int) 0x1 << 5) // (PS) Timer Counter 1 Clock
#define AT91C_PS_TC2 ((unsigned int) 0x1 << 6) // (PS) Timer Counter 2 Clock
#define AT91C_PS_PIO ((unsigned int) 0x1 << 8) // (PS) PIO Clock
// -------- PS_PCDR : (PS Offset: 0x8) Peripheral Clock Disable Register --------
// -------- PS_PCSR : (PS Offset: 0xc) Peripheral Clock Satus Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; // PIO Enable Register
AT91_REG PIO_PDR; // PIO Disable Register
AT91_REG PIO_PSR; // PIO Status Register
AT91_REG Reserved0[1]; //
AT91_REG PIO_OER; // Output Enable Register
AT91_REG PIO_ODR; // Output Disable Registerr
AT91_REG PIO_OSR; // Output Status Register
AT91_REG Reserved1[1]; //
AT91_REG PIO_IFER; // Input Filter Enable Register
AT91_REG PIO_IFDR; // Input Filter Disable Register
AT91_REG PIO_IFSR; // Input Filter Status Register
AT91_REG Reserved2[1]; //
AT91_REG PIO_SODR; // Set Output Data Register
AT91_REG PIO_CODR; // Clear Output Data Register
AT91_REG PIO_ODSR; // Output Data Status Register
AT91_REG PIO_PDSR; // Pin Data Status Register
AT91_REG PIO_IER; // Interrupt Enable Register
AT91_REG PIO_IDR; // Interrupt Disable Register
AT91_REG PIO_IMR; // Interrupt Mask Register
AT91_REG PIO_ISR; // Interrupt Status Register
AT91_REG PIO_MDER; // Multi-driver Enable Register
AT91_REG PIO_MDDR; // Multi-driver Disable Register
AT91_REG PIO_MDSR; // Multi-driver Status Register
} AT91S_PIO, *AT91PS_PIO;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
typedef struct _AT91S_TC {
AT91_REG TC_CCR; // Channel Control Register
AT91_REG TC_CMR; // Channel Mode Register
AT91_REG Reserved0[2]; //
AT91_REG TC_CV; // Counter Value
AT91_REG TC_RA; // Register A
AT91_REG TC_RB; // Register B
AT91_REG TC_RC; // Register C
AT91_REG TC_SR; // Status Register
AT91_REG TC_IER; // Interrupt Enable Register
AT91_REG TC_IDR; // Interrupt Disable Register
AT91_REG TC_IMR; // Interrupt Mask Register
} AT91S_TC, *AT91PS_TC;
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x1 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x2 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger
#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Interface
// *****************************************************************************
typedef struct _AT91S_TCB {
AT91S_TC TCB_TC0; // TC Channel 0
AT91_REG Reserved0[4]; //
AT91S_TC TCB_TC1; // TC Channel 1
AT91_REG Reserved1[4]; //
AT91S_TC TCB_TC2; // TC Channel 2
AT91_REG Reserved2[4]; //
AT91_REG TCB_BCR; // TC Block Control Register
AT91_REG TCB_BMR; // TC Block Mode Register
} AT91S_TCB, *AT91PS_TCB;
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection
#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection
#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection
#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral Data Controller
// *****************************************************************************
typedef struct _AT91S_PDC {
AT91_REG PDC_RPR; // Receive Pointer Register
AT91_REG PDC_RCR; // Receive Counter Register
AT91_REG PDC_TPR; // Transmit Pointer Register
AT91_REG PDC_TCR; // Transmit Counter Register
} AT91S_PDC, *AT91PS_PDC;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
typedef struct _AT91S_USART {
AT91_REG US_CR; // Control Register
AT91_REG US_MR; // Mode Register
AT91_REG US_IER; // Interrupt Enable Register
AT91_REG US_IDR; // Interrupt Disable Register
AT91_REG US_IMR; // Interrupt Mask Register
AT91_REG US_CSR; // Channel Status Register
AT91_REG US_RHR; // Receiver Holding Register
AT91_REG US_THR; // Transmitter Holding Register
AT91_REG US_BRGR; // Baud Rate Generator Register
AT91_REG US_RTOR; // Receiver Time-out Register
AT91_REG US_TTGR; // Transmitter Time-guard Register
AT91_REG Reserved0[1]; //
AT91_REG US_RPR; // Receive Pointer Register
AT91_REG US_RCR; // Receive Counter Register
AT91_REG US_TPR; // Transmit Pointer Register
AT91_REG US_TCR; // Transmit Counter Register
} AT91S_USART, *AT91PS_USART;
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (USART) Reset Receiver
#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (USART) Reset Transmitter
#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (USART) Receiver Enable
#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (USART) Receiver Disable
#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (USART) Transmitter Enable
#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (USART) Transmitter Disable
#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits
#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (USART) Parity type
#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (USART) Even Parity
#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (USART) Odd Parity
#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (USART) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (USART) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (USART) No Parity
#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (USART) Multi-drop mode
#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (USART) Channel Mode
#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin.
#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (USART) RXRDY Interrupt
#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (USART) TXRDY Interrupt
#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (USART) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (USART) End of Transmit Interrupt
#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (USART) Overrun Interrupt
#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (USART) Framing Error Interrupt
#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (USART) Parity Error Interrupt
#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (USART) TXEMPTY Interrupt
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Special Function Interface
// *****************************************************************************
typedef struct _AT91S_SF {
AT91_REG SF_CIDR; // Chip ID Register
AT91_REG SF_EXID; // Chip ID Extension Register
AT91_REG SF_RSR; // Reset Status Register
AT91_REG SF_MMR; // Memory Mode Register
AT91_REG Reserved0[2]; //
AT91_REG SF_PMR; // Protect Mode Register
} AT91S_SF, *AT91PS_SF;
// -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register --------
#define AT91C_SF_VERSION ((unsigned int) 0x1F << 0) // (SF) Version of the chip
#define AT91C_SF_BIT5 ((unsigned int) 0x1 << 5) // (SF) Hardwired at 0
#define AT91C_SF_BIT6 ((unsigned int) 0x1 << 6) // (SF) Hardwired at 1
#define AT91C_SF_BIT7 ((unsigned int) 0x1 << 7) // (SF) Hardwired at 0
#define AT91C_SF_NVPSIZ ((unsigned int) 0xF << 8) // (SF) Nonvolatile Program Memory Size
#define AT91C_SF_NVPSIZ_NONE ((unsigned int) 0x0 << 8) // (SF) None
#define AT91C_SF_NVPSIZ_32K ((unsigned int) 0x3 << 8) // (SF) 32K Bytes
#define AT91C_SF_NVPSIZ_64K ((unsigned int) 0x5 << 8) // (SF) 64K Bytes
#define AT91C_SF_NVPSIZ_128K ((unsigned int) 0x7 << 8) // (SF) 128K Bytes
#define AT91C_SF_NVPSIZ_256K ((unsigned int) 0x11 << 8) // (SF) 256K Bytes
#define AT91C_SF_NVDSIZ ((unsigned int) 0xF << 12) // (SF) Nonvolatile Data Memory Size
#define AT91C_SF_NVDSIZ_NONE ((unsigned int) 0x0 << 12) // (SF) None
#define AT91C_SF_VDSIZ ((unsigned int) 0xF << 16) // (SF) Volatile Data Memory Size
#define AT91C_SF_VDSIZ_NONE ((unsigned int) 0x0 << 16) // (SF) None
#define AT91C_SF_VDSIZ_1K ((unsigned int) 0x3 << 16) // (SF) 1K Bytes
#define AT91C_SF_VDSIZ_2K ((unsigned int) 0x5 << 16) // (SF) 2K Bytes
#define AT91C_SF_VDSIZ_4K ((unsigned int) 0x7 << 16) // (SF) 4K Bytes
#define AT91C_SF_VDSIZ_8K ((unsigned int) 0x11 << 16) // (SF) 8K Bytes
#define AT91C_SF_ARCH ((unsigned int) 0xFF << 20) // (SF) Chip Architecture
#define AT91C_SF_ARCH_AT91x40 ((unsigned int) 0x28 << 20) // (SF) AT91x40yyy
#define AT91C_SF_ARCH_AT91x55 ((unsigned int) 0x37 << 20) // (SF) AT91x55yyy
#define AT91C_SF_ARCH_AT91x63 ((unsigned int) 0x3F << 20) // (SF) AT91x63yyy
#define AT91C_SF_NVPTYP ((unsigned int) 0x7 << 28) // (SF) Nonvolatile Program Memory Type
#define AT91C_SF_NVPTYP_NVPTYP_M ((unsigned int) 0x1 << 28) // (SF) 'M' Series or 'F' Series
#define AT91C_SF_NVPTYP_NVPTYP_R ((unsigned int) 0x4 << 28) // (SF) 'R' Series
#define AT91C_SF_EXT ((unsigned int) 0x1 << 31) // (SF) Extension Flag
// -------- SF_RSR : (SF Offset: 0x8) Reset Status Information --------
#define AT91C_SF_RESET ((unsigned int) 0xFF << 0) // (SF) Cause of Reset
#define AT91C_SF_RESET_WD ((unsigned int) 0x35) // (SF) Internal Watchdog
#define AT91C_SF_RESET_EXT ((unsigned int) 0x6C) // (SF) External Pin
// -------- SF_MMR : (SF Offset: 0xc) Memory Mode Register --------
#define AT91C_SF_RAMWU ((unsigned int) 0x1 << 0) // (SF) Internal Extended RAM Write Detection
// -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register --------
#define AT91C_SF_AIC ((unsigned int) 0x1 << 5) // (SF) AIC Protect Mode Enable
#define AT91C_SF_PMRKEY ((unsigned int) 0xFFFF << 16) // (SF) Protect Mode Register Key
// *****************************************************************************
// SOFTWARE API DEFINITION FOR External Bus Interface
// *****************************************************************************
typedef struct _AT91S_EBI {
AT91_REG EBI_CSR[8]; // Chip-select Register
AT91_REG EBI_RCR; // Remap Control Register
AT91_REG EBI_MCR; // Memory Control Register
} AT91S_EBI, *AT91PS_EBI;
// -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register --------
#define AT91C_EBI_DBW ((unsigned int) 0x3 << 0) // (EBI) Data Bus Width
#define AT91C_EBI_DBW_16 ((unsigned int) 0x1) // (EBI) 16-bit data bus width
#define AT91C_EBI_DBW_8 ((unsigned int) 0x2) // (EBI) 8-bit data bus width
#define AT91C_EBI_NWS ((unsigned int) 0x7 << 2) // (EBI) Number of wait states
#define AT91C_EBI_NWS_1 ((unsigned int) 0x0 << 2) // (EBI) 1 wait state
#define AT91C_EBI_NWS_2 ((unsigned int) 0x1 << 2) // (EBI) 2 wait state
#define AT91C_EBI_NWS_3 ((unsigned int) 0x2 << 2) // (EBI) 3 wait state
#define AT91C_EBI_NWS_4 ((unsigned int) 0x3 << 2) // (EBI) 4 wait state
#define AT91C_EBI_NWS_5 ((unsigned int) 0x4 << 2) // (EBI) 5 wait state
#define AT91C_EBI_NWS_6 ((unsigned int) 0x5 << 2) // (EBI) 6 wait state
#define AT91C_EBI_NWS_7 ((unsigned int) 0x6 << 2) // (EBI) 7 wait state
#define AT91C_EBI_NWS_8 ((unsigned int) 0x7 << 2) // (EBI) 8 wait state
#define AT91C_EBI_WSE ((unsigned int) 0x1 << 5) // (EBI) Wait State Enable
#define AT91C_EBI_PAGES ((unsigned int) 0x3 << 7) // (EBI) Pages Size
#define AT91C_EBI_PAGES_1M ((unsigned int) 0x0 << 7) // (EBI) 1M Byte
#define AT91C_EBI_PAGES_4M ((unsigned int) 0x1 << 7) // (EBI) 4M Byte
#define AT91C_EBI_PAGES_16M ((unsigned int) 0x2 << 7) // (EBI) 16M Byte
#define AT91C_EBI_PAGES_64M ((unsigned int) 0x3 << 7) // (EBI) 64M Byte
#define AT91C_EBI_TDF ((unsigned int) 0x7 << 9) // (EBI) Data Float Output Time
#define AT91C_EBI_TDF_0 ((unsigned int) 0x0 << 9) // (EBI) 1 TDF
#define AT91C_EBI_TDF_1 ((unsigned int) 0x1 << 9) // (EBI) 2 TDF
#define AT91C_EBI_TDF_2 ((unsigned int) 0x2 << 9) // (EBI) 3 TDF
#define AT91C_EBI_TDF_3 ((unsigned int) 0x3 << 9) // (EBI) 4 TDF
#define AT91C_EBI_TDF_4 ((unsigned int) 0x4 << 9) // (EBI) 5 TDF
#define AT91C_EBI_TDF_5 ((unsigned int) 0x5 << 9) // (EBI) 6 TDF
#define AT91C_EBI_TDF_6 ((unsigned int) 0x6 << 9) // (EBI) 7 TDF
#define AT91C_EBI_TDF_7 ((unsigned int) 0x7 << 9) // (EBI) 8 TDF
#define AT91C_EBI_BAT ((unsigned int) 0x1 << 12) // (EBI) Byte Access Type
#define AT91C_EBI_CSEN ((unsigned int) 0x1 << 13) // (EBI) Chip Select Enable
#define AT91C_EBI_BA ((unsigned int) 0xFFF << 20) // (EBI) Base Address
// -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register --------
#define AT91C_EBI_RCB ((unsigned int) 0x1 << 0) // (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices.
// -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register --------
#define AT91C_EBI_ALE ((unsigned int) 0x7 << 0) // (EBI) Address Line Enable
#define AT91C_EBI_ALE_16M ((unsigned int) 0x0) // (EBI) Valid Address Bits = A20, A21, A22, A23 Max Addressable Space = 16M Bytes Valid Chip Select=None
#define AT91C_EBI_ALE_8M ((unsigned int) 0x4) // (EBI) Valid Address Bits = A20, A21, A22 Max Addressable Space = 8M Bytes Valid Chip Select = CS4
#define AT91C_EBI_ALE_4M ((unsigned int) 0x5) // (EBI) Valid Address Bits = A20, A21 Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5
#define AT91C_EBI_ALE_2M ((unsigned int) 0x6) // (EBI) Valid Address Bits = A20 Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6
#define AT91C_EBI_ALE_1M ((unsigned int) 0x7) // (EBI) Valid Address Bits = None Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7
#define AT91C_EBI_DRP ((unsigned int) 0x1 << 4) // (EBI)
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91R40008
// *****************************************************************************
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector egister
#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode egister
#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command egister
// ========== Register definition for WD peripheral ==========
#define AT91C_WD_SR ((AT91_REG *) 0xFFFF800C) // (WD) Status Register
#define AT91C_WD_CMR ((AT91_REG *) 0xFFFF8004) // (WD) Clock Mode Register
#define AT91C_WD_CR ((AT91_REG *) 0xFFFF8008) // (WD) Control Register
#define AT91C_WD_OMR ((AT91_REG *) 0xFFFF8000) // (WD) Overflow Mode Register
// ========== Register definition for PS peripheral ==========
#define AT91C_PS_PCDR ((AT91_REG *) 0xFFFF4008) // (PS) Peripheral Clock Disable Register
#define AT91C_PS_CR ((AT91_REG *) 0xFFFF4000) // (PS) Control Register
#define AT91C_PS_PCSR ((AT91_REG *) 0xFFFF400C) // (PS) Peripheral Clock Status Register
#define AT91C_PS_PCER ((AT91_REG *) 0xFFFF4004) // (PS) Peripheral Clock Enable Register
// ========== Register definition for PIO peripheral ==========
#define AT91C_PIO_MDSR ((AT91_REG *) 0xFFFF0058) // (PIO) Multi-driver Status Register
#define AT91C_PIO_IFSR ((AT91_REG *) 0xFFFF0028) // (PIO) Input Filter Status Register
#define AT91C_PIO_IFER ((AT91_REG *) 0xFFFF0020) // (PIO) Input Filter Enable Register
#define AT91C_PIO_OSR ((AT91_REG *) 0xFFFF0018) // (PIO) Output Status Register
#define AT91C_PIO_OER ((AT91_REG *) 0xFFFF0010) // (PIO) Output Enable Register
#define AT91C_PIO_PSR ((AT91_REG *) 0xFFFF0008) // (PIO) PIO Status Register
#define AT91C_PIO_PDSR ((AT91_REG *) 0xFFFF003C) // (PIO) Pin Data Status Register
#define AT91C_PIO_CODR ((AT91_REG *) 0xFFFF0034) // (PIO) Clear Output Data Register
#define AT91C_PIO_IFDR ((AT91_REG *) 0xFFFF0024) // (PIO) Input Filter Disable Register
#define AT91C_PIO_MDER ((AT91_REG *) 0xFFFF0050) // (PIO) Multi-driver Enable Register
#define AT91C_PIO_IMR ((AT91_REG *) 0xFFFF0048) // (PIO) Interrupt Mask Register
#define AT91C_PIO_IER ((AT91_REG *) 0xFFFF0040) // (PIO) Interrupt Enable Register
#define AT91C_PIO_ODSR ((AT91_REG *) 0xFFFF0038) // (PIO) Output Data Status Register
#define AT91C_PIO_SODR ((AT91_REG *) 0xFFFF0030) // (PIO) Set Output Data Register
#define AT91C_PIO_PER ((AT91_REG *) 0xFFFF0000) // (PIO) PIO Enable Register
#define AT91C_PIO_MDDR ((AT91_REG *) 0xFFFF0054) // (PIO) Multi-driver Disable Register
#define AT91C_PIO_ISR ((AT91_REG *) 0xFFFF004C) // (PIO) Interrupt Status Register
#define AT91C_PIO_IDR ((AT91_REG *) 0xFFFF0044) // (PIO) Interrupt Disable Register
#define AT91C_PIO_PDR ((AT91_REG *) 0xFFFF0004) // (PIO) PIO Disable Register
#define AT91C_PIO_ODR ((AT91_REG *) 0xFFFF0014) // (PIO) Output Disable Registerr
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFE00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_SR ((AT91_REG *) 0xFFFE00A0) // (TC2) Status Register
#define AT91C_TC2_RB ((AT91_REG *) 0xFFFE0098) // (TC2) Register B
#define AT91C_TC2_CV ((AT91_REG *) 0xFFFE0090) // (TC2) Counter Value
#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFE0080) // (TC2) Channel Control Register
#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFE00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_IER ((AT91_REG *) 0xFFFE00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_RC ((AT91_REG *) 0xFFFE009C) // (TC2) Register C
#define AT91C_TC2_RA ((AT91_REG *) 0xFFFE0094) // (TC2) Register A
#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFE0084) // (TC2) Channel Mode Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFE0068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_SR ((AT91_REG *) 0xFFFE0060) // (TC1) Status Register
#define AT91C_TC1_RB ((AT91_REG *) 0xFFFE0058) // (TC1) Register B
#define AT91C_TC1_CV ((AT91_REG *) 0xFFFE0050) // (TC1) Counter Value
#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFE0040) // (TC1) Channel Control Register
#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFE006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_IER ((AT91_REG *) 0xFFFE0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_RC ((AT91_REG *) 0xFFFE005C) // (TC1) Register C
#define AT91C_TC1_RA ((AT91_REG *) 0xFFFE0054) // (TC1) Register A
#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFE0044) // (TC1) Channel Mode Register
// ========== Register definition for TC0 peripheral ==========
#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFE0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_SR ((AT91_REG *) 0xFFFE0020) // (TC0) Status Register
#define AT91C_TC0_RB ((AT91_REG *) 0xFFFE0018) // (TC0) Register B
#define AT91C_TC0_CV ((AT91_REG *) 0xFFFE0010) // (TC0) Counter Value
#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFE0000) // (TC0) Channel Control Register
#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFE002C) // (TC0) Interrupt Mask Register
#define AT91C_TC0_IER ((AT91_REG *) 0xFFFE0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RC ((AT91_REG *) 0xFFFE001C) // (TC0) Register C
#define AT91C_TC0_RA ((AT91_REG *) 0xFFFE0014) // (TC0) Register A
#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFE0004) // (TC0) Channel Mode Register
// ========== Register definition for TCB0 peripheral ==========
#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFE00C0) // (TCB0) TC Block Control Register
#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFE00C4) // (TCB0) TC Block Mode Register
// ========== Register definition for PDC_US1 peripheral ==========
#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4038) // (PDC_US1) Transmit Pointer Register
#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4030) // (PDC_US1) Receive Pointer Register
#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC403C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4034) // (PDC_US1) Receive Counter Register
// ========== Register definition for US1 peripheral ==========
#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFCC024) // (US1) Receiver Time-out Register
#define AT91C_US1_THR ((AT91_REG *) 0xFFFCC01C) // (US1) Transmitter Holding Register
#define AT91C_US1_CSR ((AT91_REG *) 0xFFFCC014) // (US1) Channel Status Register
#define AT91C_US1_IDR ((AT91_REG *) 0xFFFCC00C) // (US1) Interrupt Disable Register
#define AT91C_US1_MR ((AT91_REG *) 0xFFFCC004) // (US1) Mode Register
#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFCC028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFCC020) // (US1) Baud Rate Generator Register
#define AT91C_US1_RHR ((AT91_REG *) 0xFFFCC018) // (US1) Receiver Holding Register
#define AT91C_US1_IMR ((AT91_REG *) 0xFFFCC010) // (US1) Interrupt Mask Register
#define AT91C_US1_IER ((AT91_REG *) 0xFFFCC008) // (US1) Interrupt Enable Register
#define AT91C_US1_CR ((AT91_REG *) 0xFFFCC000) // (US1) Control Register
// ========== Register definition for PDC_US0 peripheral ==========
#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0038) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0030) // (PDC_US0) Receive Pointer Register
#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC003C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0034) // (PDC_US0) Receive Counter Register
// ========== Register definition for US0 peripheral ==========
#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFD0024) // (US0) Receiver Time-out Register
#define AT91C_US0_THR ((AT91_REG *) 0xFFFD001C) // (US0) Transmitter Holding Register
#define AT91C_US0_CSR ((AT91_REG *) 0xFFFD0014) // (US0) Channel Status Register
#define AT91C_US0_IDR ((AT91_REG *) 0xFFFD000C) // (US0) Interrupt Disable Register
#define AT91C_US0_MR ((AT91_REG *) 0xFFFD0004) // (US0) Mode Register
#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFD0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFD0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_RHR ((AT91_REG *) 0xFFFD0018) // (US0) Receiver Holding Register
#define AT91C_US0_IMR ((AT91_REG *) 0xFFFD0010) // (US0) Interrupt Mask Register
#define AT91C_US0_IER ((AT91_REG *) 0xFFFD0008) // (US0) Interrupt Enable Register
#define AT91C_US0_CR ((AT91_REG *) 0xFFFD0000) // (US0) Control Register
// ========== Register definition for SF peripheral ==========
#define AT91C_SF_PMR ((AT91_REG *) 0xFFF00018) // (SF) Protect Mode Register
#define AT91C_SF_RSR ((AT91_REG *) 0xFFF00008) // (SF) Reset Status Register
#define AT91C_SF_CIDR ((AT91_REG *) 0xFFF00000) // (SF) Chip ID Register
#define AT91C_SF_MMR ((AT91_REG *) 0xFFF0000C) // (SF) Memory Mode Register
#define AT91C_SF_EXID ((AT91_REG *) 0xFFF00004) // (SF) Chip ID Extension Register
// ========== Register definition for EBI peripheral ==========
#define AT91C_EBI_RCR ((AT91_REG *) 0xFFE00020) // (EBI) Remap Control Register
#define AT91C_EBI_CSR ((AT91_REG *) 0xFFE00000) // (EBI) Chip-select Register
#define AT91C_EBI_MCR ((AT91_REG *) 0xFFE00024) // (EBI) Memory Control Register
// *****************************************************************************
// PIO DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_PIO_P0 ((unsigned int) 1 << 0) // Pin Controlled by P0
#define AT91C_P0_TCLK0 ((unsigned int) AT91C_PIO_P0) // Timer 0 Clock signal
#define AT91C_PIO_P1 ((unsigned int) 1 << 1) // Pin Controlled by P1
#define AT91C_P1_TIOA0 ((unsigned int) AT91C_PIO_P1) // Timer 0 Signal A
#define AT91C_PIO_P10 ((unsigned int) 1 << 10) // Pin Controlled by P10
#define AT91C_P10_IRQ1 ((unsigned int) AT91C_PIO_P10) // External Interrupt 1
#define AT91C_PIO_P11 ((unsigned int) 1 << 11) // Pin Controlled by P11
#define AT91C_P11_IRQ2 ((unsigned int) AT91C_PIO_P11) // External Interrupt 2
#define AT91C_PIO_P12 ((unsigned int) 1 << 12) // Pin Controlled by P12
#define AT91C_P12_FIQ ((unsigned int) AT91C_PIO_P12) // Fast External Interrupt
#define AT91C_PIO_P13 ((unsigned int) 1 << 13) // Pin Controlled by P13
#define AT91C_P13_SCK0 ((unsigned int) AT91C_PIO_P13) // USART 0 Serial Clock
#define AT91C_PIO_P14 ((unsigned int) 1 << 14) // Pin Controlled by P14
#define AT91C_P14_TXD0 ((unsigned int) AT91C_PIO_P14) // USART 0 Transmit Data
#define AT91C_PIO_P15 ((unsigned int) 1 << 15) // Pin Controlled by P15
#define AT91C_P15_RXD0 ((unsigned int) AT91C_PIO_P15) // USART 0 Receive Data
#define AT91C_PIO_P16 ((unsigned int) 1 << 16) // Pin Controlled by P16
#define AT91C_PIO_P17 ((unsigned int) 1 << 17) // Pin Controlled by P17
#define AT91C_PIO_P18 ((unsigned int) 1 << 18) // Pin Controlled by P18
#define AT91C_PIO_P19 ((unsigned int) 1 << 19) // Pin Controlled by P19
#define AT91C_PIO_P2 ((unsigned int) 1 << 2) // Pin Controlled by P2
#define AT91C_P2_TIOB0 ((unsigned int) AT91C_PIO_P2) // Timer 0 Signal B
#define AT91C_PIO_P20 ((unsigned int) 1 << 20) // Pin Controlled by P20
#define AT91C_P20_SCK1 ((unsigned int) AT91C_PIO_P20) // USART 1 Serial Clock
#define AT91C_PIO_P21 ((unsigned int) 1 << 21) // Pin Controlled by P21
#define AT91C_P21_TXD1 ((unsigned int) AT91C_PIO_P21) // USART 1 Transmit Data
#define AT91C_P21_NTRI ((unsigned int) AT91C_PIO_P21) // Tri-state Mode
#define AT91C_PIO_P22 ((unsigned int) 1 << 22) // Pin Controlled by P22
#define AT91C_P22_RXD1 ((unsigned int) AT91C_PIO_P22) // USART 1 Receive Data
#define AT91C_PIO_P23 ((unsigned int) 1 << 23) // Pin Controlled by P23
#define AT91C_PIO_P24 ((unsigned int) 1 << 24) // Pin Controlled by P24
#define AT91C_P24_BMS ((unsigned int) AT91C_PIO_P24) // Boot Mode Select
#define AT91C_PIO_P25 ((unsigned int) 1 << 25) // Pin Controlled by P25
#define AT91C_P25_MCKO ((unsigned int) AT91C_PIO_P25) // Master Clock Out
#define AT91C_PIO_P26 ((unsigned int) 1 << 26) // Pin Controlled by P26
#define AT91C_P26_NCS2 ((unsigned int) AT91C_PIO_P26) // Chip Select 2
#define AT91C_PIO_P27 ((unsigned int) 1 << 27) // Pin Controlled by P27
#define AT91C_P27_NCS3 ((unsigned int) AT91C_PIO_P27) // Chip Select 3
#define AT91C_PIO_P28 ((unsigned int) 1 << 28) // Pin Controlled by P28
#define AT91C_P28_A20 ((unsigned int) AT91C_PIO_P28) // Address line A20
#define AT91C_P28_NCS7 ((unsigned int) AT91C_PIO_P28) // Chip Select 7
#define AT91C_PIO_P29 ((unsigned int) 1 << 29) // Pin Controlled by P29
#define AT91C_P29_A21 ((unsigned int) AT91C_PIO_P29) // Address line A21
#define AT91C_P29_NCS6 ((unsigned int) AT91C_PIO_P29) // Chip Select 6
#define AT91C_PIO_P3 ((unsigned int) 1 << 3) // Pin Controlled by P3
#define AT91C_P3_TCLK1 ((unsigned int) AT91C_PIO_P3) // Timer 1 Clock signal
#define AT91C_PIO_P30 ((unsigned int) 1 << 30) // Pin Controlled by P30
#define AT91C_P30_A22 ((unsigned int) AT91C_PIO_P30) // Address line A22
#define AT91C_P30_NCS5 ((unsigned int) AT91C_PIO_P30) // Chip Select 5
#define AT91C_PIO_P31 ((unsigned int) 1 << 31) // Pin Controlled by P31
#define AT91C_P31_A23 ((unsigned int) AT91C_PIO_P31) // Address line A23
#define AT91C_P31_NCS4 ((unsigned int) AT91C_PIO_P31) // Chip Select 4
#define AT91C_PIO_P4 ((unsigned int) 1 << 4) // Pin Controlled by P4
#define AT91C_P4_TIOA1 ((unsigned int) AT91C_PIO_P4) // Timer 1 Signal A
#define AT91C_PIO_P5 ((unsigned int) 1 << 5) // Pin Controlled by P5
#define AT91C_P5_TIOB1 ((unsigned int) AT91C_PIO_P5) // Timer 1 Signal B
#define AT91C_PIO_P6 ((unsigned int) 1 << 6) // Pin Controlled by P6
#define AT91C_P6_TCLK2 ((unsigned int) AT91C_PIO_P6) // Timer 2 Clock signal
#define AT91C_PIO_P7 ((unsigned int) 1 << 7) // Pin Controlled by P7
#define AT91C_P7_TIOA2 ((unsigned int) AT91C_PIO_P7) // Timer 2 Signal A
#define AT91C_PIO_P8 ((unsigned int) 1 << 8) // Pin Controlled by P8
#define AT91C_P8_TIOB2 ((unsigned int) AT91C_PIO_P8) // Timer 2 Signal B
#define AT91C_PIO_P9 ((unsigned int) 1 << 9) // Pin Controlled by P9
#define AT91C_P9_IRQ0 ((unsigned int) AT91C_PIO_P9) // External Interrupt 0
// *****************************************************************************
// PERIPHERAL ID DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS ((unsigned int) 1) // SWI
#define AT91C_ID_US0 ((unsigned int) 2) // USART 0
#define AT91C_ID_US1 ((unsigned int) 3) // USART 1
#define AT91C_ID_TC0 ((unsigned int) 4) // Timer Counter 0
#define AT91C_ID_TC1 ((unsigned int) 5) // Timer Counter 1
#define AT91C_ID_TC2 ((unsigned int) 6) // Timer Counter 2
#define AT91C_ID_WD ((unsigned int) 7) // Watchdog Timer
#define AT91C_ID_PIO ((unsigned int) 8) // Parallel IO Controller
#define AT91C_ID_IRQ0 ((unsigned int) 16) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1 ((unsigned int) 17) // Advanced Interrupt Controller (IRQ1)
#define AT91C_ID_IRQ2 ((unsigned int) 18) // Advanced Interrupt Controller (IRQ2)
// *****************************************************************************
// BASE ADDRESS DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_WD ((AT91PS_WD) 0xFFFF8000) // (WD) Base Address
#define AT91C_BASE_PS ((AT91PS_PS) 0xFFFF4000) // (PS) Base Address
#define AT91C_BASE_PIO ((AT91PS_PIO) 0xFFFF0000) // (PIO) Base Address
#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFE0080) // (TC2) Base Address
#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFE0040) // (TC1) Base Address
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFE0000) // (TC0) Base Address
#define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFE0000) // (TCB0) Base Address
#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4030) // (PDC_US1) Base Address
#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFCC000) // (US1) Base Address
#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0030) // (PDC_US0) Base Address
#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFD0000) // (US0) Base Address
#define AT91C_BASE_SF ((AT91PS_SF) 0xFFF00000) // (SF) Base Address
#define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFE00000) // (EBI) Base Address
// *****************************************************************************
// MEMORY MAPPING DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_SRAM_BEFORE_REMAP ((char *) 0x00300000) // Internal SRAM before remap base address
#define AT91C_SRAM_BEFORE_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM before remap size in byte (256 Kbyte)
#define AT91C_SRAM_AFTER_REMAP ((char *) 0x00000000) // Internal SRAM after remap base address
#define AT91C_SRAM_AFTER_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM after remap size in byte (256 Kbyte)
#endif

24
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg Normal file
View File

@ -0,0 +1,24 @@
[SETUP]
CpuVendor=Atmel
CpuChip=AT91R40807
FlashVendor=Atmel
FlashChip=AT49BV/F1614A
RamAddress=$00000000
RamSupport=1
FlashAddress=$01000000
FlashWidth=16
FlashChipsPerSector=1
LittleEndian=0
SectStart=0
SectEnd=38
AutoErase=0
AutoVerify=1
CpuEndian=LITTLE
SimCount=3
MemoryCount=0
ProgramFile=E:\temp\embesttest\Demo\ARM7_AT91R40008_GCC_Embest\rtosdemo.hex
UploadFile=c:\EB40_Lower.bin
Format=Intel Hex
Sim3=EBI_RCR:$00000001
Sim2=EBI_CSR1:$02002122
Sim1=EBI_CSR0:$01002539

79
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h Normal file
View File

@ -0,0 +1,79 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <AT91R40008.h>
#define configFLASH_SPEED_NSEC 100 /* External flash access speed (for ROM builds) */
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html
*/
/*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) 66000000 ) /* = 66.000MHz clk gen */
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configMAX_PRIORITIES ( 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 128 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 25 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

99
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/Makefile Normal file
View File

@ -0,0 +1,99 @@
#/*
# * FreeRTOS V202111.00
# * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
# *
# * Permission is hereby granted, free of charge, to any person obtaining a copy of
# * this software and associated documentation files (the "Software"), to deal in
# * the Software without restriction, including without limitation the rights to
# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
# * the Software, and to permit persons to whom the Software is furnished to do so,
# * subject to the following conditions:
# *
# * The above copyright notice and this permission notice shall be included in all
# * copies or substantial portions of the Software.
# *
# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# *
# * http://www.FreeRTOS.org
# * http://aws.amazon.com/freertos
# *
# * 1 tab == 4 spaces!
# */
CC=arm-elf-gcc
OBJCOPY=arm-elf-objcopy
ARCH=arm-elf-ar
CRT0=boot.s
#
# CFLAGS common to both the THUMB and ARM mode builds
#
CFLAGS=-Wall -Wextra -D $(RUN_MODE) -D GCC_AT91FR40008 -I. -I../../Source/include \
-I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \
-Wcast-align $(OPTIM) -fomit-frame-pointer -fno-strict-aliasing \
-fno-dwarf2-cfi-asm
ifeq ($(USE_THUMB_MODE),YES)
CFLAGS += -mthumb-interwork -D THUMB_INTERWORK
THUMB_FLAGS=-mthumb
endif
LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map
#
# Source files that can be built to THUMB mode.
#
THUMB_SRC = \
main.c \
serial/serial.c \
ParTest/ParTest.c \
../Common/Minimal/integer.c \
../Common/Minimal/flash.c \
../Common/Minimal/PollQ.c \
../Common/Minimal/comtest.c \
../Common/Minimal/flop.c \
../Common/Minimal/semtest.c \
../Common/Minimal/dynamic.c \
../Common/Minimal/BlockQ.c \
../../Source/tasks.c \
../../Source/queue.c \
../../Source/list.c \
../../Source/portable/MemMang/heap_2.c \
../../Source/portable/GCC/ARM7_AT91FR40008/port.c
#
# Source files that must be built to ARM mode.
#
ARM_SRC = \
../../Source/portable/GCC/ARM7_AT91FR40008/portISR.c \
serial/serialISR.c
#
# Define all object files.
#
ARM_OBJ = $(ARM_SRC:.c=.o)
THUMB_OBJ = $(THUMB_SRC:.c=.o)
rtosdemo.hex : rtosdemo.elf
$(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex
rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile
$(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)
$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
$(CC) -c $(CFLAGS) $< -o $@
clean :
touch Makefile
rm $(ARM_OBJ)
rm $(THUMB_OBJ)

115
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c Normal file
View File

@ -0,0 +1,115 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "portable.h"
/* Demo app includes. */
#include "partest.h"
/* Hardware specific definitions. */
#include "AT91R40008.h"
#include "pio.h"
#include "aic.h"
#define partstNUM_LEDS ( 8 )
#define partstALL_OUTPUTS_OFF ( ( unsigned long ) ~(0xFFFFFFFF << partstNUM_LEDS) )
static unsigned long ulLEDReg;
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
static void SetLeds (unsigned int leds)
{
unsigned long ulPIOSetReg, ulPIOClearReg;
/* LEDs are grouped in different port bits: P3-P6 and P16-P19.
A port bit set to '0' turns an LED on, '1' turns it off. */
ulPIOSetReg = ( (leds & 0xF) << 16 ) | ( (leds & 0xF0) >> 1 );
ulPIOClearReg = (~ulPIOSetReg) & 0x000F0078;
AT91C_BASE_PIO->PIO_SODR = ulPIOSetReg;
AT91C_BASE_PIO->PIO_CODR = ulPIOClearReg;
}
/*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* This is performed from main() as the io bits are shared with other setup
functions. Ensure the outputs are off to start. */
ulLEDReg = partstALL_OUTPUTS_OFF;
/* Enable clock to PIO... */
AT91C_BASE_PS->PS_PCER = AT91C_PS_PIO;
/* Enable all 8 LEDs and the four switches to be controlled by PIO... */
AT91C_BASE_PIO->PIO_PER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19 | P1 | P2 | P9 | P12;
/* Configure all LED PIO lines for output... */
AT91C_BASE_PIO->PIO_OER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19;
/* Configure all switch PIO lines for input... */
AT91C_BASE_PIO->PIO_ODR = P1 | P2 | P9 | P12;
/* Set initial state of LEDs. */
SetLeds( ulLEDReg );
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
/* Switch an LED on or off as requested. */
if (uxLED < partstNUM_LEDS)
{
if( xValue )
{
ulLEDReg &= ~(1 << uxLED);
}
else
{
ulLEDReg |= (1 << uxLED);
}
SetLeds( ulLEDReg );
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
/* Toggle the state of the requested LED. */
if (uxLED < partstNUM_LEDS)
{
ulLEDReg ^= ( 1 << uxLED );
SetLeds( ulLEDReg );
}
}

81
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/aic.h Normal file
View File

@ -0,0 +1,81 @@
//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name : aic.h
//* Object : Advanced Interrupt Controller Definition File.
//*
//* 1.0 01/04/00 JCZ : Creation
//*----------------------------------------------------------------------------
#ifndef aic_h
#define aic_h
//#include "periph/stdc/std_c.h"
/*-----------------------------------------*/
/* AIC User Interface Structure Definition */
/*-----------------------------------------*/
typedef struct
{
at91_reg AIC_SMR[32] ; /* Source Mode Register */
at91_reg AIC_SVR[32] ; /* Source Vector Register */
at91_reg AIC_IVR ; /* IRQ Vector Register */
at91_reg AIC_FVR ; /* FIQ Vector Register */
at91_reg AIC_ISR ; /* Interrupt Status Register */
at91_reg AIC_IPR ; /* Interrupt Pending Register */
at91_reg AIC_IMR ; /* Interrupt Mask Register */
at91_reg AIC_CISR ; /* Core Interrupt Status Register */
at91_reg reserved0 ;
at91_reg reserved1 ;
at91_reg AIC_IECR ; /* Interrupt Enable Command Register */
at91_reg AIC_IDCR ; /* Interrupt Disable Command Register */
at91_reg AIC_ICCR ; /* Interrupt Clear Command Register */
at91_reg AIC_ISCR ; /* Interrupt Set Command Register */
at91_reg AIC_EOICR ; /* End of Interrupt Command Register */
at91_reg AIC_SPU ; /* Spurious Vector Register */
} StructAIC ;
/*--------------------------------------------*/
/* AIC_SMR[]: Interrupt Source Mode Registers */
/*--------------------------------------------*/
#define AIC_PRIOR 0x07 /* Priority */
#define AIC_SRCTYPE 0x60 /* Source Type Definition */
/* Internal Interrupts */
#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00 /* Level Sensitive */
#define AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x20 /* Edge Triggered */
/* External Interrupts */
#define AIC_SRCTYPE_EXT_LOW_LEVEL 0x00 /* Low Level */
#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x20 /* Negative Edge */
#define AIC_SRCTYPE_EXT_HIGH_LEVEL 0x40 /* High Level */
#define AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x60 /* Positive Edge */
/*------------------------------------*/
/* AIC_ISR: Interrupt Status Register */
/*------------------------------------*/
#define AIC_IRQID 0x1F /* Current source interrupt */
/*------------------------------------------*/
/* AIC_CISR: Interrupt Core Status Register */
/*------------------------------------------*/
#define AIC_NFIQ 0x01 /* Core FIQ Status */
#define AIC_NIRQ 0x02 /* Core IRQ Status */
/*-------------------------------*/
/* Advanced Interrupt Controller */
/*-------------------------------*/
#define AIC_BASE ((StructAIC *)0xFFFFF000)
#endif /* aic_h */

54
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld Normal file
View File

@ -0,0 +1,54 @@
MEMORY
{
ram : ORIGIN = 0x00000000, LENGTH = 256K
}
__stack_end__ = 0x00000000 + 256K - 4;
SECTIONS
{
. = 0;
startup : { *(.startup)} >ram
prog :
{
*(.text)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
} >ram
__end_of_text__ = .;
.data :
{
__data_beg__ = .;
__data_beg_src__ = __end_of_text__;
*(.data)
__data_end__ = .;
} >ram
.bss :
{
__bss_beg__ = .;
*(.bss)
} >ram
. = ALIGN(4);
.eh_frame :
{
KEEP (*(.eh_frame))
} > ram
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
}
. = ALIGN(32 / 8);
_end = .;
_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
PROVIDE (end = .);

55
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld Normal file
View File

@ -0,0 +1,55 @@
MEMORY
{
flash : ORIGIN = 0x00000000, LENGTH = 2048K
ram : ORIGIN = 0x00300000, LENGTH = 256K
}
__stack_end__ = 0x00300000 + 256K - 4;
SECTIONS
{
. = 0;
startup : { *(.startup)} >flash
prog :
{
*(.text)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
} >flash
__end_of_text__ = .;
.data :
{
__data_beg__ = .;
__data_beg_src__ = __end_of_text__;
*(.data)
__data_end__ = .;
} >ram AT>flash
.bss :
{
__bss_beg__ = .;
*(.bss)
} >ram
. = ALIGN(4);
.eh_frame :
{
KEEP (*(.eh_frame))
} > ram
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
}
. = ALIGN(32 / 8);
_end = .;
_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
PROVIDE (end = .);

157
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/boot.s Normal file
View File

@ -0,0 +1,157 @@
/* Sample initialization file */
.extern main
.extern exit
.text
.code 32
.align 0
.extern __bss_beg__
.extern __bss_end__
.extern __stack_end__
.extern __data_beg__
.extern __data_end__
.extern __data+beg_src__
.global start
.global endless_loop
/* Stack Sizes */
.set UND_STACK_SIZE, 0x00000004
.set ABT_STACK_SIZE, 0x00000004
.set FIQ_STACK_SIZE, 0x00000004
.set IRQ_STACK_SIZE, 0X00000400
.set SVC_STACK_SIZE, 0x00000400
/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
.set MODE_USR, 0x10 /* User Mode */
.set MODE_FIQ, 0x11 /* FIQ Mode */
.set MODE_IRQ, 0x12 /* IRQ Mode */
.set MODE_SVC, 0x13 /* Supervisor Mode */
.set MODE_ABT, 0x17 /* Abort Mode */
.set MODE_UND, 0x1B /* Undefined Mode */
.set MODE_SYS, 0x1F /* System Mode */
.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
start:
_start:
_mainCRTStartup:
/* Setup a stack for each mode - note that this only sets up a usable stack
for system/user, SWI and IRQ modes. Also each mode is setup with
interrupts initially disabled. */
ldr r0, .LC6
msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
mov sp, r0
sub r0, r0, #UND_STACK_SIZE
msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
mov sp, r0
sub r0, r0, #ABT_STACK_SIZE
msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
mov sp, r0
sub r0, r0, #FIQ_STACK_SIZE
msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
mov sp, r0
sub r0, r0, #IRQ_STACK_SIZE
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
mov sp, r0
sub r0, r0, #SVC_STACK_SIZE
msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
mov sp, r0
/* We want to start in supervisor mode. Operation will switch to system
mode when the first task starts. */
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT
/* Clear BSS. */
mov a2, #0 /* Fill value */
mov fp, a2 /* Null frame pointer */
mov r7, a2 /* Null frame pointer for Thumb */
ldr r1, .LC1 /* Start of memory block */
ldr r3, .LC2 /* End of memory block */
subs r3, r3, r1 /* Length of block */
beq .end_clear_loop
mov r2, #0
.clear_loop:
strb r2, [r1], #1
subs r3, r3, #1
bgt .clear_loop
.end_clear_loop:
/* Initialise data. */
ldr r1, .LC3 /* Start of memory block */
ldr r2, .LC4 /* End of memory block */
ldr r3, .LC5
subs r3, r3, r1 /* Length of block */
beq .end_set_loop
.set_loop:
ldrb r4, [r2], #1
strb r4, [r1], #1
subs r3, r3, #1
bgt .set_loop
.end_set_loop:
mov r0, #0 /* no arguments */
mov r1, #0 /* no argv either */
bl main
endless_loop:
b endless_loop
.align 0
.LC1:
.word __bss_beg__
.LC2:
.word __bss_end__
.LC3:
.word __data_beg__
.LC4:
.word __data_beg_src__
.LC5:
.word __data_end__
.LC6:
.word __stack_end__
/* Setup vector table. Note that undf, pabt, dabt, fiq just execute
a null loop. */
.section .startup,"ax"
.code 32
.align 0
b _start /* reset - _start */
ldr pc, _undf /* undefined - _undf */
ldr pc, _swi /* SWI - _swi */
ldr pc, _pabt /* program abort - _pabt */
ldr pc, _dabt /* data abort - _dabt */
nop /* reserved */
ldr pc, [pc,#-0xF20] /* IRQ - read the AIC */
ldr pc, _fiq /* FIQ - _fiq */
_undf: .word __undf /* undefined */
_swi: .word vPortYieldProcessor /* SWI */
_pabt: .word __pabt /* program abort */
_dabt: .word __dabt /* data abort */
_fiq: .word __fiq /* FIQ */
__undf: b . /* undefined */
__pabt: b . /* program abort */
__dabt: b . /* data abort */
__fiq: b . /* FIQ */

121
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ebi.h Normal file
View File

@ -0,0 +1,121 @@
//*-----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*-----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : ebi.h
//* Object : External Bus Interface Definition File
//* Translator : ARM Software Development Toolkit V2.11a
//*
//* 1.0 03/11/97 JCZ : Creation
//* 2.0 21/10/98 JCZ : Clean up
//*-----------------------------------------------------------------------------
#ifndef ebi_h
#define ebi_h
/*----------------------------------------*/
/* Memory Controller Interface Definition */
/*----------------------------------------*/
typedef struct
{
at91_reg EBI_CSR[8] ; /* Chip Select Register */
at91_reg EBI_RCR ; /* Remap Control Register */
at91_reg EBI_MCR ; /* Memory Control Register */
} StructEBI ;
/*-----------------------*/
/* Chip Select Registers */
/*-----------------------*/
/* Data Bus Width */
#define DataBus16 (1<<0)
#define DataBus8 (2<<0)
#define DBW (3<<0)
/* Number of Wait States */
#define B_NWS 2
#define WaitState1 (0<<B_NWS)
#define WaitState2 (1<<B_NWS)
#define WaitState3 (2<<B_NWS)
#define WaitState4 (3<<B_NWS)
#define WaitState5 (4<<B_NWS)
#define WaitState6 (5<<B_NWS)
#define WaitState7 (6<<B_NWS)
#define WaitState8 (7<<B_NWS)
#define NWS (7<<B_NWS)
/* Wait State Enable */
#define WaitStateDisable (0<<5)
#define WaitStateEnable (1<<5)
#define WSE (1<<5)
/* Page size */
#define PageSize1M (0<<7)
#define PageSize4M (1<<7)
#define PageSize16M (2<<7)
#define PageSize64M (3<<7)
#define PAGES (3<<7)
/* Number of Data Float Output Time Clock Cycle */
#define B_TDF 9
#define tDF_0cycle (0<<B_TDF)
#define tDF_1cycle (1<<B_TDF)
#define tDF_2cycle (2<<B_TDF)
#define tDF_3cycle (3<<B_TDF)
#define tDF_4cycle (4<<B_TDF)
#define tDF_5cycle (5<<B_TDF)
#define tDF_6cycle (6<<B_TDF)
#define tDF_7cycle (7<<B_TDF)
#define TDF (7<<B_TDF)
/* Byte Access Type */
#define ByteWriteAccessType (0<<12)
#define ByteSelectAccessType (1<<12)
#define BAT 1<<12)
/* Chip Select Enable */
#define CSEnable (1<<13)
#define CSDisable (0<<13)
#define CSE (1<<13)
#define BA ((u_int)(0xFFF)<<20)
/*-------------------------*/
/* Memory Control Register */
/*-------------------------*/
/* Address Line Enable */
#define ALE (7<<0)
#define BankSize16M (0<<0)
#define BankSize8M (4<<0)
#define BankSize4M (5<<0)
#define BankSize2M (6<<0)
#define BankSize1M (7<<0)
/* Data Read Protocol */
#define StandardReadProtocol (0<<4)
#define EarlyReadProtocol (1<<4)
#define DRP (1<<4)
/*------------------------*/
/* Remap Control Register */
/*------------------------*/
#define RCB (1<<0)
/*--------------------------------*/
/* Device Dependancies Definition */
/*--------------------------------*/
#ifdef AT91M40400
/* External Bus Interface User Interface BAse Address */
#define EBI_BASE ((StructEBI *) 0xFFE00000)
#endif
#endif /* ebi_h */

467
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/main.c Normal file
View File

@ -0,0 +1,467 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
* To check the operation of the memory allocator the check task also
* dynamically creates a task before delaying, and deletes it again when it
* wakes. If memory cannot be allocated for the new task the call to xTaskCreate
* will fail and an error is signalled. The dynamically created task itself
* allocates and frees memory just to give the allocator a bit more exercise.
*
*/
/* Standard includes. */
#include <stdlib.h>
#include <string.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "partest.h"
#include "flash.h"
#include "integer.h"
#include "PollQ.h"
#include "comtest2.h"
#include "semtest.h"
#include "flop.h"
#include "dynamic.h"
#include "BlockQ.h"
#include "serial.h"
/* Hardware specific definitions. */
#include "aic.h"
#include "ebi.h"
/*-----------------------------------------------------------*/
/* Constants for the ComTest tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 )
#define mainCOM_TEST_LED ( 5 )
/* Priorities for the demo application tasks. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* The rate at which the on board LED will toggle when there is/is not an
error. */
#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS )
#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS )
#define mainON_BOARD_LED_BIT ( ( unsigned long ) 7 )
/* Constants used by the vMemCheckTask() task. */
#define mainCOUNT_INITIAL_VALUE ( ( unsigned long ) 0 )
#define mainNO_TASK ( 0 )
/* The size of the memory blocks allocated by the vMemCheckTask() task. */
#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )
#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )
#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )
#define MAX_WAIT_STATES 8
static const unsigned long ululCSRWaitValues[ MAX_WAIT_STATES + 1 ] =
{
WaitState1,/* There is no "zero wait state" value, so use one wait state */
WaitState1,
WaitState2,
WaitState3,
WaitState4,
WaitState5,
WaitState6,
WaitState7,
WaitState8
};
/*-----------------------------------------------------------*/
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static long prvCheckOtherTasksAreStillRunning( unsigned long ulMemCheckTaskCount );
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Dynamically created and deleted during each cycle of the vErrorChecks()
* task. This is done to check the operation of the memory allocator.
* See the top of vErrorChecks for more details.
*/
static void vMemCheckTask( void *pvParameters );
/*
* Configure the processor for use with the Olimex demo board. This includes
* setup for the I/O, system clock, and access timings.
*/
static void prvSetupHardware( void );
/*-----------------------------------------------------------*/
/*
* Starts all the other tasks, then starts the scheduler.
*/
int main( void )
{
/* Setup the hardware for use with the Olimex demo board. */
prvSetupHardware();
/* Start the demo/test application tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartMathTasks( tskIDLE_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartDynamicPriorityTasks();
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
/* Start the check task - which is defined in this file. */
xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Now all the tasks have been started - start the scheduler.
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used here. */
vTaskStartScheduler();
/* Should never reach here! */
return 0;
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
unsigned long ulMemCheckTaskRunningCount;
TaskHandle_t xCreatedTask;
/* Just to stop compiler warnings. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. If an error is detected then the delay period
is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
the on board LED flash rate will increase.
In addition to the standard tests the memory allocator is tested through
the dynamic creation and deletion of a task each cycle. Each time the
task is created memory must be allocated for its stack. When the task is
deleted this memory is returned to the heap. If the task cannot be created
then it is likely that the memory allocation failed. */
for( ;; )
{
/* Reset xCreatedTask. This is modified by the task about to be
created so we can tell if it is executing correctly or not. */
xCreatedTask = mainNO_TASK;
/* Dynamically create a task - passing ulMemCheckTaskRunningCount as a
parameter. */
ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;
if( xTaskCreate( vMemCheckTask, "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
{
/* Could not create the task - we have probably run out of heap. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
/* Delay until it is time to execute again. */
vTaskDelay( xDelayPeriod );
/* Delete the dynamically created task. */
if( xCreatedTask != mainNO_TASK )
{
vTaskDelete( xCreatedTask );
}
/* Check all the standard demo application tasks are executing without
error. ulMemCheckTaskRunningCount is checked to ensure it was
modified by the task just deleted. */
if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
/* The toggle rate of the LED depends on how long this task delays for.
An error reduces the delay period and so increases the toggle rate. */
vParTestToggleLED( mainON_BOARD_LED_BIT );
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
long lCount;
#ifdef RUN_FROM_ROM
{
portFLOAT nsecsPerClockTick;
long lNumWaitStates;
unsigned long ulCSRWaitValue;
/* We are compiling to run from ROM (either on-chip or off-chip flash).
Leave the RAM/flash mapped the way they are on reset
(flash @ 0x00000000, RAM @ 0x00300000), and set up the
proper flash wait states (starts out at the maximum number
of wait states on reset, so we should be able to reduce it).
Most of this code will probably get removed by the compiler
if optimization is enabled, since these calculations are
based on constants. But the compiler should still produce
a correct wait state register value. */
nsecsPerClockTick = ( portFLOAT ) 1000000000 / configCPU_CLOCK_HZ;
lNumWaitStates = ( long )( ( configFLASH_SPEED_NSEC / nsecsPerClockTick ) + 0.5 ) - 1;
if( lNumWaitStates < 0 )
{
lNumWaitStates = 0;
}
if( lNumWaitStates > MAX_WAIT_STATES )
{
lNumWaitStates = MAX_WAIT_STATES;
}
ulCSRWaitValue = ululCSRWaitValues[ lNumWaitStates ];
ulCSRWaitValue = WaitState5;
AT91C_BASE_EBI->EBI_CSR[ 0 ] = ulCSRWaitValue | DataBus16 | WaitStateEnable
| PageSize1M | tDF_0cycle
| ByteWriteAccessType | CSEnable
| 0x00000000 /* Base Address */;
}
#else /* else we are compiling to run from on-chip RAM */
{
/* If compiling to run from RAM, we expect the on-chip RAM to already
be mapped at 0x00000000. This is typically done with an initialization
script for the JTAG emulator you are using to download and run the
demo application. So there is nothing to do here in this case. */
}
#endif
/* Disable all interrupts at the AIC level initially... */
AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
/* Set all SVR and SMR entries to default values (start with a clean slate)... */
for( lCount = 0; lCount < 32; lCount++ )
{
AT91C_BASE_AIC->AIC_SVR[ lCount ] = (unsigned long) 0;
AT91C_BASE_AIC->AIC_SMR[ lCount ] = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
}
/* Disable clocks to all peripherals initially... */
AT91C_BASE_PS->PS_PCDR = 0xFFFFFFFF;
/* Clear all interrupts at the AIC level initially... */
AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
/* Perform 8 "End Of Interrupt" cmds to make sure AIC will not Lock out
nIRQ */
for( lCount = 0; lCount < 8; lCount++ )
{
AT91C_BASE_AIC->AIC_EOICR = 0;
}
/* Initialise LED outputs. */
vParTestInitialise();
}
/*-----------------------------------------------------------*/
static long prvCheckOtherTasksAreStillRunning( unsigned long ulMemCheckTaskCount )
{
long lReturn = ( long ) pdPASS;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none of them have detected
an error. */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )
{
/* The vMemCheckTask did not increment the counter - it must
have failed. */
lReturn = ( long ) pdFAIL;
}
return lReturn;
}
/*-----------------------------------------------------------*/
static void vMemCheckTask( void *pvParameters )
{
unsigned long *pulMemCheckTaskRunningCounter;
void *pvMem1, *pvMem2, *pvMem3;
static long lErrorOccurred = pdFALSE;
/* This task is dynamically created then deleted during each cycle of the
vErrorChecks task to check the operation of the memory allocator. Each time
the task is created memory is allocated for the stack and TCB. Each time
the task is deleted this memory is returned to the heap. This task itself
exercises the allocator by allocating and freeing blocks.
The task executes at the idle priority so does not require a delay.
pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the
vErrorChecks() task that this task is still executing without error. */
pulMemCheckTaskRunningCounter = ( unsigned long * ) pvParameters;
for( ;; )
{
if( lErrorOccurred == pdFALSE )
{
/* We have never seen an error so increment the counter. */
( *pulMemCheckTaskRunningCounter )++;
}
else
{
/* There has been an error so reset the counter so the check task
can tell that an error occurred. */
*pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE;
}
/* Allocate some memory - just to give the allocator some extra
exercise. This has to be in a critical section to ensure the
task does not get deleted while it has memory allocated. */
vTaskSuspendAll();
{
pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );
if( pvMem1 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );
vPortFree( pvMem1 );
}
}
xTaskResumeAll();
/* Again - with a different size block. */
vTaskSuspendAll();
{
pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );
if( pvMem2 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );
vPortFree( pvMem2 );
}
}
xTaskResumeAll();
/* Again - with a different size block. */
vTaskSuspendAll();
{
pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );
if( pvMem3 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );
vPortFree( pvMem3 );
}
}
xTaskResumeAll();
}
}

149
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/pio.h Normal file
View File

@ -0,0 +1,149 @@
//*---------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*---------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : pio.h
//* Object : Parallel I/O Definition File
//* Translator : ARM Software Development Toolkit V2.11a
//*
//* 1.0 20/10/97 JCZ : Creation
//* 2.0 21/10/98 JCZ : Clean up
//*---------------------------------------------------------------------------
#ifndef pio_h
#define pio_h
/*---------------------------------------------*/
/* Parallel I/O Interface Structure Definition */
/*---------------------------------------------*/
typedef struct
{
at91_reg PIO_PER ; /* PIO Enable Register */
at91_reg PIO_PDR ; /* PIO Disable Register */
at91_reg PIO_PSR ; /* PIO Status Register */
at91_reg Reserved0 ;
at91_reg PIO_OER ; /* Output Enable Register */
at91_reg PIO_ODR ; /* Output Disable Register */
at91_reg PIO_OSR ; /* Output Status Register */
at91_reg Reserved1 ;
at91_reg PIO_IFER ; /* Input Filter Enable Register */
at91_reg PIO_IFDR ; /* Input Filter Disable Register */
at91_reg PIO_IFSR ; /* Input Filter Status Register */
at91_reg Reserved2 ;
at91_reg PIO_SODR ; /* Set Output Data Register */
at91_reg PIO_CODR ; /* Clear Output Data Register */
at91_reg PIO_ODSR ; /* Output Data Status Register */
at91_reg PIO_PDSR ; /* Pin Data Status Register */
at91_reg PIO_IER ; /* Interrupt Enable Register */
at91_reg PIO_IDR ; /* Interrupt Disable Register */
at91_reg PIO_IMR ; /* Interrupt Mask Register */
at91_reg PIO_ISR ; /* Interrupt Status Register */
} StructPIO ;
/*-----------------------------*/
/* PIO Handler type definition */
/*-----------------------------*/
//typedef void (*TypePIOHandler) ( StructPIO *pio_pt, u_int pio_mask ) ;
/*--------------------------------*/
/* Device Dependancies Definition */
/*--------------------------------*/
/* Number of PIO Controller */
#define NB_PIO_CTRL 1
/* Base Address */
#define PIO_BASE ((StructPIO *) 0xFFFF0000 )
/* Number of PIO Lines */
#define NB_PIO 32
/* Parallel I/O Bits Definition */
#define P0 (1<<0)
#define P1 (1<<1)
#define P2 (1<<2)
#define P3 (1<<3)
#define P4 (1<<4)
#define P5 (1<<5)
#define P6 (1<<6)
#define P7 (1<<7)
#define P8 (1<<8)
#define P9 (1<<9)
#define P10 (1<<10)
#define P11 (1<<11)
#define P12 (1<<12)
#define P13 (1<<13)
#define P14 (1<<14)
#define P15 (1<<15)
#define P16 (1<<16)
#define P17 (1<<17)
#define P18 (1<<18)
#define P19 (1<<19)
#define P20 (1<<20)
#define P21 (1<<21)
#define P22 (1<<22)
#define P23 (1<<23)
#define P24 (1<<24)
#define P25 (1<<25)
#define P26 (1<<26)
#define P27 (1<<27)
#define P28 (1<<28)
#define P29 (1<<29)
#define P30 (1<<30)
#define P31 (1<<31)
/* PIO Multiplexing Definition */
/* There is only one PIO Controller */
#define PIO_CTRL 0
#define PIO_TC0 PIO_CTRL
#define TCLK0 P0
#define TIOA0 P1
#define TIOB0 P2
#define PIN_TC0 (TIOA0|TIOB0|TCLK0)
#define PIO_TC1 PIO_CTRL
#define TCLK1 P3
#define TIOA1 P4
#define TIOB1 P5
#define PIN_TC1 (TIOA1|TIOB1|TCLK1)
#define PIO_TC2 PIO_CTRL
#define TCLK2 P6
#define TIOA2 P7
#define TIOB2 P8
#define PIN_TC2 (TIOA2|TIOB2|TCLK2)
#define PIO_EXT_IRQ PIO_CTRL
#define PIN_IRQ0 P9
#define PIN_IRQ1 P10
#define PIN_IRQ2 P11
#define PIN_FIQ P12
#define PIO_USART0 PIO_CTRL
#define SCK0 P13
#define TXD0 P14
#define RXD0 P15
#define PIN_USART0 (SCK0|TXD0|RXD0)
#define PIO_USART1 PIO_CTRL
#define SCK1 P20
#define TXD1 P21
#define RXD1 P22
#define PIN_USART1 (SCK1|TXD1|RXD1)
#define MCKO P25
#define CS2 P26
#define CS3 P27
#define CS4 P31
#define CS5 P30
#define CS6 P29
#define CS7 P28
#endif /* pio_h */

6
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ram_arm.bat Normal file
View File

@ -0,0 +1,6 @@
set USE_THUMB_MODE=NO
set DEBUG=-g
set OPTIM=-O0
set RUN_MODE=RUN_FROM_RAM
set LDSCRIPT=atmel-ram.ld
make

6
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/ram_thumb.bat Normal file
View File

@ -0,0 +1,6 @@
set USE_THUMB_MODE=YES
set DEBUG=-g
set OPTIM=-O0
set RUN_MODE=RUN_FROM_RAM
set LDSCRIPT=atmel-ram.ld
make

6
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/rom_arm.bat Normal file
View File

@ -0,0 +1,6 @@
set USE_THUMB_MODE=NO
set DEBUG=-g
set OPTIM=-O2
set RUN_MODE=RUN_FROM_ROM
set LDSCRIPT=atmel-rom.ld
make

6
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat Normal file
View File

@ -0,0 +1,6 @@
set USE_THUMB_MODE=YES
set DEBUG=-g
set OPTIM=-O2
set RUN_MODE=RUN_FROM_ROM
set LDSCRIPT=atmel-rom.ld
make

227
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/serial/serial.c Normal file
View File

@ -0,0 +1,227 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0.
This file contains all the serial port components that can be compiled to
either ARM or THUMB mode. Components that must be compiled to ARM mode are
contained in serialISR.c.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
#include "AT91R40008.h"
#include "usart.h"
#include "pio.h"
#include "aic.h"
/*-----------------------------------------------------------*/
/* Constants to setup and access the UART. */
#define portUSART0_AIC_CHANNEL ( ( unsigned long ) 2 )
#define serINVALID_QUEUE ( ( QueueHandle_t ) 0 )
#define serHANDLE ( ( xComPortHandle ) 1 )
#define serNO_BLOCK ( ( TickType_t ) 0 )
/*-----------------------------------------------------------*/
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static QueueHandle_t xRxedChars;
static QueueHandle_t xCharsForTx;
/*-----------------------------------------------------------*/
/*
* The queues are created in serialISR.c as they are used from the ISR.
* Obtain references to the queues and THRE Empty flag.
*/
extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, QueueHandle_t *pxRxedChars, QueueHandle_t *pxCharsForTx );
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned long ulSpeed;
unsigned long ulCD;
xComPortHandle xReturn = serHANDLE;
extern void ( vUART_ISR_Wrapper )( void );
/* The queues are used in the serial ISR routine, so are created from
serialISR.c (which is always compiled to ARM mode. */
vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx );
if(
( xRxedChars != serINVALID_QUEUE ) &&
( xCharsForTx != serINVALID_QUEUE ) &&
( ulWantedBaud != ( unsigned long ) 0 )
)
{
portENTER_CRITICAL();
{
/* Enable clock to USART0... */
AT91C_BASE_PS->PS_PCER = AT91C_PS_US0;
/* Disable all USART0 interrupt sources to begin... */
AT91C_BASE_US0->US_IDR = 0xFFFFFFFF;
/* Reset various status bits (just in case)... */
AT91C_BASE_US0->US_CR = US_RSTSTA;
AT91C_BASE_PIO->PIO_PDR = TXD0 | RXD0; /* Enable RXD and TXD pins */
AT91C_BASE_US0->US_CR = US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS;
/* Clear Transmit and Receive Counters */
AT91C_BASE_US0->US_RCR = 0;
AT91C_BASE_US0->US_TCR = 0;
/* Input clock to baud rate generator is MCK */
ulSpeed = configCPU_CLOCK_HZ * 10;
ulSpeed = ulSpeed / 16;
ulSpeed = ulSpeed / ulWantedBaud;
/* compute the error */
ulCD = ulSpeed / 10;
if ((ulSpeed - (ulCD * 10)) >= 5)
ulCD++;
/* Define the baud rate divisor register */
AT91C_BASE_US0->US_BRGR = ulCD;
/* Define the USART mode */
AT91C_BASE_US0->US_MR = US_CLKS_MCK | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1 | US_CHMODE_NORMAL;
/* Write the Timeguard Register */
AT91C_BASE_US0->US_TTGR = 0;
/* Setup the interrupt for USART0.
Store interrupt handler function address in USART0 vector register... */
AT91C_BASE_AIC->AIC_SVR[ portUSART0_AIC_CHANNEL ] = (unsigned long)vUART_ISR_Wrapper;
/* USART0 interrupt level-sensitive, priority 1... */
AT91C_BASE_AIC->AIC_SMR[ portUSART0_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 1;
/* Clear some pending USART0 interrupts (just in case)... */
AT91C_BASE_US0->US_CR = US_RSTSTA;
/* Enable USART0 interrupt sources (but not Tx for now)... */
AT91C_BASE_US0->US_IER = US_RXRDY;
/* Enable USART0 interrupts in the AIC... */
AT91C_BASE_AIC->AIC_IECR = ( 1 << portUSART0_AIC_CHANNEL );
/* Enable receiver and transmitter... */
AT91C_BASE_US0->US_CR = US_RXEN | US_TXEN;
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
{
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
{
signed char *pxNext;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
( void ) usStringLength;
/* Send each character in the string, one at a time. */
pxNext = ( signed char * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
{
( void ) pxPort;
/* Place the character in the queue of characters to be transmitted. */
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
{
return pdFAIL;
}
/* Turn on the Tx interrupt so the ISR will remove the character from the
queue and send it. This does not need to be in a critical section as
if the interrupt has already removed the character the next interrupt
will simply turn off the Tx interrupt again. */
AT91C_BASE_US0->US_IER = US_TXRDY;
return pdPASS;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
( void ) xPort;
}
/*-----------------------------------------------------------*/

154
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c Normal file
View File

@ -0,0 +1,154 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0.
This file contains all the serial port components that must be compiled
to ARM mode. The components that can be compiled to either ARM or THUMB
mode are contained in serial.c.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
#include "AT91R40008.h"
#include "usart.h"
/*-----------------------------------------------------------*/
/* Constant to access the AIC. */
#define serCLEAR_AIC_INTERRUPT ( ( unsigned long ) 0 )
/* Constants to determine the ISR source. */
#define serSOURCE_THRE ( ( unsigned char ) 0x02 )
#define serSOURCE_RX_TIMEOUT ( ( unsigned char ) 0x0c )
#define serSOURCE_ERROR ( ( unsigned char ) 0x06 )
#define serSOURCE_RX ( ( unsigned char ) 0x04 )
#define serINTERRUPT_SOURCE_MASK ( ( unsigned long ) (US_RXRDY | US_TXRDY | US_RXBRK | US_OVRE | US_FRAME | US_PARE) )
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static QueueHandle_t xRxedChars;
static QueueHandle_t xCharsForTx;
/*-----------------------------------------------------------*/
/* UART0 interrupt service routine. This can cause a context switch so MUST
be declared "naked". */
void vUART_ISR_Wrapper( void ) __attribute__ ((naked));
/* The ISR function that actually performs the work. This must be separate
from the wrapper to ensure the correct stack frame is set up. */
void vUART_ISR_Handler( void ) __attribute__ ((noinline));
/*-----------------------------------------------------------*/
void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, QueueHandle_t *pxRxedChars, QueueHandle_t *pxCharsForTx )
{
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
/* Pass back a reference to the queues so the serial API file can
post/receive characters. */
*pxRxedChars = xRxedChars;
*pxCharsForTx = xCharsForTx;
}
/*-----------------------------------------------------------*/
void vUART_ISR_Wrapper( void )
{
/* Save the context of the interrupted task. */
portSAVE_CONTEXT();
/* Call the handler. This must be a separate function to ensure the
stack frame is correctly set up. */
__asm volatile( "bl vUART_ISR_Handler" );
/* Restore the context of whichever task will run next. */
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
void vUART_ISR_Handler( void )
{
/* Now we can declare the local variables. These must be static. */
signed char cChar;
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
unsigned long ulStatus;
/* What caused the interrupt? */
ulStatus = AT91C_BASE_US0->US_CSR & AT91C_BASE_US0->US_IMR;
if (ulStatus & US_TXRDY)
{
/* The interrupt was caused by the THR becoming empty. Are there any
more characters to transmit? */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
{
/* A character was retrieved from the queue so can be sent to the
THR now. */
AT91C_BASE_US0->US_THR = cChar;
}
else
{
/* Queue empty, nothing to send so turn off the Tx interrupt. */
AT91C_BASE_US0->US_IDR = US_TXRDY;
}
}
if (ulStatus & US_RXRDY)
{
/* The interrupt was caused by the receiver getting data. */
cChar = AT91C_BASE_US0->US_RHR;
xQueueSendFromISR(xRxedChars, &cChar, &xHigherPriorityTaskWoken);
}
/* Acknowledge the interrupt at AIC level... */
AT91C_BASE_AIC->AIC_EOICR = serCLEAR_AIC_INTERRUPT;
/* If an event caused a task to unblock then we call "Yield from ISR" to
ensure that the unblocked task is the task that executes when the interrupt
completes if the unblocked task has a priority higher than the interrupted
task. */
if( xHigherPriorityTaskWoken )
{
portYIELD_FROM_ISR();
}
}
/*-----------------------------------------------------------*/

301
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/tc.h Normal file
View File

@ -0,0 +1,301 @@
//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : tc.h
//* Object : Timer Counter Header File
//*
//* 1.0 01/04/00 JCZ : Creation
//* 1.0 01/09/00 JPP : modification TC_BEEVT, TC_BEEVT_SET_OUTPUT,
//* TC_BEEVT_CLEAR_OUTPUT, TC_BEEVT_TOGGLE_OUTPUT
//*-----------------------------------------------------------------------------
#ifndef tc_h
#define tc_h
//#include "periph/stdc/std_c.h"
//#include "periph/pio/lib_pio.h"
/*-------------------------------------------*/
/* Timer User Interface Structure Definition */
/*-------------------------------------------*/
typedef struct
{
at91_reg TC_CCR ; /* Control Register */
at91_reg TC_CMR ; /* Mode Register */
at91_reg Reserved0 ;
at91_reg Reserved1 ;
at91_reg TC_CV ; /* Counter value */
at91_reg TC_RA ; /* Register A */
at91_reg TC_RB ; /* Register B */
at91_reg TC_RC ; /* Register C */
at91_reg TC_SR ; /* Status Register */
at91_reg TC_IER ; /* Interrupt Enable Register */
at91_reg TC_IDR ; /* Interrupt Disable Register */
at91_reg TC_IMR ; /* Interrupt Mask Register */
at91_reg Reserved2 ;
at91_reg Reserved3 ;
at91_reg Reserved4 ;
at91_reg Reserved5 ;
} StructTC ;
#define NB_TC_CHANNEL 3
typedef struct
{
StructTC TC[NB_TC_CHANNEL] ;
at91_reg TC_BCR ; /* Block Control Register */
at91_reg TC_BMR ; /* Block Mode Register */
} StructTCBlock ;
/*--------------------------------------------------------*/
/* TC_CCR: Timer Counter Control Register Bits Definition */
/*--------------------------------------------------------*/
#define TC_CLKEN 0x1
#define TC_CLKDIS 0x2
#define TC_SWTRG 0x4
/*---------------------------------------------------------------*/
/* TC_CMR: Timer Counter Channel Mode Register Bits Definition */
/*---------------------------------------------------------------*/
/*-----------------*/
/* Clock Selection */
/*-----------------*/
#define TC_CLKS 0x7
#define TC_CLKS_MCK2 0x0
#define TC_CLKS_MCK8 0x1
#define TC_CLKS_MCK32 0x2
#define TC_CLKS_MCK128 0x3
#define TC_CLKS_MCK1024 0x4
#define TC_CLKS_SLCK 0x4
#define TC_CLKS_XC0 0x5
#define TC_CLKS_XC1 0x6
#define TC_CLKS_XC2 0x7
/*-----------------*/
/* Clock Inversion */
/*-----------------*/
#define TC_CLKI 0x8
/*------------------------*/
/* Burst Signal Selection */
/*------------------------*/
#define TC_BURST 0x30
#define TC_BURST_NONE 0x0
#define TC_BUSRT_XC0 0x10
#define TC_BURST_XC1 0x20
#define TC_BURST_XC2 0x30
/*------------------------------------------------------*/
/* Capture Mode : Counter Clock Stopped with RB Loading */
/*------------------------------------------------------*/
#define TC_LDBSTOP 0x40
/*-------------------------------------------------------*/
/* Waveform Mode : Counter Clock Stopped with RC Compare */
/*-------------------------------------------------------*/
#define TC_CPCSTOP 0x40
/*-------------------------------------------------------*/
/* Capture Mode : Counter Clock Disabled with RB Loading */
/*--------------------------------------------------------*/
#define TC_LDBDIS 0x80
/*--------------------------------------------------------*/
/* Waveform Mode : Counter Clock Disabled with RC Compare */
/*--------------------------------------------------------*/
#define TC_CPCDIS 0x80
/*------------------------------------------------*/
/* Capture Mode : External Trigger Edge Selection */
/*------------------------------------------------*/
#define TC_ETRGEDG 0x300
#define TC_ETRGEDG_EDGE_NONE 0x0
#define TC_ETRGEDG_RISING_EDGE 0x100
#define TC_ETRGEDG_FALLING_EDGE 0x200
#define TC_ETRGEDG_BOTH_EDGE 0x300
/*-----------------------------------------------*/
/* Waveform Mode : External Event Edge Selection */
/*-----------------------------------------------*/
#define TC_EEVTEDG 0x300
#define TC_EEVTEDG_EDGE_NONE 0x0
#define TC_EEVTEDG_RISING_EDGE 0x100
#define TC_EEVTEDG_FALLING_EDGE 0x200
#define TC_EEVTEDG_BOTH_EDGE 0x300
/*--------------------------------------------------------*/
/* Capture Mode : TIOA or TIOB External Trigger Selection */
/*--------------------------------------------------------*/
#define TC_ABETRG 0x400
#define TC_ABETRG_TIOB 0x0
#define TC_ABETRG_TIOA 0x400
/*------------------------------------------*/
/* Waveform Mode : External Event Selection */
/*------------------------------------------*/
#define TC_EEVT 0xC00
#define TC_EEVT_TIOB 0x0
#define TC_EEVT_XC0 0x400
#define TC_EEVT_XC1 0x800
#define TC_EEVT_XC2 0xC00
/*--------------------------------------------------*/
/* Waveform Mode : Enable Trigger on External Event */
/*--------------------------------------------------*/
#define TC_ENETRG 0x1000
/*----------------------------------*/
/* RC Compare Enable Trigger Enable */
/*----------------------------------*/
#define TC_CPCTRG 0x4000
/*----------------*/
/* Mode Selection */
/*----------------*/
#define TC_WAVE 0x8000
#define TC_CAPT 0x0
/*-------------------------------------*/
/* Capture Mode : RA Loading Selection */
/*-------------------------------------*/
#define TC_LDRA 0x30000
#define TC_LDRA_EDGE_NONE 0x0
#define TC_LDRA_RISING_EDGE 0x10000
#define TC_LDRA_FALLING_EDGE 0x20000
#define TC_LDRA_BOTH_EDGE 0x30000
/*-------------------------------------------*/
/* Waveform Mode : RA Compare Effect on TIOA */
/*-------------------------------------------*/
#define TC_ACPA 0x30000
#define TC_ACPA_OUTPUT_NONE 0x0
#define TC_ACPA_SET_OUTPUT 0x10000
#define TC_ACPA_CLEAR_OUTPUT 0x20000
#define TC_ACPA_TOGGLE_OUTPUT 0x30000
/*-------------------------------------*/
/* Capture Mode : RB Loading Selection */
/*-------------------------------------*/
#define TC_LDRB 0xC0000
#define TC_LDRB_EDGE_NONE 0x0
#define TC_LDRB_RISING_EDGE 0x40000
#define TC_LDRB_FALLING_EDGE 0x80000
#define TC_LDRB_BOTH_EDGE 0xC0000
/*-------------------------------------------*/
/* Waveform Mode : RC Compare Effect on TIOA */
/*-------------------------------------------*/
#define TC_ACPC 0xC0000
#define TC_ACPC_OUTPUT_NONE 0x0
#define TC_ACPC_SET_OUTPUT 0x40000
#define TC_ACPC_CLEAR_OUTPUT 0x80000
#define TC_ACPC_TOGGLE_OUTPUT 0xC0000
/*-----------------------------------------------*/
/* Waveform Mode : External Event Effect on TIOA */
/*-----------------------------------------------*/
#define TC_AEEVT 0x300000
#define TC_AEEVT_OUTPUT_NONE 0x0
#define TC_AEEVT_SET_OUTPUT 0x100000
#define TC_AEEVT_CLEAR_OUTPUT 0x200000
#define TC_AEEVT_TOGGLE_OUTPUT 0x300000
/*-------------------------------------------------*/
/* Waveform Mode : Software Trigger Effect on TIOA */
/*-------------------------------------------------*/
#define TC_ASWTRG 0xC00000
#define TC_ASWTRG_OUTPUT_NONE 0x0
#define TC_ASWTRG_SET_OUTPUT 0x400000
#define TC_ASWTRG_CLEAR_OUTPUT 0x800000
#define TC_ASWTRG_TOGGLE_OUTPUT 0xC00000
/*-------------------------------------------*/
/* Waveform Mode : RB Compare Effect on TIOB */
/*-------------------------------------------*/
#define TC_BCPB 0x1000000
#define TC_BCPB_OUTPUT_NONE 0x0
#define TC_BCPB_SET_OUTPUT 0x1000000
#define TC_BCPB_CLEAR_OUTPUT 0x2000000
#define TC_BCPB_TOGGLE_OUTPUT 0x3000000
/*-------------------------------------------*/
/* Waveform Mode : RC Compare Effect on TIOB */
/*-------------------------------------------*/
#define TC_BCPC 0xC000000
#define TC_BCPC_OUTPUT_NONE 0x0
#define TC_BCPC_SET_OUTPUT 0x4000000
#define TC_BCPC_CLEAR_OUTPUT 0x8000000
#define TC_BCPC_TOGGLE_OUTPUT 0xC000000
/*-----------------------------------------------*/
/* Waveform Mode : External Event Effect on TIOB */
/*-----------------------------------------------*/
#define TC_BEEVT 0x30000000 //* bit 29-28
#define TC_BEEVT_OUTPUT_NONE 0x0
#define TC_BEEVT_SET_OUTPUT 0x10000000 //* bit 29-28 01
#define TC_BEEVT_CLEAR_OUTPUT 0x20000000 //* bit 29-28 10
#define TC_BEEVT_TOGGLE_OUTPUT 0x30000000 //* bit 29-28 11
/*- -----------------------------------------------*/
/* Waveform Mode : Software Trigger Effect on TIOB */
/*-------------------------------------------------*/
#define TC_BSWTRG 0xC0000000
#define TC_BSWTRG_OUTPUT_NONE 0x0
#define TC_BSWTRG_SET_OUTPUT 0x40000000
#define TC_BSWTRG_CLEAR_OUTPUT 0x80000000
#define TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000
/*------------------------------------------------------*/
/* TC_SR: Timer Counter Status Register Bits Definition */
/*------------------------------------------------------*/
#define TC_COVFS 0x1 /* Counter Overflow Status */
#define TC_LOVRS 0x2 /* Load Overrun Status */
#define TC_CPAS 0x4 /* RA Compare Status */
#define TC_CPBS 0x8 /* RB Compare Status */
#define TC_CPCS 0x10 /* RC Compare Status */
#define TC_LDRAS 0x20 /* RA Loading Status */
#define TC_LDRBS 0x40 /* RB Loading Status */
#define TC_ETRGS 0x80 /* External Trigger Status */
#define TC_CLKSTA 0x10000 /* Clock Status */
#define TC_MTIOA 0x20000 /* TIOA Mirror */
#define TC_MTIOB 0x40000 /* TIOB Status */
/*--------------------------------------------------------------*/
/* TC_BCR: Timer Counter Block Control Register Bits Definition */
/*--------------------------------------------------------------*/
#define TC_SYNC 0x1 /* Synchronisation Trigger */
/*------------------------------------------------------------*/
/* TC_BMR: Timer Counter Block Mode Register Bits Definition */
/*------------------------------------------------------------*/
#define TC_TC0XC0S 0x3 /* External Clock Signal 0 Selection */
#define TC_TCLK0XC0 0x0
#define TC_NONEXC0 0x1
#define TC_TIOA1XC0 0x2
#define TC_TIOA2XC0 0x3
#define TC_TC1XC1S 0xC /* External Clock Signal 1 Selection */
#define TC_TCLK1XC1 0x0
#define TC_NONEXC1 0x4
#define TC_TIOA0XC1 0x8
#define TC_TIOA2XC1 0xC
#define TC_TC2XC2S 0x30 /* External Clock Signal 2 Selection */
#define TC_TCLK2XC2 0x0
#define TC_NONEXC2 0x10
#define TC_TIOA0XC2 0x20
#define TC_TIOA1XC2 0x30
#endif /* tc_h */

151
FreeRTOS/Demo/ARM7_AT91FR40008_GCC/usart.h Normal file
View File

@ -0,0 +1,151 @@
//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : usart.h
//* Object : USART Header File.
//*
//* 1.0 01/04/00 JCZ : Creation
//*----------------------------------------------------------------------------
#ifndef usart_h
#define usart_h
//#include "periph/stdc/std_c.h"
//#include "periph/pio/lib_pio.h"
/*-------------------------------------------*/
/* USART User Interface Structure Definition */
/*-------------------------------------------*/
typedef struct
{
at91_reg US_CR ; /* Control Register */
at91_reg US_MR ; /* Mode Register */
at91_reg US_IER ; /* Interrupt Enable Register */
at91_reg US_IDR ; /* Interrupt Disable Register */
at91_reg US_IMR ; /* Interrupt Mask Register */
at91_reg US_CSR ; /* Channel Status Register */
at91_reg US_RHR ; /* Receive Holding Register */
at91_reg US_THR ; /* Transmit Holding Register */
at91_reg US_BRGR ; /* Baud Rate Generator Register */
at91_reg US_RTOR ; /* Receiver Timeout Register */
at91_reg US_TTGR ; /* Transmitter Time-guard Register */
at91_reg Reserved ;
at91_reg US_RPR ; /* Receiver Pointer Register */
at91_reg US_RCR ; /* Receiver Counter Register */
at91_reg US_TPR ; /* Transmitter Pointer Register */
at91_reg US_TCR ; /* Transmitter Counter Register */
} StructUSART ;
/*--------------------------*/
/* US_CR : Control Register */
/*--------------------------*/
#define US_RSTRX 0x0004 /* Reset Receiver */
#define US_RSTTX 0x0008 /* Reset Transmitter */
#define US_RXEN 0x0010 /* Receiver Enable */
#define US_RXDIS 0x0020 /* Receiver Disable */
#define US_TXEN 0x0040 /* Transmitter Enable */
#define US_TXDIS 0x0080 /* Transmitter Disable */
#define US_RSTSTA 0x0100 /* Reset Status Bits */
#define US_STTBRK 0x0200 /* Start Break */
#define US_STPBRK 0x0400 /* Stop Break */
#define US_STTTO 0x0800 /* Start Time-out */
#define US_SENDA 0x1000 /* Send Address */
/*-----------------------*/
/* US_MR : Mode Register */
/*-----------------------*/
#define US_CLKS 0x0030 /* Clock Selection */
#define US_CLKS_MCK 0x00 /* Master Clock */
#define US_CLKS_MCK8 0x10 /* Master Clock divided by 8 */
#define US_CLKS_SCK 0x20 /* External Clock */
#define US_CLKS_SLCK 0x30 /* Slow Clock */
#define US_CHRL 0x00C0 /* Byte Length */
#define US_CHRL_5 0x00 /* 5 bits */
#define US_CHRL_6 0x40 /* 6 bits */
#define US_CHRL_7 0x80 /* 7 bits */
#define US_CHRL_8 0xC0 /* 8 bits */
#define US_SYNC 0x0100 /* Synchronous Mode Enable */
#define US_PAR 0x0E00 /* Parity Mode */
#define US_PAR_EVEN 0x00 /* Even Parity */
#define US_PAR_ODD 0x200 /* Odd Parity */
#define US_PAR_SPACE 0x400 /* Space Parity to 0 */
#define US_PAR_MARK 0x600 /* Marked Parity to 1 */
#define US_PAR_NO 0x800 /* No Parity */
#define US_PAR_MULTIDROP 0xC00 /* Multi-drop Mode */
#define US_NBSTOP 0x3000 /* Stop Bit Number */
#define US_NBSTOP_1 0x0000 /* 1 Stop Bit */
#define US_NBSTOP_1_5 0x1000 /* 1.5 Stop Bits */
#define US_NBSTOP_2 0x2000 /* 2 Stop Bits */
#define US_CHMODE 0xC000 /* Channel Mode */
#define US_CHMODE_NORMAL 0x0000 /* Normal Mode */
#define US_CHMODE_AUTOMATIC_ECHO 0x4000 /* Automatic Echo */
#define US_CHMODE_LOCAL_LOOPBACK 0x8000 /* Local Loopback */
#define US_CHMODE_REMOTE_LOOPBACK 0xC000 /* Remote Loopback */
#define US_MODE9 0x20000 /* 9 Bit Mode */
#define US_CLKO 0x40000 /* Baud Rate Output Enable */
/* Mode Register model */
/* Standard Asynchronous Mode : 8 bits , 1 stop , no parity */
#define US_ASYNC_MODE ( US_CHMODE_NORMAL + \
US_NBSTOP_1 + \
US_PAR_NO + \
US_CHRL_8 + \
US_CLKS_MCK )
/* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */
#define US_ASYNC_SCK_MODE ( US_CHMODE_NORMAL + \
US_NBSTOP_1 + \
US_PAR_NO + \
US_CHRL_8 + \
US_CLKS_SCK )
/* Standard Synchronous Mode : 8 bits , 1 stop , no parity */
#define US_SYNC_MODE ( US_SYNC + \
US_CHMODE_NORMAL + \
US_NBSTOP_1 + \
US_PAR_NO + \
US_CHRL_8 + \
US_CLKS_MCK )
/* SCK used Label */
#define SCK_USED (US_CLKO | US_CLKS_SCK)
/*---------------------------------------------------------------*/
/* US_IER, US_IDR, US_IMR, US_IMR: Status and Interrupt Register */
/*---------------------------------------------------------------*/
#define US_RXRDY 0x1 /* Receiver Ready */
#define US_TXRDY 0x2 /* Transmitter Ready */
#define US_RXBRK 0x4 /* Receiver Break */
#define US_ENDRX 0x8 /* End of Receiver PDC Transfer */
#define US_ENDTX 0x10 /* End of Transmitter PDC Transfer */
#define US_OVRE 0x20 /* Overrun Error */
#define US_FRAME 0x40 /* Framing Error */
#define US_PARE 0x80 /* Parity Error */
#define US_TIMEOUT 0x100 /* Receiver Timeout */
#define US_TXEMPTY 0x200 /* Transmitter Empty */
#define US_MASK_IRQ_TX (US_TXRDY | US_ENDTX | US_TXEMPTY)
#define US_MASK_IRQ_RX (US_RXRDY | US_ENDRX | US_TIMEOUT)
#define US_MASK_IRQ_ERROR (US_PARE | US_FRAME | US_OVRE | US_RXBRK)
#endif /* usart_h */

75
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h Normal file
View File

@ -0,0 +1,75 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <intrinsics.h>
#include "Board.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html
-----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) 47923200 )
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configMAX_PRIORITIES ( 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) 14200 )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

76
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c Normal file
View File

@ -0,0 +1,76 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#include "FreeRTOS.h"
#include "partest.h"
#include "board.h"
/*-----------------------------------------------------------
* Simple parallel port IO routines for the LED's.
*-----------------------------------------------------------*/
const unsigned long led_mask[ NB_LED ]= { LED1, LED2, LED3, LED4 };
void vParTestInitialise( void )
{
/* Start with all LED's off. */
AT91F_PIO_SetOutput( AT91C_BASE_PIOA, LED_MASK );
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
if( uxLED < ( portBASE_TYPE ) NB_LED )
{
if( xValue )
{
AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] );
}
else
{
AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]);
}
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
if( uxLED < ( portBASE_TYPE ) NB_LED )
{
if( AT91F_PIO_GetInput( AT91C_BASE_PIOA ) & led_mask[ uxLED ] )
{
AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]);
}
else
{
AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] );
}
}
}

89
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Board.h Normal file
View File

@ -0,0 +1,89 @@
/*----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support - ROUSSET -
*----------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*----------------------------------------------------------------------------
* File Name : Board.h
* Object : AT91SAM7S Evaluation Board Features Definition File.
*
* Creation : JPP 16/Jun/2004
*----------------------------------------------------------------------------
*/
#ifndef Board_h
#define Board_h
#include "AT91SAM7S64.h"
#define __inline static inline
#include "lib_AT91SAM7S64.h"
#define true -1
#define false 0
/*-------------------------------*/
/* SAM7Board Memories Definition */
/*-------------------------------*/
// The AT91SAM7S64 embeds a 16-Kbyte SRAM bank, and 64 K-Byte Flash
#define INT_SARM 0x00200000
#define INT_SARM_REMAP 0x00000000
#define INT_FLASH 0x00000000
#define INT_FLASH_REMAP 0x01000000
#define FLASH_PAGE_NB 512
#define FLASH_PAGE_SIZE 128
/*-----------------*/
/* Leds Definition */
/*-----------------*/
/* PIO Flash PA PB PIN */
#define LED1 (1<<0) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */
#define LED2 (1<<1) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */
#define LED3 (1<<2) /* PA2 & PWM2 SCK0 44 */
#define LED4 (1<<3) /* PA3 & TWD NPCS3 43 */
#define NB_LED 4
#define LED_MASK (LED1|LED2|LED3|LED4)
/*-------------------------*/
/* Push Buttons Definition */
/*-------------------------*/
/* PIO Flash PA PB PIN */
#define SW1_MASK (1<<19) /* PA19 / PGMD7 & RK FIQ 13 */
#define SW2_MASK (1<<20) /* PA20 / PGMD8 & RF IRQ0 16 */
#define SW3_MASK (1<<15) /* PA15 / PGM3 & TF TIOA1 20 */
#define SW4_MASK (1<<14) /* PA14 / PGMD2 & SPCK PWM3 21 */
#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
#define SW1 (1<<19) // PA19
#define SW2 (1<<20) // PA20
#define SW3 (1<<15) // PA15
#define SW4 (1<<14) // PA14
/*------------------*/
/* USART Definition */
/*------------------*/
/* SUB-D 9 points J3 DBGU*/
#define DBGU_RXD AT91C_PA9_DRXD /* JP11 must be close */
#define DBGU_TXD AT91C_PA10_DTXD /* JP12 must be close */
#define AT91C_DBGU_BAUD 115200 // Baud rate
#define US_RXD_PIN AT91C_PA5_RXD0 /* JP9 must be close */
#define US_TXD_PIN AT91C_PA6_TXD0 /* JP7 must be close */
#define US_RTS_PIN AT91C_PA7_RTS0 /* JP8 must be close */
#define US_CTS_PIN AT91C_PA8_CTS0 /* JP6 must be close */
/*--------------*/
/* Master Clock */
/*--------------*/
#define EXT_OC 18432000 // Exetrnal ocilator MAINCK
#define MCK 47923200 // MCK (PLLRC div by 2)
#define MCKKHz (MCK/1000) //
#endif /* Board_h */

302
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s Normal file
View File

@ -0,0 +1,302 @@
;* ----------------------------------------------------------------------------
;* ATMEL Microcontroller Software Support - ROUSSET -
;* ----------------------------------------------------------------------------
;* Copyright (c) 2006, Atmel Corporation
;
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met:
;*
;* - Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the disclaimer below.
;*
;* - Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the disclaimer below in the documentation and/or
;* other materials provided with the distribution.
;*
;* Atmel's name may not be used to endorse or promote products derived from
;* this software without specific prior written permission.
;*
;* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
;* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
;* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
;* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
;* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
;* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;* ----------------------------------------------------------------------------
;------------------------------------------------------------------------------
; Include your AT91 Library files
;------------------------------------------------------------------------------
#include "AT91SAM7X256_inc.h"
;------------------------------------------------------------------------------
#define TOP_OF_MEMORY (AT91C_ISRAM + AT91C_ISRAM_SIZE)
#define IRQ_STACK_SIZE 200
; 3 words to be saved per interrupt priority level
; Mode, correspords to bits 0-5 in CPSR
MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR
USR_MODE DEFINE 0x10 ; User mode
FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode
IRQ_MODE DEFINE 0x12 ; Interrupt Request mode
SVC_MODE DEFINE 0x13 ; Supervisor mode
ABT_MODE DEFINE 0x17 ; Abort mode
UND_MODE DEFINE 0x1B ; Undefined Instruction mode
SYS_MODE DEFINE 0x1F ; System mode
I_BIT DEFINE 0x80
F_BIT DEFINE 0x40
;------------------------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;------------------------------------------------------------------------------
SECTION .intvec:CODE:NOROOT(2)
PUBLIC __vector
PUBLIC __iar_program_start
EXTERN vPortYieldProcessor
ARM
__vector:
ldr pc,[pc,#+24] ;; Reset
__und_handler:
ldr pc,[pc,#+24] ;; Undefined instructions
__swi_handler:
ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC)
__prefetch_handler:
ldr pc,[pc,#+24] ;; Prefetch abort
__data_handler:
ldr pc,[pc,#+24] ;; Data abort
DC32 0xFFFFFFFF ;; RESERVED
__irq_handler:
LDR PC, [PC, #-0xF20]
__fiq_handler:
ldr pc,[pc,#+24] ;; FIQ
DC32 __iar_program_start
DC32 __und_handler
DC32 vPortYieldProcessor
DC32 __prefetch_handler
DC32 __data_handler
B .
DC32 IRQ_Handler_Entry
DC32 FIQ_Handler_Entry
;------------------------------------------------------------------------------
;- Manage exception: The exception must be ensure in ARM mode
;------------------------------------------------------------------------------
SECTION text:CODE:NOROOT(2)
ARM
;------------------------------------------------------------------------------
;- Function : FIQ_Handler_Entry
;- Treatments : FIQ Controller Interrupt Handler.
;- R8 is initialize in Cstartup
;- Called Functions : None only by FIQ
;------------------------------------------------------------------------------
FIQ_Handler_Entry:
;- Switch in SVC/User Mode to allow User Stack access for C code
; because the FIQ is not yet acknowledged
;- Save and r0 in FIQ_Register
mov r9,r0
ldr r0 , [r8, #AIC_FVR]
msr CPSR_c,#I_BIT | F_BIT | SVC_MODE
;- Save scratch/used registers and LR in User Stack
stmfd sp!, { r1-r3, r12, lr}
;- Branch to the routine pointed by the AIC_FVR
mov r14, pc
bx r0
;- Restore scratch/used registers and LR from User Stack
ldmia sp!, { r1-r3, r12, lr}
;- Leave Interrupts disabled and switch back in FIQ mode
msr CPSR_c, #I_BIT | F_BIT | FIQ_MODE
;- Restore the R0 ARM_MODE_SVC register
mov r0,r9
;- Restore the Program Counter using the LR_fiq directly in the PC
subs pc,lr,#4
;------------------------------------------------------------------------------
;- Function : IRQ_Handler_Entry
;- Treatments : IRQ Controller Interrupt Handler.
;- Called Functions : AIC_IVR[interrupt]
;------------------------------------------------------------------------------
IRQ_Handler_Entry:
;-------------------------
;- Manage Exception Entry
;-------------------------
;- Adjust and save LR_irq in IRQ stack
sub lr, lr, #4
stmfd sp!, {lr}
;- Save r0 and SPSR (need to be saved for nested interrupt)
mrs r14, SPSR
stmfd sp!, {r0,r14}
;- Write in the IVR to support Protect Mode
;- No effect in Normal Mode
;- De-assert the NIRQ and clear the source in Protect Mode
ldr r14, =AT91C_BASE_AIC
ldr r0 , [r14, #AIC_IVR]
str r14, [r14, #AIC_IVR]
;- Enable Interrupt and Switch in Supervisor Mode
msr CPSR_c, #SVC_MODE
;- Save scratch/used registers and LR in User Stack
stmfd sp!, { r1-r3, r12, r14}
;----------------------------------------------
;- Branch to the routine pointed by the AIC_IVR
;----------------------------------------------
mov r14, pc
bx r0
;----------------------------------------------
;- Manage Exception Exit
;----------------------------------------------
;- Restore scratch/used registers and LR from User Stack
ldmia sp!, { r1-r3, r12, r14}
;- Disable Interrupt and switch back in IRQ mode
msr CPSR_c, #I_BIT | IRQ_MODE
;- Mark the End of Interrupt on the AIC
ldr r14, =AT91C_BASE_AIC
str r14, [r14, #AIC_EOICR]
;- Restore SPSR_irq and r0 from IRQ stack
ldmia sp!, {r0,r14}
msr SPSR_cxsf, r14
;- Restore adjusted LR_irq from IRQ stack directly in the PC
ldmia sp!, {pc}^
;------------------------------------------------------------------------------
;- Exception Vectors
;------------------------------------------------------------------------------
PUBLIC AT91F_Default_FIQ_handler
PUBLIC AT91F_Default_IRQ_handler
PUBLIC AT91F_Spurious_handler
ARM ; Always ARM mode after exeption
AT91F_Default_FIQ_handler
b AT91F_Default_FIQ_handler
AT91F_Default_IRQ_handler
b AT91F_Default_IRQ_handler
AT91F_Spurious_handler
b AT91F_Spurious_handler
;------------------------------------------------------------------------------
; ?INIT
; Program entry.
;------------------------------------------------------------------------------
SECTION FIQ_STACK:DATA:NOROOT(3)
SECTION IRQ_STACK:DATA:NOROOT(3)
SECTION SVC_STACK:DATA:NOROOT(3)
SECTION ABT_STACK:DATA:NOROOT(3)
SECTION UND_STACK:DATA:NOROOT(3)
SECTION CSTACK:DATA:NOROOT(3)
SECTION text:CODE:NOROOT(2)
REQUIRE __vector
EXTERN ?main
PUBLIC __iar_program_start
EXTERN AT91F_LowLevelInit
__iar_program_start:
;------------------------------------------------------------------------------
;- Low level Init is performed in a C function: AT91F_LowLevelInit
;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit
;------------------------------------------------------------------------------
;- Retrieve end of RAM address
ldr r13,=TOP_OF_MEMORY ;- Temporary stack in internal RAM for Low Level Init execution
ldr r0,=AT91F_LowLevelInit
mov lr, pc
bx r0 ;- Branch on C function (with interworking)
; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.
mrs r0,cpsr ; Original PSR value
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#SVC_MODE ; Set SVC mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#UND_MODE ; Set UND mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(UND_STACK) ; End of UND_STACK
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#ABT_MODE ; Set ABT mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#FIQ_MODE ; Set FIQ mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK
;- Init the FIQ register
ldr r8, =AT91C_BASE_AIC
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#IRQ_MODE ; Set IRQ mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#SYS_MODE ; Set System mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(CSTACK) ; End of CSTACK
#ifdef __ARMVFP__
; Enable the VFP coprocessor.
mov r0, #0x40000000 ; Set EN bit in VFP
fmxr fpexc, r0 ; FPEXC, clear others.
; Disable underflow exceptions by setting flush to zero mode.
; For full IEEE 754 underflow compliance this code should be removed
; and the appropriate exception handler installed.
mov r0, #0x01000000 ; Set FZ bit in VFP
fmxr fpscr, r0 ; FPSCR, clear others.
#endif
; Add more initialization here
msr CPSR_c,#I_BIT | F_BIT | SVC_MODE
; Continue to ?main for more IAR specific system startup
ldr r0,=?main
bx r0
END ;- Terminates the assembly of the last module in a file

84
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup_SAM7.c Normal file
View File

@ -0,0 +1,84 @@
//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name : Cstartup_SAM7.c
//* Object : Low level initializations written in C for IAR
//* tools
//* Creation : 12/Jun/04
//*
//*----------------------------------------------------------------------------
// Include the board file description
#include "Board.h"
// The following functions must be write in ARM mode this function called directly
// by exception vector
extern void AT91F_Spurious_handler(void);
extern void AT91F_Default_IRQ_handler(void);
extern void AT91F_Default_FIQ_handler(void);
//*----------------------------------------------------------------------------
//* \fn AT91F_LowLevelInit
//* \brief This function performs very low level HW initialization
//* this function can be use a Stack, depending the compilation
//* optimization mode
//*----------------------------------------------------------------------------
void AT91F_LowLevelInit( void );
void AT91F_LowLevelInit( void) @ "ICODE"
{
int i;
AT91PS_PMC pPMC = AT91C_BASE_PMC;
//* Set Flash Waite sate
// Single Cycle Access at Up to 30 MHz, or 40
// if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN
AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(50 <<16)) | AT91C_MC_FWS_1FWS ;
//* Watchdog Disable
AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
//* Set MCK at 47 923 200
// 1 Enabling the Main Oscillator:
// SCK = 1/32768 = 30.51 uSeconde
// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
// Wait the startup time
while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
// 2 Checking the Main Oscillator Frequency (Optional)
// 3 Setting PLL and divider:
// - div by 5 Fin = 3,6864 =(18,432 / 5)
// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
// for 96 MHz the erroe is 0.16%
// Field out NOT USED = 0
// PLLCOUNT pll startup time esrtimate at : 0.844 ms
// PLLCOUNT 28 = 0.000844 /(1/32768)
pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |
(AT91C_CKGR_PLLCOUNT & (28<<8)) |
(AT91C_CKGR_MUL & (25<<16)));
// Wait the startup time
while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
// 4. Selection of Master Clock and Processor Clock
// select the PLL clock divided by 2
pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2 ;
// Enable User Reset and set its minimal assertion to 960 us
AT91C_BASE_RSTC->RSTC_RMR = AT91C_SYSC_URSTEN | (0x4<<8) | (unsigned int) (0xA5<<24);
// Set up the default interrupts handler vectors
AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
for (i=1;i < 31; i++)
{
AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
}
AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ;
}

1268
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c Normal file
View File

File diff suppressed because it is too large Load Diff

8
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.h Normal file
View File

@ -0,0 +1,8 @@
#ifndef USB_DEMO_H
#define USB_DEMO_H
void vUSBDemoTask( void *pvParameters );
#endif

24
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/USB/USB_ISR.s79 Normal file
View File

@ -0,0 +1,24 @@
RSEG ICODE:CODE
CODE32
EXTERN vUSB_ISR
PUBLIC vUSBISREntry
; Wrapper for the USB interrupt service routine. This can cause a
; context switch so requires an assembly wrapper.
; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.
#include "ISR_Support.h"
vUSBISREntry:
portSAVE_CONTEXT ; Save the context of the current task.
bl vUSB_ISR ; Call the ISR routine.
portRESTORE_CONTEXT ; Restore the context of the current task -
; which may be different to the task that
; was interrupted.
END

247
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/main.c Normal file
View File

@ -0,0 +1,247 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks. The SAM7
* includes a sample USB that emulates a Joystick input to a USB host.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "flash.h"
#include "integer.h"
#include "PollQ.h"
#include "BlockQ.h"
#include "semtest.h"
#include "dynamic.h"
#include "partest.h"
#include "comtest2.h"
#include "USB/USBSample.h"
/* Priorities for the demo application tasks. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainUSB_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* Constants required by the 'Check' task. */
#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS )
#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS )
#define mainCHECK_TASK_LED ( 3 )
/* Constants for the ComTest tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 )
#define mainCOM_TEST_LED ( 4 ) /* Off the board. */
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Configure the processor for use with the Atmel demo board. Setup is minimal
* as the low level init function (called from the startup asm file) takes care
* of most things.
*/
static void prvSetupHardware( void );
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static long prvCheckOtherTasksAreStillRunning( void );
/*-----------------------------------------------------------*/
/*
* Starts all the other tasks, then starts the scheduler.
*/
void main( void )
{
/* Setup any hardware that has not already been configured by the low
level init routines. */
prvSetupHardware();
/* Initialise the LED outputs for use by the demo application tasks. */
vParTestInitialise();
/* Start all the standard demo application tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vStartDynamicPriorityTasks();
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
/* Also start the USB demo which is just for the SAM7. */
xTaskCreate( vUSBDemoTask, "USB", configMINIMAL_STACK_SIZE, NULL, mainUSB_PRIORITY, NULL );
/* Start the check task - which is defined in this file. */
xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Start the scheduler.
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used here. */
vTaskStartScheduler();
/* We should never get here as control is now taken by the scheduler. */
return;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* When using the JTAG debugger the hardware is not always initialised to
the correct default state. This line just ensures that this does not
cause all interrupts to be masked at the start. */
AT91C_BASE_AIC->AIC_EOICR = 0;
/* Most setup is performed by the low level init function called from the
startup asm file. */
/* Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as
well as the UART Tx line. */
AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, LED_MASK );
/* Enable the peripheral clock. */
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA );
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
/* The parameters are not used in this task. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. If an error is detected then the delay period
is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
the on board LED flash rate will increase. */
for( ;; )
{
/* Delay until it is time to execute again. */
vTaskDelay( xDelayPeriod );
/* Check all the standard demo application tasks are executing without
error. */
if( prvCheckOtherTasksAreStillRunning() != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
vParTestToggleLED( mainCHECK_TASK_LED );
}
}
/*-----------------------------------------------------------*/
static long prvCheckOtherTasksAreStillRunning( void )
{
long lReturn = ( long ) pdPASS;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none of them have detected
an error. */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
return lReturn;
}
/*-----------------------------------------------------------*/

180
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac Normal file
View File

@ -0,0 +1,180 @@
// ---------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: SAM7.mac
//
// User setup file for CSPY debugger to simulate interrupt
// driven Fibonacchi data input.
// 1.1 16/Jun/04 JPP : Creation
//
// $Revision: 1.3 $
//
// ---------------------------------------------------------
__var i;
__var pt;
execUserPreload()
{
//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
CheckRemap();
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
i=__readMemory32(0xFFFFF240,"Memory");
__message " ---------------------------------------- Chip ID 0x",i:%X;
i=__readMemory32(0xFFFFF244,"Memory");
__message " ---------------------------------------- Extention 0x",i:%X;
//* Get the chip status
//* Init AIC
AIC();
//* Watchdog Disable
Watchdog();
}
//-----------------------------------------------------------------------------
// Watchdog
//-------------------------------
// Normally, the Watchdog is enable at the reset for load it's preferable to
// Disable.
//-----------------------------------------------------------------------------
Watchdog()
{
//* Watchdog Disable
// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
__message "------------------------------- Watchdog Disable ----------------------------------------";
}
//-----------------------------------------------------------------------------
// Check Remap
//-------------
//-----------------------------------------------------------------------------
CheckRemap()
{
//* Read the value at 0x0
i=__readMemory32(0x00000000,"Memory");
i=i+1;
__writeMemory32(i,0x00,"Memory");
pt=__readMemory32(0x00000000,"Memory");
if (i == pt)
{
__message "------------------------------- The Remap is done ----------------------------------------";
//* Toggel RESET The remap
__writeMemory32(0x00000001,0xFFFFFF00,"Memory");
} else {
__message "------------------------------- The Remap is NOT -----------------------------------------";
}
}
execUserSetup()
{
ini();
__message "-------------------------------Set PC ----------------------------------------";
__writeMemory32(0x00000000,0xB4,"Register");
}
//-----------------------------------------------------------------------------
// Reset the Interrupt Controller
//-------------------------------
// Normally, the code is executed only if a reset has been actually performed.
// So, the AIC initialization resumes at setting up the default vectors.
//-----------------------------------------------------------------------------
AIC()
{
// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
__writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");
for (i=0;i < 8; i++)
{
// AT91C_BASE_AIC->AIC_EOICR
pt = __readMemory32(0xFFFFF130,"Memory");
}
__message "------------------------------- AIC INIT ---------------------------------------------";
}
ini()
{
__writeMemory32(0x0,0x00,"Register");
__writeMemory32(0x0,0x04,"Register");
__writeMemory32(0x0,0x08,"Register");
__writeMemory32(0x0,0x0C,"Register");
__writeMemory32(0x0,0x10,"Register");
__writeMemory32(0x0,0x14,"Register");
__writeMemory32(0x0,0x18,"Register");
__writeMemory32(0x0,0x1C,"Register");
__writeMemory32(0x0,0x20,"Register");
__writeMemory32(0x0,0x24,"Register");
__writeMemory32(0x0,0x28,"Register");
__writeMemory32(0x0,0x2C,"Register");
__writeMemory32(0x0,0x30,"Register");
__writeMemory32(0x0,0x34,"Register");
__writeMemory32(0x0,0x38,"Register");
// Set CPSR
__writeMemory32(0x0D3,0x98,"Register");
}
RG()
{
i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X;
i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X;
i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X;
i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X;
i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X;
i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X;
i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X;
i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X;
i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X;
i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X;
i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X;
i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X;
i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X;
i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X;
i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X;
i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X;
i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X;
i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X;
i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X;
i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X;
i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X;
i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X;
i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X;
i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X;
i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X;
i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X;
i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X;
i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X;
i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X;
i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X;
i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X;
i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X;
i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X;
i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X;
i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X;
i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X;
i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X;
i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X;
}

211
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac Normal file
View File

@ -0,0 +1,211 @@
// ---------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: SAM7_RAM.mac
//
// User setup file for CSPY debugger to simulate interrupt
// driven Fibonacchi data input.
// 1.1 16/Jun/04 JPP : Creation
// 1.2 27/Aug/04 JPP : PLL setting
//
// $Revision: 1.3 $
//
// ---------------------------------------------------------
__var i;
__var pt;
execUserPreload()
{
//*
PllSetting();
//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
CheckNoRemap();
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
i=__readMemory32(0xFFFFF240,"Memory");
__message " ---------------------------------------- Chip ID 0x",i:%X;
i=__readMemory32(0xFFFFF244,"Memory");
__message " ---------------------------------------- Extention 0x",i:%X;
i=__readMemory32(0xFFFFFF6C,"Memory");
__message " ---------------------------------------- Flash Version 0x",i:%X;
//* Get the chip status
//* Init AIC
AIC();
//* Watchdog Disable
Watchdog();
}
//-----------------------------------------------------------------------------
// PllSetting
//-------------------------------
// Set PLL
//-----------------------------------------------------------------------------
PllSetting()
{
// -1- Enabling the Main Oscillator:
//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600
// AT91C_CKGR_MOSCEN )); //0x0000 0001
__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
// -2- Wait
// -3- Setting PLL and divider:
// - div by 5 Fin = 3,6864 =(18,432 / 5)
// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
// for 96 MHz the erroe is 0.16%
// Field out NOT USED = 0
// PLLCOUNT pll startup time esrtimate at : 0.844 ms
// PLLCOUNT 28 = 0.000844 /(1/32768)
// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005
// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000
__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");
// -2- Wait
// -5- Selection of Master Clock and Processor Clock
// select the PLL clock divided by 2
// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003
// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004
__writeMemory32(0x00000007,0xFFFFFC30,"Memory");
__message "------------------------------- PLL Enable ----------------------------------------";
}
//-----------------------------------------------------------------------------
// Watchdog
//-------------------------------
// Normally, the Watchdog is enable at the reset for load it's preferable to
// Disable.
//-----------------------------------------------------------------------------
Watchdog()
{
//* Watchdog Disable
// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
__message "------------------------------- Watchdog Disable ----------------------------------------";
}
CheckNoRemap()
{
//* Read the value at 0x0
i=__readMemory32(0x00000000,"Memory");
i=i+1;
__writeMemory32(i,0x00,"Memory");
pt=__readMemory32(0x00000000,"Memory");
if (i == pt)
{
__message "------------------------------- The Remap is done ----------------------------------------";
} else {
__message "------------------------------- The Remap is NOT -----------------------------------------";
//* Toggel RESET The remap
__writeMemory32(0x00000001,0xFFFFFF00,"Memory");
}
}
execUserSetup()
{
ini();
__message "-------------------------------Set PC ----------------------------------------";
__writeMemory32(0x00000000,0xB4,"Register");
}
//-----------------------------------------------------------------------------
// Reset the Interrupt Controller
//-------------------------------
// Normally, the code is executed only if a reset has been actually performed.
// So, the AIC initialization resumes at setting up the default vectors.
//-----------------------------------------------------------------------------
AIC()
{
// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
__writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");
for (i=0;i < 8; i++)
{
// AT91C_BASE_AIC->AIC_EOICR
pt = __readMemory32(0xFFFFF130,"Memory");
}
__message "------------------------------- AIC INIT ---------------------------------------------";
}
ini()
{
__writeMemory32(0x0,0x00,"Register");
__writeMemory32(0x0,0x04,"Register");
__writeMemory32(0x0,0x08,"Register");
__writeMemory32(0x0,0x0C,"Register");
__writeMemory32(0x0,0x10,"Register");
__writeMemory32(0x0,0x14,"Register");
__writeMemory32(0x0,0x18,"Register");
__writeMemory32(0x0,0x1C,"Register");
__writeMemory32(0x0,0x20,"Register");
__writeMemory32(0x0,0x24,"Register");
__writeMemory32(0x0,0x28,"Register");
__writeMemory32(0x0,0x2C,"Register");
__writeMemory32(0x0,0x30,"Register");
__writeMemory32(0x0,0x34,"Register");
__writeMemory32(0x0,0x38,"Register");
// Set CPSR
__writeMemory32(0x0D3,0x98,"Register");
}
RG()
{
i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X;
i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X;
i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X;
i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X;
i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X;
i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X;
i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X;
i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X;
i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X;
i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X;
i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X;
i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X;
i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X;
i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X;
i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X;
i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X;
i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X;
i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X;
i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X;
i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X;
i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X;
i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X;
i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X;
i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X;
i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X;
i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X;
i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X;
i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X;
i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X;
i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X;
i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X;
i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X;
i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X;
i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X;
i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X;
i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X;
i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X;
i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X;
}

43
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_FLASH.icf Normal file
View File

@ -0,0 +1,43 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00100000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00100040;
define symbol __ICFEDIT_region_ROM_end__ = 0x10FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x200000;
define symbol __ICFEDIT_region_RAM_end__ = 0x203FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_svcstack__ = 0x100;
define symbol __ICFEDIT_size_irqstack__ = 0x100;
define symbol __ICFEDIT_size_fiqstack__ = 0x0;
define symbol __ICFEDIT_size_undstack__ = 0x0;
define symbol __ICFEDIT_size_abtstack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x0;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP };

73
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/resource/at91sam7s-ek-flash.mac Normal file
View File

@ -0,0 +1,73 @@
// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : SAM7_FLASH.mac
// Object : Generic Macro File for IAR
// 1.0 17/Aug/05 FBr : Creation
// ----------------------------------------------------------------------------
/*********************************************************************
*
* _InitRSTC()
*
* Function description
* Initializes the RSTC (Reset controller).
* This makes sense since the default is to not allow user resets, which makes it impossible to
* apply a second RESET via J-Link
*/
_InitRSTC() {
__writeMemory32(0xA5000001, 0xFFFFFD08,"Memory"); // Allow user reset
}
/*********************************************************************
*
* _InitPLL()
* Function description
* Initializes the PMC.
* 1. Enable the Main Oscillator
* 2. Configure PLL to 96MHz
* 3. Switch Master Clock (MCK) on PLL/2 = 48MHz
*/
_InitPLL() {
__message "Enable Main Oscillator";
__writeMemory32(0x00000601,0xFFFFFc20,"Memory"); // MOSC
while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x1) );
__message "Set PLL to 96MHz";
__writeMemory32(0x10191c05,0xFFFFFc2c,"Memory"); // LOCK
while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x4) );
__message "Set Master Clock to 48MHz";
__writeMemory32(0x00000004,0xFFFFFc30,"Memory"); // MCKRDY
while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x8) );
__writeMemory32(0x00000007,0xFFFFFc30,"Memory"); // MCKRDY
while( !(__readMemory32(0xFFFFFc68,"Memory") & 0x8) );
// Set 1 WS for Flash accesses on each EFC
__writeMemory32(0x00480100,0xFFFFFF60,"Memory");
__writeMemory32(0x00480100,0xFFFFFF70,"Memory");
}
/*********************************************************************
*
* execUserReset() : JTAG set initially to Full Speed
*/
execUserReset() {
__message "execUserReset()";
__hwReset(0); // Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
_InitPLL(); // Allow to debug at JTAG Full Speed
_InitRSTC(); // Enable User Reset to allow execUserReset() execution
}

12
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/resource/at91sam7s64-flash.board Normal file
View File

@ -0,0 +1,12 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<flash_board>
<pass>
<loader>$TOOLKIT_DIR$\config\flashloader\Atmel\AT91SAM7S64-EK\flash-at91sam7s64.flash</loader>
<range>CODE 0x100000 0x110000</range>
<rel_offset>0</rel_offset>
<args>--flash
--boot
</args>
</pass>
</flash_board>

1387
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd Normal file
View File

File diff suppressed because it is too large Load Diff

1670
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp Normal file
View File

File diff suppressed because it is too large Load Diff

10
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.eww Normal file
View File

@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\rtosdemo.ewp</path>
</project>
<batchBuild/>
</workspace>

241
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c Normal file
View File

@ -0,0 +1,241 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Location of the COM0 registers. */
#define serCOM0 ( ( AT91PS_USART ) AT91C_BASE_US0 )
/* Interrupt control macros. */
#define serINTERRUPT_LEVEL ( 5 )
#define vInterruptOn() AT91F_US_EnableIt( serCOM0, AT91C_US_TXRDY | AT91C_US_RXRDY )
#define vInterruptOff() AT91F_US_DisableIt( serCOM0, AT91C_US_TXRDY )
/* Misc constants. */
#define serINVALID_QUEUE ( ( QueueHandle_t ) 0 )
#define serHANDLE ( ( xComPortHandle ) 1 )
#define serNO_BLOCK ( ( TickType_t ) 0 )
#define serNO_TIMEGUARD ( ( unsigned long ) 0 )
#define serNO_PERIPHERAL_B_SETUP ( ( unsigned long ) 0 )
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static QueueHandle_t xRxedChars;
static QueueHandle_t xCharsForTx;
/*-----------------------------------------------------------*/
/* Interrupt entry point written in the assembler file serialISR.s79. */
extern void vSerialISREntry( void );
/* The interrupt service routine - called from the assembly entry point. */
__arm void vSerialISR( void );
/*-----------------------------------------------------------*/
/*
* See the serial2.h header file.
*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
xComPortHandle xReturn = serHANDLE;
extern void ( vUART_ISR )( void );
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
/* If the queues were created correctly then setup the serial port
hardware. */
if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
{
portENTER_CRITICAL();
{
/* Enable the USART clock. */
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_US0 );
AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, ( ( unsigned long ) AT91C_PA5_RXD0 ) | ( ( unsigned long ) AT91C_PA6_TXD0 ), serNO_PERIPHERAL_B_SETUP );
/* Set the required protocol. */
AT91F_US_Configure( serCOM0, configCPU_CLOCK_HZ, AT91C_US_ASYNC_MODE, ulWantedBaud, serNO_TIMEGUARD );
/* Enable Rx and Tx. */
serCOM0->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
/* Enable the Rx interrupts. The Tx interrupts are not enabled
until there are characters to be transmitted. */
AT91F_US_EnableIt( serCOM0, AT91C_US_RXRDY );
/* Enable the interrupts in the AIC. */
AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_US0, serINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)( void ) ) vSerialISREntry );
AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_US0 );
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
/* This demo file only supports a single port but we have to return
something to comply with the standard demo header file. */
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
{
/* The port handle is not required as this driver only supports one port. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
{
signed char *pxNext;
/* A couple of parameters that this port does not use. */
( void ) usStringLength;
( void ) pxPort;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
/* Send each character in the string, one at a time. */
pxNext = ( signed char * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
{
/* Place the character in the queue of characters to be transmitted. */
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
{
return pdFAIL;
}
/* Turn on the Tx interrupt so the ISR will remove the character from the
queue and send it. This does not need to be in a critical section as
if the interrupt has already removed the character the next interrupt
will simply turn off the Tx interrupt again. */
vInterruptOn();
return pdPASS;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
}
/*-----------------------------------------------------------*/
/* Serial port ISR. This can cause a context switch so is not defined as a
standard ISR using the __irq keyword. Instead a wrapper function is defined
within serialISR.s79 which in turn calls this function. See the port
documentation on the FreeRTOS.org website for more information. */
__arm void vSerialISR( void )
{
unsigned long ulStatus;
signed char cChar;
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
/* What caused the interrupt? */
ulStatus = serCOM0->US_CSR &= serCOM0->US_IMR;
if( ulStatus & AT91C_US_TXRDY )
{
/* The interrupt was caused by the THR becoming empty. Are there any
more characters to transmit? */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
{
/* A character was retrieved from the queue so can be sent to the
THR now. */
serCOM0->US_THR = cChar;
}
else
{
/* Queue empty, nothing to send so turn off the Tx interrupt. */
vInterruptOff();
}
}
if( ulStatus & AT91C_US_RXRDY )
{
/* The interrupt was caused by a character being received. Grab the
character from the RHR and place it in the queue or received
characters. */
cChar = serCOM0->US_RHR;
xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
}
/* If a task was woken by either a character being received or a character
being transmitted then we may need to switch to another task. */
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
/* End the interrupt in the AIC. */
AT91C_BASE_AIC->AIC_EOICR = 0;
}

24
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/serial/serialISR.s79 Normal file
View File

@ -0,0 +1,24 @@
RSEG ICODE:CODE
CODE32
EXTERN vSerialISR
PUBLIC vSerialISREntry
; Wrapper for the serial port interrupt service routine. This can cause a
; context switch so requires an assembly wrapper.
; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.
#include "ISR_Support.h"
vSerialISREntry:
portSAVE_CONTEXT ; Save the context of the current task.
bl vSerialISR ; Call the ISR routine.
portRESTORE_CONTEXT ; Restore the context of the current task -
; which may be different to the task that
; was interrupted.
END

71
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dbgdt Normal file
View File

@ -0,0 +1,71 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<Project>
<Desktop>
<Static>
<Workspace>
<ColumnWidths>
<Column0>189</Column0><Column1>27</Column1><Column2>27</Column2></ColumnWidths>
</Workspace>
<Disassembly>
<PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly>
<Debug-Log/>
<Build/>
<Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register><QWatch><Column0>188</Column0><Column1>171</Column1><Column2>100</Column2><Column3>100</Column3></QWatch><Memory><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory><Watch><Format><struct_types/><watch_formats/></Format></Watch></Static>
<Windows>
<Wnd0>
<Tabs>
<Tab>
<Identity>TabID-23416-30482</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>rtosdemo</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd0>
<Wnd2>
<Tabs>
<Tab>
<Identity>TabID-12145-30489</Identity>
<TabName>Debug Log</TabName>
<Factory>Debug-Log</Factory>
<Session/>
</Tab>
<Tab>
<Identity>TabID-22894-30492</Identity>
<TabName>Build</TabName>
<Factory>Build</Factory>
<Session/>
</Tab>
</Tabs>
<SelectedTab>1</SelectedTab></Wnd2>
<Wnd4><Tabs><Tab><Identity>TabID-18780-12821</Identity><TabName>Memory</TabName><Factory>Memory</Factory><Session><SelectionAnchor>2097764</SelectionAnchor><SelectionEnd>2097764</SelectionEnd><UnitsPerGroup>1</UnitsPerGroup><EndianMode>0</EndianMode><DataCovEnabled>0</DataCovEnabled><DataCovShown>0</DataCovShown></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd4><Wnd5><Tabs><Tab><Identity>TabID-23506-14575</Identity><TabName>Watch</TabName><Factory>Watch</Factory><Session><Expressions><Expression><Expression>pxCurrentTCB</Expression></Expression><Expression><Expression>ulCriticalNesting</Expression></Expression></Expressions><TabId>0</TabId><Column0>176</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd5><Wnd1><Tabs><Tab><Identity>TabID-4859-22480</Identity><TabName>Disassembly</TabName><Factory>Disassembly</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1><Wnd3><Tabs><Tab><Identity>TabID-154-22568</Identity><TabName>Register</TabName><Factory>Register</Factory><Session><REG1>0</REG1><REG2>0</REG2><Group>0</Group><States>1</States><State0>CPSR</State0></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>
<Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\main.c</Filename><XPos>0</XPos><YPos>10</YPos><SelStart>378</SelStart><SelEnd>378</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\source\include\task.h</Filename><XPos>0</XPos><YPos>778</YPos><SelStart>24283</SelStart><SelEnd>24283</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\tasks.c</Filename><XPos>0</XPos><YPos>939</YPos><SelStart>30511</SelStart><SelEnd>30511</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\SrcIAR\Cstartup.s79</Filename><XPos>0</XPos><YPos>48</YPos><SelStart>2226</SelStart><SelEnd>2226</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\Common\Minimal\flash.c</Filename><XPos>0</XPos><YPos>98</YPos><SelStart>4025</SelStart><SelEnd>4025</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portasm.s79</Filename><XPos>0</XPos><YPos>41</YPos><SelStart>1057</SelStart><SelEnd>1079</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\srciar\lib_AT91SAM7S64.h</Filename><XPos>0</XPos><YPos>2778</YPos><SelStart>108450</SelStart><SelEnd>108450</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c</Filename><XPos>0</XPos><YPos>136</YPos><SelStart>5326</SelStart><SelEnd>5326</SelEnd></Tab><ActiveTab>7</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\ParTest\ParTest.c</Filename><XPos>0</XPos><YPos>36</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portmacro.h</Filename><XPos>0</XPos><YPos>67</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-0084f8a0><key>IarIdePM1</key></Toolbar-0084f8a0></Sizes></Row0><Row1><Sizes><Toolbar-031ef990><key>DebuggerGui1</key></Toolbar-031ef990></Sizes></Row1></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>715</Bottom><Right>263</Right><x>-2</x><y>-2</y><xscreen>153</xscreen><yscreen>153</yscreen><sizeHorzCX>95625</sizeHorzCX><sizeHorzCY>136729</sizeHorzCY><sizeVertCX>165625</sizeVertCX><sizeVertCY>640750</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>715</Bottom><Right>647</Right><x>-2</x><y>-2</y><xscreen>190</xscreen><yscreen>190</yscreen><sizeHorzCX>118750</sizeHorzCX><sizeHorzCY>169794</sizeHorzCY><sizeVertCX>405625</sizeVertCX><sizeVertCY>640750</sizeVertCY></Rect></Wnd1></Sizes></Row0><Row1><Sizes><Wnd3><Rect><Top>-2</Top><Left>645</Left><Bottom>715</Bottom><Right>1025</Right><x>645</x><y>-2</y><xscreen>190</xscreen><yscreen>190</yscreen><sizeHorzCX>118750</sizeHorzCX><sizeHorzCY>169794</sizeHorzCY><sizeVertCX>237500</sizeVertCX><sizeVertCY>640750</sizeVertCY></Rect></Wnd3></Sizes></Row1></Right><Bottom><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>151</Bottom><Right>1602</Right><x>-2</x><y>-2</y><xscreen>1604</xscreen><yscreen>153</yscreen><sizeHorzCX>1002500</sizeHorzCX><sizeHorzCY>136729</sizeHorzCY><sizeVertCX>95625</sizeVertCX><sizeVertCY>136729</sizeVertCY></Rect></Wnd2></Sizes></Row0><Row1><Sizes><Wnd4><Rect><Top>149</Top><Left>-2</Left><Bottom>333</Bottom><Right>669</Right><x>-2</x><y>149</y><xscreen>671</xscreen><yscreen>184</yscreen><sizeHorzCX>419375</sizeHorzCX><sizeHorzCY>164432</sizeHorzCY><sizeVertCX>114375</sizeVertCX><sizeVertCY>163538</sizeVertCY></Rect></Wnd4><Wnd5><Rect><Top>149</Top><Left>667</Left><Bottom>333</Bottom><Right>1602</Right><x>667</x><y>149</y><xscreen>935</xscreen><yscreen>184</yscreen><sizeHorzCX>584375</sizeHorzCX><sizeHorzCY>164432</sizeHorzCY><sizeVertCX>115000</sizeVertCX><sizeVertCY>598748</sizeVertCY></Rect></Wnd5></Sizes></Row1></Bot
tom><Float><Sizes/></Float></Positions>
</Desktop>
</Project>

23
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dni Normal file
View File

@ -0,0 +1,23 @@
[DisAssemblyWindow]
NumStates=_ 1
State 1=_ 1
[JLinkDriver]
WatchVectorCatch=_ 0
WatchCond=_ 0
Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
[Log file]
LoggingEnabled=_ 0
LogFile=_ ""
Category=_ 0
[TermIOLog]
LoggingEnabled=_ 0
LogFile=_ ""
[Disassemble mode]
mode=0
[Breakpoints]
Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c}.141.1@1" 1 0 0 0 "" 0 ""
Count=1
[Low Level]
Pipeline mode=0
Initialized=0

80
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/settings/BasicSAM7.wsdt Normal file
View File

@ -0,0 +1,80 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<Workspace>
<ConfigDictionary>
<CurrentConfigs><Project>rtosdemo/Flash Debug</Project></CurrentConfigs></ConfigDictionary>
<Desktop>
<Static>
<Workspace>
<ColumnWidths>
<Column0>232</Column0><Column1>27</Column1><Column2>27</Column2></ColumnWidths>
</Workspace>
<Build/>
<TerminalIO/>
<Profiling/>
<Watch>
<Format>
<struct_types/>
<watch_formats/>
</Format>
</Watch>
<Debug-Log/>
<Disassembly>
<MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly>
<CodeCoveragePlugin/><Memory><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory></Static>
<Windows>
<Wnd6>
<Tabs>
<Tab>
<Identity>TabID-29690-30365</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>rtosdemo</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd6><Wnd7>
<Tabs>
<Tab>
<Identity>TabID-27076-30414</Identity>
<TabName>Build</TabName>
<Factory>Build</Factory>
<Session/>
</Tab>
<Tab>
<Identity>TabID-12668-30479</Identity>
<TabName>Debug Log</TabName>
<Factory>Debug-Log</Factory>
<Session/>
</Tab>
</Tabs>
<SelectedTab>1</SelectedTab></Wnd7></Windows>
<Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\source\include\task.h</Filename><XPos>0</XPos><YPos>778</YPos><SelStart>24283</SelStart><SelEnd>24283</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portasm.s79</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>2583</SelStart><SelEnd>2583</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\SrcIAR\Cstartup.s79</Filename><XPos>0</XPos><YPos>30</YPos><SelStart>2226</SelStart><SelEnd>2226</SelEnd></Tab><ActiveTab>3</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\srciar\lib_AT91SAM7S64.h</Filename><XPos>0</XPos><YPos>2371</YPos><SelStart>92638</SelStart><SelEnd>92638</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\Common\Minimal\flash.c</Filename><XPos>0</XPos><YPos>98</YPos><SelStart>4025</SelStart><SelEnd>4025</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c</Filename><XPos>0</XPos><YPos>177</YPos><SelStart>7662</SelStart><SelEnd>7662</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\ParTest\ParTest.c</Filename><XPos>0</XPos><YPos>36</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portmacro.h</Filename><XPos>0</XPos><YPos>21</YPos><SelStart>2110</SelStart><SelEnd>2110</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\SrcIAR\Cstartup_SAM7.c</Filename><XPos>0</XPos><YPos>29</YPos><SelStart>3116</SelStart><SelEnd>3116</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\MemMang\heap_2.c</Filename><XPos>0</XPos><YPos>170</YPos><SelStart>7352</SelStart><SelEnd>7352</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\tasks.c</Filename><XPos>0</XPos><YPos>1270</YPos><SelStart>40884</SelStart><SelEnd>40884</SelEnd></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-0084f7c0><key>IarIdePM1</key></Toolbar-0084f7c0></Sizes></Row0></Top><Left><Row0><Sizes><Wnd6><Rect><Top>-2</Top><Left>-2</Left><Bottom>866</Bottom><Right>306</Right><x>-2</x><y>-2</y><xscreen>48</xscreen><yscreen>48</yscreen><sizeHorzCX>30000</sizeHorzCX><sizeHorzCY>42895</sizeHorzCY><sizeVertCX>192500</sizeVertCX><sizeVertCY>775692</sizeVertCY></Rect></Wnd6></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd7><Rect><Top>-2</Top><Left>-2</Left><Bottom>206</Bottom><Right>1602</Right><x>-2</x><y>-2</y><xscreen>1604</xscreen><yscreen>208</yscreen><sizeHorzCX>1002500</sizeHorzCX><sizeHorzCY>185880</sizeHorzCY><sizeVertCX>30000</sizeVertCX><sizeVertCY>42895</sizeVertCY></Rect></Wnd7></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Workspace>

62
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dbgdt Normal file
View File

@ -0,0 +1,62 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<Project>
<Desktop>
<Static>
<Workspace>
<ColumnWidths>
<Column0>204</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Disassembly>
<PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly>
<Debug-Log><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Build</Factory></Window></Windows></PreferedWindows><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>
<Build><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window></Windows></PreferedWindows></Build>
<Register>
<PreferedWindows>
<Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows>
</Register>
<QWatch><Column0>161</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></QWatch><Memory><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory></Static>
<Windows>
<Wnd0>
<Tabs>
<Tab>
<Identity>TabID-22256-14845</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>rtosdemo</ExpandedNode><ExpandedNode>rtosdemo/USBSample.c</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd0><Wnd1><Tabs><Tab><Identity>TabID-18517-20319</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1></Windows>
<Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy\Demo\ARM7_AT91SAM7S64_IAR\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>880</SelStart><SelEnd>880</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\temp\rc\1\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Cstartup.s</Filename><XPos>0</XPos><YPos>213</YPos><SelStart>8773</SelStart><SelEnd>8773</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\temp\rc\1\FreeRTOS\Source\portable\IAR\AtmelSAM7S64\AT91SAM7S64.h</Filename><XPos>0</XPos><YPos>18</YPos><SelStart>2080</SelStart><SelEnd>2080</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\temp\rc\1\FreeRTOS\Source\portable\IAR\AtmelSAM7S64\port.c</Filename><XPos>0</XPos><YPos>234</YPos><SelStart>9960</SelStart><SelEnd>9960</SelEnd></Tab><ActiveTab>3</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-00abb198><key>iaridepm.enu1</key></Toolbar-00abb198><Toolbar-049f1f30><key>debuggergui.enu1</key></Toolbar-049f1f30></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>278</Right><x>-2</x><y>-2</y><xscreen>0</xscreen><yscreen>0</yscreen><sizeHorzCX>0</sizeHorzCX><sizeHorzCY>0</sizeHorzCY><sizeVertCX>166667</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Project>

47
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni Normal file
View File

@ -0,0 +1,47 @@
[DisAssemblyWindow]
NumStates=_ 1
State 1=_ 1
[JLinkDriver]
WatchVectorCatch=_ 0
WatchCond=_ 0
Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
[Low Level]
Pipeline mode=1
Initialized=0
[CodeCoverage]
Enabled=_ 0
[Profiling]
Enabled=0
[StackPlugin]
Enabled=1
OverflowWarningsEnabled=1
WarningThreshold=90
SpWarningsEnabled=1
WarnHow=0
UseTrigger=1
TriggerName=main
LimitSize=0
ByteLimit=50
[TraceHelper]
Enabled=0
ShowSource=1
[DebugChecksum]
Checksum=-1701609349
[InstructionProfiling]
Enabled=_ 0
[Log file]
LoggingEnabled=_ 0
LogFile=_ ""
Category=_ 0
[TermIOLog]
LoggingEnabled=_ 0
LogFile=_ ""
[DriverProfiling]
Enabled=0
Source=2
Graph=0
[Disassemble mode]
mode=0
[Breakpoints]
Count=0

76
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt Normal file
View File

@ -0,0 +1,76 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<Workspace>
<ConfigDictionary>
<CurrentConfigs><Project>rtosdemo/Flash Debug</Project></CurrentConfigs></ConfigDictionary>
<Desktop>
<Static>
<Workspace>
<ColumnWidths>
<Column0>236</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Build><ColumnWidth0>18</ColumnWidth0><ColumnWidth1>1155</ColumnWidth1><ColumnWidth2>308</ColumnWidth2><ColumnWidth3>77</ColumnWidth3></Build>
<Debug-Log/>
<TerminalIO/>
<CodeCoveragePlugin/>
<Profiling/>
<Watch>
<Format>
<struct_types/>
<watch_formats/>
</Format>
</Watch>
<Disassembly><MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly><Memory><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory></Static>
<Windows>
<Wnd2>
<Tabs>
<Tab>
<Identity>TabID-17425-14382</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>rtosdemo</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd2><Wnd3>
<Tabs>
<Tab>
<Identity>TabID-4084-16269</Identity>
<TabName>Build</TabName>
<Factory>Build</Factory>
<Session/>
</Tab>
<Tab>
<Identity>TabID-25581-16276</Identity>
<TabName>Debug Log</TabName>
<Factory>Debug-Log</Factory>
<Session/>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd3></Windows>
<Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy\Demo\ARM7_AT91SAM7S64_IAR\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>880</SelStart><SelEnd>880</SelEnd></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-00abb198><key>iaridepm.enu1</key></Toolbar-00abb198></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>576</Bottom><Right>310</Right><x>-2</x><y>-2</y><xscreen>32</xscreen><yscreen>26</yscreen><sizeHorzCX>19048</sizeHorzCX><sizeHorzCY>26477</sizeHorzCY><sizeVertCX>185714</sizeVertCX><sizeVertCY>588595</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>362</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>364</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>370672</sizeHorzCY><sizeVertCX>19048</sizeVertCX><sizeVertCY>26477</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Workspace>

17
FreeRTOS/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo_lnk.par Normal file
View File

@ -0,0 +1,17 @@
// IAR XLINK Setup
// Autogenerated file - do not edit
%
setrangelist($evec_ADR,[0-3F]);
setrangelist($internal_ROM,[8000-FFFFF]);
setrangelist($external_ROM,[]);
setrangelist($internal_RAM,[100000-7FFFFF]);
setrangelist($external_RAM,[]);
$CSTACK_SIZE=200;
$IRQSTACK_SIZE=100;
$HEAP_SIZE=4;
$COMMANDS="";
$STACK_LOCATION="Internal RAM";
$IRQSTACK_LOCATION="Internal RAM";
$HEAP_LOCATION="Internal RAM";
$iar_saved_xclfilename="E:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\resource\at91SAM7S64_NoRemap.xcl";
%

3
FreeRTOS/Demo/ARM7_AT91SAM7X256_Eclipse/ReadMe.txt Normal file
View File

@ -0,0 +1,3 @@
If you need the demo that used to be in this directory then download FreeRTOS V8.2.3
from http://sourceforge.net/projects/freertos/files/FreeRTOS/

76
FreeRTOS/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h Normal file
View File

@ -0,0 +1,76 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <lpc210x.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configMAX_PRIORITIES ( 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 128 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 24 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configQUEUE_REGISTRY_SIZE 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

112
FreeRTOS/Demo/ARM7_LPC2106_GCC/Makefile Normal file
View File

@ -0,0 +1,112 @@
#/*
# * FreeRTOS V202111.00
# * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
# *
# * Permission is hereby granted, free of charge, to any person obtaining a copy of
# * this software and associated documentation files (the "Software"), to deal in
# * the Software without restriction, including without limitation the rights to
# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
# * the Software, and to permit persons to whom the Software is furnished to do so,
# * subject to the following conditions:
# *
# * The above copyright notice and this permission notice shall be included in all
# * copies or substantial portions of the Software.
# *
# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# *
# * http://www.FreeRTOS.org
# * http://aws.amazon.com/freertos
# *
# * 1 tab == 4 spaces!
# */
CC=arm-elf-gcc
OBJCOPY=arm-elf-objcopy
ARCH=arm-elf-ar
CRT0=boot.s
WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \
-Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused
#
# CFLAGS common to both the THUMB and ARM mode builds
#
CFLAGS=$(WARNINGS) -D $(RUN_MODE) -D GCC_ARM7 -I. -I../../Source/include \
-I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \
$(OPTIM) -fomit-frame-pointer -fno-strict-aliasing -fno-dwarf2-cfi-asm
ifeq ($(USE_THUMB_MODE),YES)
CFLAGS += -mthumb-interwork -D THUMB_INTERWORK
THUMB_FLAGS=-mthumb
endif
LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map
RTOS_SOURCE_DIR=../../Source
DEMO_SOURCE_DIR=../Common/Minimal
#
# Source files that can be built to THUMB mode.
#
THUMB_SRC = \
main.c \
serial/serial.c \
ParTest/ParTest.c \
$(DEMO_SOURCE_DIR)/integer.c \
$(DEMO_SOURCE_DIR)/flash.c \
$(DEMO_SOURCE_DIR)/PollQ.c \
$(DEMO_SOURCE_DIR)/comtest.c \
$(DEMO_SOURCE_DIR)/flop.c \
$(DEMO_SOURCE_DIR)/semtest.c \
$(DEMO_SOURCE_DIR)/dynamic.c \
$(DEMO_SOURCE_DIR)/BlockQ.c \
$(RTOS_SOURCE_DIR)/tasks.c \
$(RTOS_SOURCE_DIR)/queue.c \
$(RTOS_SOURCE_DIR)/list.c \
$(RTOS_SOURCE_DIR)/portable/MemMang/heap_2.c \
$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/port.c
#
# Source files that must be built to ARM mode.
#
ARM_SRC = \
$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/portISR.c \
serial/serialISR.c
#
# Define all object files.
#
ARM_OBJ = $(ARM_SRC:.c=.o)
THUMB_OBJ = $(THUMB_SRC:.c=.o)
rtosdemo.hex : rtosdemo.elf
$(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex
rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile
$(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)
$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
$(CC) -c $(CFLAGS) $< -o $@
clean :
rm -rf $(ARM_OBJ) $(THUMB_OBJ)
touch Makefile

101
FreeRTOS/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c Normal file
View File

@ -0,0 +1,101 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
Changes from V2.5.2
+ All LED's are turned off to start.
*/
#include "FreeRTOS.h"
#include "partest.h"
#define partstFIRST_IO ( ( unsigned long ) 0x400 )
#define partstNUM_LEDS ( 4 )
#define partstALL_OUTPUTS_OFF ( ( unsigned long ) 0xffffffff )
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* This is performed from main() as the io bits are shared with other setup
functions. */
/* Turn all outputs off. */
GPIO_IOSET = partstALL_OUTPUTS_OFF;
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned long ulLED = partstFIRST_IO;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED
attached. */
ulLED <<= ( unsigned long ) uxLED;
/* Set of clear the output. */
if( xValue )
{
GPIO_IOCLR = ulLED;
}
else
{
GPIO_IOSET = ulLED;
}
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned long ulLED = partstFIRST_IO, ulCurrentState;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED
attached. */
ulLED <<= ( unsigned long ) uxLED;
/* If this bit is already set, clear it, and vice versa. */
ulCurrentState = GPIO0_IOPIN;
if( ulCurrentState & ulLED )
{
GPIO_IOCLR = ulLED;
}
else
{
GPIO_IOSET = ulLED;
}
}
}

157
FreeRTOS/Demo/ARM7_LPC2106_GCC/boot.s Normal file
View File

@ -0,0 +1,157 @@
/* Sample initialization file */
.extern main
.extern exit
.text
.code 32
.align 0
.extern __bss_beg__
.extern __bss_end__
.extern __stack_end__
.extern __data_beg__
.extern __data_end__
.extern __data+beg_src__
.global start
.global endless_loop
/* Stack Sizes */
.set UND_STACK_SIZE, 0x00000004
.set ABT_STACK_SIZE, 0x00000004
.set FIQ_STACK_SIZE, 0x00000004
.set IRQ_STACK_SIZE, 0X00000400
.set SVC_STACK_SIZE, 0x00000400
/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
.set MODE_USR, 0x10 /* User Mode */
.set MODE_FIQ, 0x11 /* FIQ Mode */
.set MODE_IRQ, 0x12 /* IRQ Mode */
.set MODE_SVC, 0x13 /* Supervisor Mode */
.set MODE_ABT, 0x17 /* Abort Mode */
.set MODE_UND, 0x1B /* Undefined Mode */
.set MODE_SYS, 0x1F /* System Mode */
.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
start:
_start:
_mainCRTStartup:
/* Setup a stack for each mode - note that this only sets up a usable stack
for system/user, SWI and IRQ modes. Also each mode is setup with
interrupts initially disabled. */
ldr r0, .LC6
msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
mov sp, r0
sub r0, r0, #UND_STACK_SIZE
msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
mov sp, r0
sub r0, r0, #ABT_STACK_SIZE
msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
mov sp, r0
sub r0, r0, #FIQ_STACK_SIZE
msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
mov sp, r0
sub r0, r0, #IRQ_STACK_SIZE
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
mov sp, r0
sub r0, r0, #SVC_STACK_SIZE
msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
mov sp, r0
/* We want to start in supervisor mode. Operation will switch to system
mode when the first task starts. */
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT
/* Clear BSS. */
mov a2, #0 /* Fill value */
mov fp, a2 /* Null frame pointer */
mov r7, a2 /* Null frame pointer for Thumb */
ldr r1, .LC1 /* Start of memory block */
ldr r3, .LC2 /* End of memory block */
subs r3, r3, r1 /* Length of block */
beq .end_clear_loop
mov r2, #0
.clear_loop:
strb r2, [r1], #1
subs r3, r3, #1
bgt .clear_loop
.end_clear_loop:
/* Initialise data. */
ldr r1, .LC3 /* Start of memory block */
ldr r2, .LC4 /* End of memory block */
ldr r3, .LC5
subs r3, r3, r1 /* Length of block */
beq .end_set_loop
.set_loop:
ldrb r4, [r2], #1
strb r4, [r1], #1
subs r3, r3, #1
bgt .set_loop
.end_set_loop:
mov r0, #0 /* no arguments */
mov r1, #0 /* no argv either */
bl main
endless_loop:
b endless_loop
.align 0
.LC1:
.word __bss_beg__
.LC2:
.word __bss_end__
.LC3:
.word __data_beg__
.LC4:
.word __data_beg_src__
.LC5:
.word __data_end__
.LC6:
.word __stack_end__
/* Setup vector table. Note that undf, pabt, dabt, fiq just execute
a null loop. */
.section .startup,"ax"
.code 32
.align 0
b _start /* reset - _start */
ldr pc, _undf /* undefined - _undf */
ldr pc, _swi /* SWI - _swi */
ldr pc, _pabt /* program abort - _pabt */
ldr pc, _dabt /* data abort - _dabt */
nop /* reserved */
ldr pc, [pc,#-0xFF0] /* IRQ - read the VIC */
ldr pc, _fiq /* FIQ - _fiq */
_undf: .word __undf /* undefined */
_swi: .word vPortYieldProcessor /* SWI */
_pabt: .word __pabt /* program abort */
_dabt: .word __dabt /* data abort */
_fiq: .word __fiq /* FIQ */
__undf: b . /* undefined */
__pabt: b . /* program abort */
__dabt: b . /* data abort */
__fiq: b . /* FIQ */

55
FreeRTOS/Demo/ARM7_LPC2106_GCC/lpc2106-ram.ld Normal file
View File

@ -0,0 +1,55 @@
MEMORY
{
flash : ORIGIN = 0, LENGTH = 120K
ram : ORIGIN = 0x40000000, LENGTH = 64K
}
__stack_end__ = 0x40000000 + 64K - 4;
SECTIONS
{
. = 0;
startup : { *(.startup)} >ram
prog :
{
*(.text)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
} >ram
__end_of_text__ = .;
.data :
{
__data_beg__ = .;
__data_beg_src__ = __end_of_text__;
*(.data)
__data_end__ = .;
} >ram
.bss :
{
__bss_beg__ = .;
*(.bss)
} >ram
. = ALIGN(4);
.eh_frame :
{
KEEP (*(.eh_frame))
} > ram
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
}
. = ALIGN(32 / 8);
_end = .;
_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
PROVIDE (end = .);

55
FreeRTOS/Demo/ARM7_LPC2106_GCC/lpc2106-rom.ld Normal file
View File

@ -0,0 +1,55 @@
MEMORY
{
flash : ORIGIN = 0, LENGTH = 120K
ram : ORIGIN = 0x40000000, LENGTH = 64K
}
__stack_end__ = 0x40000000 + 64K - 4;
SECTIONS
{
. = 0;
startup : { *(.startup)} >flash
prog :
{
*(.text)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
} >flash
__end_of_text__ = .;
.data :
{
__data_beg__ = .;
__data_beg_src__ = __end_of_text__;
*(.data)
__data_end__ = .;
} >ram AT>flash
.bss :
{
__bss_beg__ = .;
*(.bss)
} >ram
. = ALIGN(4);
.eh_frame :
{
KEEP (*(.eh_frame))
} > ram
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
}
. = ALIGN(32 / 8);
_end = .;
_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
PROVIDE (end = .);

321
FreeRTOS/Demo/ARM7_LPC2106_GCC/lpc210x.h Normal file
View File

@ -0,0 +1,321 @@
#ifndef lpc210x_h
#define lpc210x_h
/*******************************************************************************
lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106
THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND,
EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY
WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS
OF OTHERS.
This file may be freely used for commercial and non-commercial applications,
including being redistributed with any tools.
If you find a problem with the file, please report it so that it can be fixed.
Created by Sten Larsson (sten_larsson at yahoo com)
Edited by Richard Barry.
*******************************************************************************/
#define REG8 (volatile unsigned char*)
#define REG16 (volatile unsigned short*)
#define REG32 (volatile unsigned int*)
/*##############################################################################
## MISC
##############################################################################*/
/* Constants for data to put in IRQ/FIQ Exception Vectors */
#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */
#define VECTDATA_FIQ /* __TODO */
/*##############################################################################
## VECTORED INTERRUPT CONTROLLER
##############################################################################*/
#define VICIRQStatus (*(REG32 (0xFFFFF000)))
#define VICFIQStatus (*(REG32 (0xFFFFF004)))
#define VICRawIntr (*(REG32 (0xFFFFF008)))
#define VICIntSelect (*(REG32 (0xFFFFF00C)))
#define VICIntEnable (*(REG32 (0xFFFFF010)))
#define VICIntEnClear (*(REG32 (0xFFFFF014)))
#define VICSoftInt (*(REG32 (0xFFFFF018)))
#define VICSoftIntClear (*(REG32 (0xFFFFF01C)))
#define VICProtection (*(REG32 (0xFFFFF020)))
#define VICVectAddr (*(REG32 (0xFFFFF030)))
#define VICDefVectAddr (*(REG32 (0xFFFFF034)))
#define VICVectAddr0 (*(REG32 (0xFFFFF100)))
#define VICVectAddr1 (*(REG32 (0xFFFFF104)))
#define VICVectAddr2 (*(REG32 (0xFFFFF108)))
#define VICVectAddr3 (*(REG32 (0xFFFFF10C)))
#define VICVectAddr4 (*(REG32 (0xFFFFF110)))
#define VICVectAddr5 (*(REG32 (0xFFFFF114)))
#define VICVectAddr6 (*(REG32 (0xFFFFF118)))
#define VICVectAddr7 (*(REG32 (0xFFFFF11C)))
#define VICVectAddr8 (*(REG32 (0xFFFFF120)))
#define VICVectAddr9 (*(REG32 (0xFFFFF124)))
#define VICVectAddr10 (*(REG32 (0xFFFFF128)))
#define VICVectAddr11 (*(REG32 (0xFFFFF12C)))
#define VICVectAddr12 (*(REG32 (0xFFFFF130)))
#define VICVectAddr13 (*(REG32 (0xFFFFF134)))
#define VICVectAddr14 (*(REG32 (0xFFFFF138)))
#define VICVectAddr15 (*(REG32 (0xFFFFF13C)))
#define VICVectCntl0 (*(REG32 (0xFFFFF200)))
#define VICVectCntl1 (*(REG32 (0xFFFFF204)))
#define VICVectCntl2 (*(REG32 (0xFFFFF208)))
#define VICVectCntl3 (*(REG32 (0xFFFFF20C)))
#define VICVectCntl4 (*(REG32 (0xFFFFF210)))
#define VICVectCntl5 (*(REG32 (0xFFFFF214)))
#define VICVectCntl6 (*(REG32 (0xFFFFF218)))
#define VICVectCntl7 (*(REG32 (0xFFFFF21C)))
#define VICVectCntl8 (*(REG32 (0xFFFFF220)))
#define VICVectCntl9 (*(REG32 (0xFFFFF224)))
#define VICVectCntl10 (*(REG32 (0xFFFFF228)))
#define VICVectCntl11 (*(REG32 (0xFFFFF22C)))
#define VICVectCntl12 (*(REG32 (0xFFFFF230)))
#define VICVectCntl13 (*(REG32 (0xFFFFF234)))
#define VICVectCntl14 (*(REG32 (0xFFFFF238)))
#define VICVectCntl15 (*(REG32 (0xFFFFF23C)))
#define VICITCR (*(REG32 (0xFFFFF300)))
#define VICITIP1 (*(REG32 (0xFFFFF304)))
#define VICITIP2 (*(REG32 (0xFFFFF308)))
#define VICITOP1 (*(REG32 (0xFFFFF30C)))
#define VICITOP2 (*(REG32 (0xFFFFF310)))
#define VICPeriphID0 (*(REG32 (0xFFFFFFE0)))
#define VICPeriphID1 (*(REG32 (0xFFFFFFE4)))
#define VICPeriphID2 (*(REG32 (0xFFFFFFE8)))
#define VICPeriphID3 (*(REG32 (0xFFFFFFEC)))
#define VICIntEnClr VICIntEnClear
#define VICSoftIntClr VICSoftIntClear
/*##############################################################################
## PCB - Pin Connect Block
##############################################################################*/
#define PCB_PINSEL0 (*(REG32 (0xE002C000)))
#define PCB_PINSEL1 (*(REG32 (0xE002C004)))
/*##############################################################################
## GPIO - General Purpose I/O
##############################################################################*/
#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */
#define GPIO_IOSET (*(REG32 (0xE0028004)))
#define GPIO_IODIR (*(REG32 (0xE0028008)))
#define GPIO_IOCLR (*(REG32 (0xE002800C)))
#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */
#define GPIO0_IOSET (*(REG32 (0xE0028004)))
#define GPIO0_IODIR (*(REG32 (0xE0028008)))
#define GPIO0_IOCLR (*(REG32 (0xE002800C)))
/*##############################################################################
## UART0 / UART1
##############################################################################*/
/* ---- UART 0 --------------------------------------------- */
#define UART0_RBR (*(REG32 (0xE000C000)))
#define UART0_THR (*(REG32 (0xE000C000)))
#define UART0_IER (*(REG32 (0xE000C004)))
#define UART0_IIR (*(REG32 (0xE000C008)))
#define UART0_FCR (*(REG32 (0xE000C008)))
#define UART0_LCR (*(REG32 (0xE000C00C)))
#define UART0_LSR (*(REG32 (0xE000C014)))
#define UART0_SCR (*(REG32 (0xE000C01C)))
#define UART0_DLL (*(REG32 (0xE000C000)))
#define UART0_DLM (*(REG32 (0xE000C004)))
/* ---- UART 1 --------------------------------------------- */
#define UART1_RBR (*(REG32 (0xE0010000)))
#define UART1_THR (*(REG32 (0xE0010000)))
#define UART1_IER (*(REG32 (0xE0010004)))
#define UART1_IIR (*(REG32 (0xE0010008)))
#define UART1_FCR (*(REG32 (0xE0010008)))
#define UART1_LCR (*(REG32 (0xE001000C)))
#define UART1_LSR (*(REG32 (0xE0010014)))
#define UART1_SCR (*(REG32 (0xE001001C)))
#define UART1_DLL (*(REG32 (0xE0010000)))
#define UART1_DLM (*(REG32 (0xE0010004)))
#define UART1_MCR (*(REG32 (0xE0010010)))
#define UART1_MSR (*(REG32 (0xE0010018)))
/*##############################################################################
## I2C
##############################################################################*/
#define I2C_I2CONSET (*(REG32 (0xE001C000)))
#define I2C_I2STAT (*(REG32 (0xE001C004)))
#define I2C_I2DAT (*(REG32 (0xE001C008)))
#define I2C_I2ADR (*(REG32 (0xE001C00C)))
#define I2C_I2SCLH (*(REG32 (0xE001C010)))
#define I2C_I2SCLL (*(REG32 (0xE001C014)))
#define I2C_I2CONCLR (*(REG32 (0xE001C018)))
/*##############################################################################
## SPI - Serial Peripheral Interface
##############################################################################*/
#define SPI_SPCR (*(REG32 (0xE0020000)))
#define SPI_SPSR (*(REG32 (0xE0020004)))
#define SPI_SPDR (*(REG32 (0xE0020008)))
#define SPI_SPCCR (*(REG32 (0xE002000C)))
#define SPI_SPTCR (*(REG32 (0xE0020010)))
#define SPI_SPTSR (*(REG32 (0xE0020014)))
#define SPI_SPTOR (*(REG32 (0xE0020018)))
#define SPI_SPINT (*(REG32 (0xE002001C)))
/*##############################################################################
## Timer 0 and Timer 1
##############################################################################*/
/* ---- Timer 0 -------------------------------------------- */
#define T0_IR (*(REG32 (0xE0004000)))
#define T0_TCR (*(REG32 (0xE0004004)))
#define T0_TC (*(REG32 (0xE0004008)))
#define T0_PR (*(REG32 (0xE000400C)))
#define T0_PC (*(REG32 (0xE0004010)))
#define T0_MCR (*(REG32 (0xE0004014)))
#define T0_MR0 (*(REG32 (0xE0004018)))
#define T0_MR1 (*(REG32 (0xE000401C)))
#define T0_MR2 (*(REG32 (0xE0004020)))
#define T0_MR3 (*(REG32 (0xE0004024)))
#define T0_CCR (*(REG32 (0xE0004028)))
#define T0_CR0 (*(REG32 (0xE000402C)))
#define T0_CR1 (*(REG32 (0xE0004030)))
#define T0_CR2 (*(REG32 (0xE0004034)))
#define T0_CR3 (*(REG32 (0xE0004038)))
#define T0_EMR (*(REG32 (0xE000403C)))
/* ---- Timer 1 -------------------------------------------- */
#define T1_IR (*(REG32 (0xE0008000)))
#define T1_TCR (*(REG32 (0xE0008004)))
#define T1_TC (*(REG32 (0xE0008008)))
#define T1_PR (*(REG32 (0xE000800C)))
#define T1_PC (*(REG32 (0xE0008010)))
#define T1_MCR (*(REG32 (0xE0008014)))
#define T1_MR0 (*(REG32 (0xE0008018)))
#define T1_MR1 (*(REG32 (0xE000801C)))
#define T1_MR2 (*(REG32 (0xE0008020)))
#define T1_MR3 (*(REG32 (0xE0008024)))
#define T1_CCR (*(REG32 (0xE0008028)))
#define T1_CR0 (*(REG32 (0xE000802C)))
#define T1_CR1 (*(REG32 (0xE0008030)))
#define T1_CR2 (*(REG32 (0xE0008034)))
#define T1_CR3 (*(REG32 (0xE0008038)))
#define T1_EMR (*(REG32 (0xE000803C)))
/*##############################################################################
## PWM
##############################################################################*/
#define PWM_IR (*(REG32 (0xE0014000)))
#define PWM_TCR (*(REG32 (0xE0014004)))
#define PWM_TC (*(REG32 (0xE0014008)))
#define PWM_PR (*(REG32 (0xE001400C)))
#define PWM_PC (*(REG32 (0xE0014010)))
#define PWM_MCR (*(REG32 (0xE0014014)))
#define PWM_MR0 (*(REG32 (0xE0014018)))
#define PWM_MR1 (*(REG32 (0xE001401C)))
#define PWM_MR2 (*(REG32 (0xE0014020)))
#define PWM_MR3 (*(REG32 (0xE0014024)))
#define PWM_MR4 (*(REG32 (0xE0014040)))
#define PWM_MR5 (*(REG32 (0xE0014044)))
#define PWM_MR6 (*(REG32 (0xE0014048)))
#define PWM_EMR (*(REG32 (0xE001403C)))
#define PWM_PCR (*(REG32 (0xE001404C)))
#define PWM_LER (*(REG32 (0xE0014050)))
#define PWM_CCR (*(REG32 (0xE0014028)))
#define PWM_CR0 (*(REG32 (0xE001402C)))
#define PWM_CR1 (*(REG32 (0xE0014030)))
#define PWM_CR2 (*(REG32 (0xE0014034)))
#define PWM_CR3 (*(REG32 (0xE0014038)))
/*##############################################################################
## RTC
##############################################################################*/
/* ---- RTC: Miscellaneous Register Group ------------------ */
#define RTC_ILR (*(REG32 (0xE0024000)))
#define RTC_CTC (*(REG32 (0xE0024004)))
#define RTC_CCR (*(REG32 (0xE0024008)))
#define RTC_CIIR (*(REG32 (0xE002400C)))
#define RTC_AMR (*(REG32 (0xE0024010)))
#define RTC_CTIME0 (*(REG32 (0xE0024014)))
#define RTC_CTIME1 (*(REG32 (0xE0024018)))
#define RTC_CTIME2 (*(REG32 (0xE002401C)))
/* ---- RTC: Timer Control Group --------------------------- */
#define RTC_SEC (*(REG32 (0xE0024020)))
#define RTC_MIN (*(REG32 (0xE0024024)))
#define RTC_HOUR (*(REG32 (0xE0024028)))
#define RTC_DOM (*(REG32 (0xE002402C)))
#define RTC_DOW (*(REG32 (0xE0024030)))
#define RTC_DOY (*(REG32 (0xE0024034)))
#define RTC_MONTH (*(REG32 (0xE0024038)))
#define RTC_YEAR (*(REG32 (0xE002403C)))
/* ---- RTC: Alarm Control Group --------------------------- */
#define RTC_ALSEC (*(REG32 (0xE0024060)))
#define RTC_ALMIN (*(REG32 (0xE0024064)))
#define RTC_ALHOUR (*(REG32 (0xE0024068)))
#define RTC_ALDOM (*(REG32 (0xE002406C)))
#define RTC_ALDOW (*(REG32 (0xE0024070)))
#define RTC_ALDOY (*(REG32 (0xE0024074)))
#define RTC_ALMON (*(REG32 (0xE0024078)))
#define RTC_ALYEAR (*(REG32 (0xE002407C)))
/* ---- RTC: Reference Clock Divider Group ----------------- */
#define RTC_PREINT (*(REG32 (0xE0024080)))
#define RTC_PREFRAC (*(REG32 (0xE0024084)))
/*##############################################################################
## WD - Watchdog
##############################################################################*/
#define WD_WDMOD (*(REG32 (0xE0000000)))
#define WD_WDTC (*(REG32 (0xE0000004)))
#define WD_WDFEED (*(REG32 (0xE0000008)))
#define WD_WDTV (*(REG32 (0xE000000C)))
/*##############################################################################
## System Control Block
##############################################################################*/
#define SCB_EXTINT (*(REG32 (0xE01FC140)))
#define SCB_EXTWAKE (*(REG32 (0xE01FC144)))
#define SCB_MEMMAP (*(REG32 (0xE01FC040)))
#define SCB_PLLCON (*(REG32 (0xE01FC080)))
#define SCB_PLLCFG (*(REG32 (0xE01FC084)))
#define SCB_PLLSTAT (*(REG32 (0xE01FC088)))
#define SCB_PLLFEED (*(REG32 (0xE01FC08C)))
#define SCB_PCON (*(REG32 (0xE01FC0C0)))
#define SCB_PCONP (*(REG32 (0xE01FC0C4)))
#define SCB_VPBDIV (*(REG32 (0xE01FC100)))
/*##############################################################################
## Memory Accelerator Module (MAM)
##############################################################################*/
#define MAM_TIM (*(REG32 (0xE01FC004)))
#define MAM_CR (*(REG32 (0xE01FC000)))
#endif /* lpc210x_h */

1
FreeRTOS/Demo/ARM7_LPC2106_GCC/lpc221x.h Normal file
View File

@ -0,0 +1 @@
#include "lpc2114.h"

470
FreeRTOS/Demo/ARM7_LPC2106_GCC/main.c Normal file
View File

@ -0,0 +1,470 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
* To check the operation of the memory allocator the check task also
* dynamically creates a task before delaying, and deletes it again when it
* wakes. If memory cannot be allocated for the new task the call to xTaskCreate
* will fail and an error is signalled. The dynamically created task itself
* allocates and frees memory just to give the allocator a bit more exercise.
*
*/
/*
Changes from V2.4.2
+ The vErrorChecks() task now dynamically creates then deletes a task each
cycle. This tests the operation of the memory allocator.
Changes from V2.5.2
+ vParTestInitialise() is called during initialisation to ensure all the
LED's start off.
*/
/* Standard includes. */
#include <stdlib.h>
#include <string.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "partest.h"
#include "flash.h"
#include "integer.h"
#include "PollQ.h"
#include "comtest2.h"
#include "semtest.h"
#include "flop.h"
#include "dynamic.h"
#include "BlockQ.h"
#include "serial.h"
/*-----------------------------------------------------------*/
/* Constants to setup I/O. */
#define mainTX_ENABLE ( ( unsigned long ) 0x0001 )
#define mainRX_ENABLE ( ( unsigned long ) 0x0004 )
#define mainP0_14 ( ( unsigned long ) 0x4000 )
#define mainJTAG_PORT ( ( unsigned long ) 0x3E0000UL )
/* Constants to setup the PLL. */
#define mainPLL_MUL_4 ( ( unsigned char ) 0x0003 )
#define mainPLL_DIV_1 ( ( unsigned char ) 0x0000 )
#define mainPLL_ENABLE ( ( unsigned char ) 0x0001 )
#define mainPLL_CONNECT ( ( unsigned char ) 0x0003 )
#define mainPLL_FEED_BYTE1 ( ( unsigned char ) 0xaa )
#define mainPLL_FEED_BYTE2 ( ( unsigned char ) 0x55 )
#define mainPLL_LOCK ( ( unsigned long ) 0x0400 )
/* Constants to setup the MAM. */
#define mainMAM_TIM_3 ( ( unsigned char ) 0x03 )
#define mainMAM_MODE_FULL ( ( unsigned char ) 0x02 )
/* Constants to setup the peripheral bus. */
#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 )
/* Constants for the ComTest tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 )
#define mainCOM_TEST_LED ( 3 )
/* Priorities for the demo application tasks. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 0 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 0 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* The rate at which the on board LED will toggle when there is/is not an
error. */
#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS )
#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS )
#define mainON_BOARD_LED_BIT ( ( unsigned long ) 0x80 )
/* Constants used by the vMemCheckTask() task. */
#define mainCOUNT_INITIAL_VALUE ( ( unsigned long ) 0 )
#define mainNO_TASK ( 0 )
/* The size of the memory blocks allocated by the vMemCheckTask() task. */
#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )
#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )
#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )
/*-----------------------------------------------------------*/
/*
* The Olimex demo board has a single built in LED. This function simply
* toggles its state.
*/
void prvToggleOnBoardLED( void );
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static long prvCheckOtherTasksAreStillRunning( unsigned long ulMemCheckTaskCount );
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Dynamically created and deleted during each cycle of the vErrorChecks()
* task. This is done to check the operation of the memory allocator.
* See the top of vErrorChecks for more details.
*/
static void vMemCheckTask( void *pvParameters );
/*
* Configure the processor for use with the Olimex demo board. This includes
* setup for the I/O, system clock, and access timings.
*/
static void prvSetupHardware( void );
/*-----------------------------------------------------------*/
/*
* Starts all the other tasks, then starts the scheduler.
*/
int main( void )
{
/* Setup the hardware for use with the Olimex demo board. */
prvSetupHardware();
/* Start the demo/test application tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartMathTasks( tskIDLE_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartDynamicPriorityTasks();
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
/* Start the check task - which is defined in this file. */
xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Now all the tasks have been started - start the scheduler.
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used here. */
vTaskStartScheduler();
/* Should never reach here! */
return 0;
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
unsigned long ulMemCheckTaskRunningCount;
TaskHandle_t xCreatedTask;
/* The parameters are not used in this function. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. If an error is detected then the delay period
is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
the on board LED flash rate will increase.
In addition to the standard tests the memory allocator is tested through
the dynamic creation and deletion of a task each cycle. Each time the
task is created memory must be allocated for its stack. When the task is
deleted this memory is returned to the heap. If the task cannot be created
then it is likely that the memory allocation failed. */
for( ;; )
{
/* Dynamically create a task - passing ulMemCheckTaskRunningCount as a
parameter. */
ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;
xCreatedTask = mainNO_TASK;
if( xTaskCreate( vMemCheckTask, "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
{
/* Could not create the task - we have probably run out of heap. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
/* Delay until it is time to execute again. */
vTaskDelay( xDelayPeriod );
/* Delete the dynamically created task. */
if( xCreatedTask != mainNO_TASK )
{
vTaskDelete( xCreatedTask );
}
/* Check all the standard demo application tasks are executing without
error. ulMemCheckTaskRunningCount is checked to ensure it was
modified by the task just deleted. */
if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
prvToggleOnBoardLED();
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
#ifdef RUN_FROM_RAM
/* Remap the interrupt vectors to RAM if we are are running from RAM. */
SCB_MEMMAP = 2;
#endif
/* Configure the RS2332 pins. All other pins remain at their default of 0. */
PCB_PINSEL0 |= mainTX_ENABLE;
PCB_PINSEL0 |= mainRX_ENABLE;
/* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins.
The JTAG pins are left as input as I'm not sure what will happen if the
Wiggler is connected after powerup - not that it would be a good idea to
do that anyway. */
GPIO_IODIR = ~( mainP0_14 + mainJTAG_PORT );
/* Setup the PLL to multiply the XTAL input by 4. */
SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 );
/* Activate the PLL by turning it on then feeding the correct sequence of
bytes. */
SCB_PLLCON = mainPLL_ENABLE;
SCB_PLLFEED = mainPLL_FEED_BYTE1;
SCB_PLLFEED = mainPLL_FEED_BYTE2;
/* Wait for the PLL to lock... */
while( !( SCB_PLLSTAT & mainPLL_LOCK ) );
/* ...before connecting it using the feed sequence again. */
SCB_PLLCON = mainPLL_CONNECT;
SCB_PLLFEED = mainPLL_FEED_BYTE1;
SCB_PLLFEED = mainPLL_FEED_BYTE2;
/* Setup and turn on the MAM. Three cycle access is used due to the fast
PLL used. It is possible faster overall performance could be obtained by
tuning the MAM and PLL settings. */
MAM_TIM = mainMAM_TIM_3;
MAM_CR = mainMAM_MODE_FULL;
/* Setup the peripheral bus to be the same as the PLL output. */
SCB_VPBDIV = mainBUS_CLK_FULL;
/* Initialise LED outputs. */
vParTestInitialise();
}
/*-----------------------------------------------------------*/
void prvToggleOnBoardLED( void )
{
unsigned long ulState;
ulState = GPIO0_IOPIN;
if( ulState & mainON_BOARD_LED_BIT )
{
GPIO_IOCLR = mainON_BOARD_LED_BIT;
}
else
{
GPIO_IOSET = mainON_BOARD_LED_BIT;
}
}
/*-----------------------------------------------------------*/
static long prvCheckOtherTasksAreStillRunning( unsigned long ulMemCheckTaskCount )
{
long lReturn = ( long ) pdPASS;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none of them have detected
an error. */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )
{
/* The vMemCheckTask did not increment the counter - it must
have failed. */
lReturn = ( long ) pdFAIL;
}
return lReturn;
}
/*-----------------------------------------------------------*/
static void vMemCheckTask( void *pvParameters )
{
unsigned long *pulMemCheckTaskRunningCounter;
void *pvMem1, *pvMem2, *pvMem3;
static long lErrorOccurred = pdFALSE;
/* This task is dynamically created then deleted during each cycle of the
vErrorChecks task to check the operation of the memory allocator. Each time
the task is created memory is allocated for the stack and TCB. Each time
the task is deleted this memory is returned to the heap. This task itself
exercises the allocator by allocating and freeing blocks.
The task executes at the idle priority so does not require a delay.
pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the
vErrorChecks() task that this task is still executing without error. */
pulMemCheckTaskRunningCounter = ( unsigned long * ) pvParameters;
for( ;; )
{
if( lErrorOccurred == pdFALSE )
{
/* We have never seen an error so increment the counter. */
( *pulMemCheckTaskRunningCounter )++;
}
/* Allocate some memory - just to give the allocator some extra
exercise. This has to be in a critical section to ensure the
task does not get deleted while it has memory allocated. */
vTaskSuspendAll();
{
pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );
if( pvMem1 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );
vPortFree( pvMem1 );
}
}
xTaskResumeAll();
/* Again - with a different size block. */
vTaskSuspendAll();
{
pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );
if( pvMem2 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );
vPortFree( pvMem2 );
}
}
xTaskResumeAll();
/* Again - with a different size block. */
vTaskSuspendAll();
{
pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );
if( pvMem3 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );
vPortFree( pvMem3 );
}
}
xTaskResumeAll();
}
}

6
FreeRTOS/Demo/ARM7_LPC2106_GCC/ram_arm.bat Normal file
View File

@ -0,0 +1,6 @@
set USE_THUMB_MODE=NO
set DEBUG=-g
set OPTIM=-O0
set RUN_MODE=RUN_FROM_RAM
set LDSCRIPT=lpc2106-ram.ld
make

6
FreeRTOS/Demo/ARM7_LPC2106_GCC/ram_thumb.bat Normal file
View File

@ -0,0 +1,6 @@
set USE_THUMB_MODE=YES
set DEBUG=-g
set OPTIM=-O0
set RUN_MODE=RUN_FROM_RAM
set LDSCRIPT=lpc2106-ram.ld
make

18
FreeRTOS/Demo/ARM7_LPC2106_GCC/readme.txt Normal file
View File

@ -0,0 +1,18 @@
Use one of the following four batch files to build the demo application:
+ rom_arm.bat
Creates an ARM mode release build suitable for programming into flash.
+ ram_arm.bat
Creates an ARM mode debug build suitable for running from RAM.
+ rom_thumb.bat
Creates a THUMB mode release build suitable for programming into flash.
+ ram_thumb.bat
Creates a THUMB mode debug build suitable for running from RAM.

6
FreeRTOS/Demo/ARM7_LPC2106_GCC/rom_arm.bat Normal file
View File

@ -0,0 +1,6 @@
set USE_THUMB_MODE=NO
set DEBUG=
set OPTIM=-O3
set RUN_MODE=RUN_FROM_ROM
set LDSCRIPT=lpc2106-rom.ld
make

6
FreeRTOS/Demo/ARM7_LPC2106_GCC/rom_thumb.bat Normal file
View File

@ -0,0 +1,6 @@
set USE_THUMB_MODE=YES
set DEBUG=
set OPTIM=-O3
set RUN_MODE=RUN_FROM_ROM
set LDSCRIPT=lpc2106-rom.ld
make

258
FreeRTOS/Demo/ARM7_LPC2106_GCC/serial/serial.c Normal file
View File

@ -0,0 +1,258 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
Changes from V2.4.0
+ Made serial ISR handling more complete and robust.
Changes from V2.4.1
+ Split serial.c into serial.c and serialISR.c. serial.c can be
compiled using ARM or THUMB modes. serialISR.c must always be
compiled in ARM mode.
+ Another small change to cSerialPutChar().
Changed from V2.5.1
+ In cSerialPutChar() an extra check is made to ensure the post to
the queue was successful if then attempting to retrieve the posted
character.
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
This file contains all the serial port components that can be compiled to
either ARM or THUMB mode. Components that must be compiled to ARM mode are
contained in serialISR.c.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Constants to setup and access the UART. */
#define serDLAB ( ( unsigned char ) 0x80 )
#define serENABLE_INTERRUPTS ( ( unsigned char ) 0x03 )
#define serNO_PARITY ( ( unsigned char ) 0x00 )
#define ser1_STOP_BIT ( ( unsigned char ) 0x00 )
#define ser8_BIT_CHARS ( ( unsigned char ) 0x03 )
#define serFIFO_ON ( ( unsigned char ) 0x01 )
#define serCLEAR_FIFO ( ( unsigned char ) 0x06 )
#define serWANTED_CLOCK_SCALING ( ( unsigned long ) 16 )
/* Constants to setup and access the VIC. */
#define serUART0_VIC_CHANNEL ( ( unsigned long ) 0x0006 )
#define serUART0_VIC_CHANNEL_BIT ( ( unsigned long ) 0x0040 )
#define serUART0_VIC_ENABLE ( ( unsigned long ) 0x0020 )
#define serCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )
#define serINVALID_QUEUE ( ( QueueHandle_t ) 0 )
#define serHANDLE ( ( xComPortHandle ) 1 )
#define serNO_BLOCK ( ( TickType_t ) 0 )
/*-----------------------------------------------------------*/
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static QueueHandle_t xRxedChars;
static QueueHandle_t xCharsForTx;
/*-----------------------------------------------------------*/
/* Communication flag between the interrupt service routine and serial API. */
static volatile long *plTHREEmpty;
/*
* The queues are created in serialISR.c as they are used from the ISR.
* Obtain references to the queues and THRE Empty flag.
*/
extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, QueueHandle_t *pxRxedChars, QueueHandle_t *pxCharsForTx, long volatile **pplTHREEmptyFlag );
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned long ulDivisor, ulWantedClock;
xComPortHandle xReturn = serHANDLE;
extern void ( vUART_ISR_Wrapper )( void );
/* The queues are used in the serial ISR routine, so are created from
serialISR.c (which is always compiled to ARM mode. */
vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty );
if(
( xRxedChars != serINVALID_QUEUE ) &&
( xCharsForTx != serINVALID_QUEUE ) &&
( ulWantedBaud != ( unsigned long ) 0 )
)
{
portENTER_CRITICAL();
{
/* Setup the baud rate: Calculate the divisor value. */
ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;
ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;
/* Set the DLAB bit so we can access the divisor. */
UART0_LCR |= serDLAB;
/* Setup the divisor. */
UART0_DLL = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );
ulDivisor >>= 8;
UART0_DLM = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );
/* Turn on the FIFO's and clear the buffers. */
UART0_FCR = ( serFIFO_ON | serCLEAR_FIFO );
/* Setup transmission format. */
UART0_LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;
/* Setup the VIC for the UART. */
VICIntSelect &= ~( serUART0_VIC_CHANNEL_BIT );
VICIntEnable |= serUART0_VIC_CHANNEL_BIT;
VICVectAddr1 = ( long ) vUART_ISR_Wrapper;
VICVectCntl1 = serUART0_VIC_CHANNEL | serUART0_VIC_ENABLE;
/* Enable UART0 interrupts. */
UART0_IER |= serENABLE_INTERRUPTS;
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
{
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
{
signed char *pxNext;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
( void ) usStringLength;
/* Send each character in the string, one at a time. */
pxNext = ( signed char * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
{
signed portBASE_TYPE xReturn;
/* This demo driver only supports one port so the parameter is not used. */
( void ) pxPort;
portENTER_CRITICAL();
{
/* Is there space to write directly to the UART? */
if( *plTHREEmpty == ( long ) pdTRUE )
{
/* We wrote the character directly to the UART, so was
successful. */
*plTHREEmpty = pdFALSE;
UART0_THR = cOutChar;
xReturn = pdPASS;
}
else
{
/* We cannot write directly to the UART, so queue the character.
Block for a maximum of xBlockTime if there is no space in the
queue. */
xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
/* Depending on queue sizing and task prioritisation: While we
were blocked waiting to post interrupts were not disabled. It is
possible that the serial ISR has emptied the Tx queue, in which
case we need to start the Tx off again. */
if( ( *plTHREEmpty == ( long ) pdTRUE ) && ( xReturn == pdPASS ) )
{
xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
*plTHREEmpty = pdFALSE;
UART0_THR = cOutChar;
}
}
}
portEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
( void ) xPort;
}
/*-----------------------------------------------------------*/

166
FreeRTOS/Demo/ARM7_LPC2106_GCC/serial/serialISR.c Normal file
View File

@ -0,0 +1,166 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
This file contains all the serial port components that must be compiled
to ARM mode. The components that can be compiled to either ARM or THUMB
mode are contained in serial.c.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Constant to access the VIC. */
#define serCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )
/* Constants to determine the ISR source. */
#define serSOURCE_THRE ( ( unsigned char ) 0x02 )
#define serSOURCE_RX_TIMEOUT ( ( unsigned char ) 0x0c )
#define serSOURCE_ERROR ( ( unsigned char ) 0x06 )
#define serSOURCE_RX ( ( unsigned char ) 0x04 )
#define serINTERRUPT_SOURCE_MASK ( ( unsigned char ) 0x0f )
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static QueueHandle_t xRxedChars;
static QueueHandle_t xCharsForTx;
static volatile long lTHREEmpty;
/*-----------------------------------------------------------*/
/*
* The queues are created in serialISR.c as they are used from the ISR.
* Obtain references to the queues and THRE Empty flag.
*/
void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, QueueHandle_t *pxRxedChars, QueueHandle_t *pxCharsForTx, long volatile **pplTHREEmptyFlag );
/* UART0 interrupt service routine entry point. */
void vUART_ISR_Wrapper( void ) __attribute__ ((naked));
/* UART0 interrupt service routine handler. */
void vUART_ISR_Handler( void ) __attribute__ ((noinline));
/*-----------------------------------------------------------*/
void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, QueueHandle_t *pxRxedChars,
QueueHandle_t *pxCharsForTx, long volatile **pplTHREEmptyFlag )
{
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
/* Pass back a reference to the queues so the serial API file can
post/receive characters. */
*pxRxedChars = xRxedChars;
*pxCharsForTx = xCharsForTx;
/* Initialise the THRE empty flag - and pass back a reference. */
lTHREEmpty = ( long ) pdTRUE;
*pplTHREEmptyFlag = &lTHREEmpty;
}
/*-----------------------------------------------------------*/
void vUART_ISR_Wrapper( void )
{
/* Save the context of the interrupted task. */
portSAVE_CONTEXT();
/* Call the handler. This must be a separate function from the wrapper
to ensure the correct stack frame is set up. */
__asm volatile ("bl vUART_ISR_Handler");
/* Restore the context of whichever task is going to run next. */
portRESTORE_CONTEXT();
}
/*-----------------------------------------------------------*/
void vUART_ISR_Handler( void )
{
signed char cChar;
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
/* What caused the interrupt? */
switch( UART0_IIR & serINTERRUPT_SOURCE_MASK )
{
case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */
cChar = UART0_LSR;
break;
case serSOURCE_THRE : /* The THRE is empty. If there is another
character in the Tx queue, send it now. */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
{
UART0_THR = cChar;
}
else
{
/* There are no further characters
queued to send so we can indicate
that the THRE is available. */
lTHREEmpty = pdTRUE;
}
break;
case serSOURCE_RX_TIMEOUT :
case serSOURCE_RX : /* A character was received. Place it in
the queue of received characters. */
cChar = UART0_RBR;
xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
break;
default : /* There is nothing to do, leave the ISR. */
break;
}
if( xHigherPriorityTaskWoken )
{
portYIELD_FROM_ISR();
}
/* Clear the ISR in the VIC. */
VICVectAddr = serCLEAR_VIC_INTERRUPT;
}

77
FreeRTOS/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h Normal file
View File

@ -0,0 +1,77 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/* Hardware specifics. */
#ifdef __ICCARM__
#include <NXP/iolpc2129.h>
#endif
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configMAX_PRIORITIES ( 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) 14200 )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

97
FreeRTOS/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c Normal file
View File

@ -0,0 +1,97 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*-----------------------------------------------------------
* Simple parallel port IO routines for the LED's.
*-----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
/* Demo application includes. */
#include "partest.h"
/* Board specific defines. */
#define partstFIRST_IO ( ( unsigned long ) 0x10000 )
#define partstNUM_LEDS ( 8 )
/*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* The ports are setup within prvInitialiseHardware(), called by main(). */
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned long ulLED = partstFIRST_IO;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 1. Only P16 to P23 have an LED
attached. */
ulLED <<= ( unsigned long ) uxLED;
/* Set or clear the output. */
if( xValue )
{
IO1SET = ulLED;
}
else
{
IO1CLR = ulLED;
}
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned long ulLED = partstFIRST_IO, ulCurrentState;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 1. Only P10 to P13 have an LED
attached. */
ulLED <<= ( unsigned long ) uxLED;
/* If this bit is already set, clear it, and vice versa. */
ulCurrentState = IO1PIN;
if( ulCurrentState & ulLED )
{
IO1CLR = ulLED;
}
else
{
IO1SET = ulLED;
}
}
}

189
FreeRTOS/Demo/ARM7_LPC2129_IAR/SrcIAR/lpc2xxx_cstartup.s Normal file
View File

@ -0,0 +1,189 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Part one of the system initialization code,
;; contains low-level
;; initialization.
;;
;; Copyright 2006 IAR Systems. All rights reserved.
;;
;; $Revision: 10608 $
;;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION IRQ_STACK:DATA:NOROOT(3)
SECTION ABT_STACK:DATA:NOROOT(3)
SECTION SVC_STACK:DATA:NOROOT(3)
SECTION UND_STACK:DATA:NOROOT(3)
SECTION FIQ_STACK:DATA:NOROOT(3)
SECTION CSTACK:DATA:NOROOT(3)
;
; The module in this file are included in the libraries, and may be
; replaced by any user-defined modules that define the PUBLIC symbol
; __iar_program_start or a user defined start symbol.
;
; To override the cstartup defined in the library, simply add your
; modified version to the workbench project.
SECTION .intvec:CODE:NOROOT(2)
PUBLIC __vector
PUBLIC __vector_0x14
PUBLIC __iar_program_start
EXTERN vPortYieldProcessor
ARM
__vector:
;;
ldr pc,[pc,#+24] ;; Reset
ldr pc,[pc,#+24] ;; Undefined instructions
;; ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC)
b vPortYieldProcessor
ldr pc,[pc,#+24] ;; Prefetch abort
ldr pc,[pc,#+24] ;; Data abort
__vector_0x14
DC32 0 ;; RESERVED
ldr pc, [PC, #-0xFF0] ;; IRQ
ldr pc,[pc,#+24] ;; FIQ
DC32 __iar_program_start ;; Reset
DC32 undef_handler ;; Undefined instructions
DC32 0 ;; Software interrupt (SWI/SVC)
DC32 prefetch_handler ;; Prefetch abort
DC32 data_handler ;; Data abort
DC32 0 ;; RESERVED
DC32 0 ;; IRQ
DC32 fiq_handler ;; FIQ
undef_handler
b undef_handler
prefetch_handler
b prefetch_handler
data_handler
b data_handler
fiq_handler
b fiq_handler
; --------------------------------------------------
; ?cstartup -- low-level system initialization code.
;
; After a reser execution starts here, the mode is ARM, supervisor
; with interrupts disabled.
;
SECTION .text:CODE:NOROOT(2)
; PUBLIC ?cstartup
EXTERN ?main
REQUIRE __vector
ARM
__iar_program_start:
?cstartup:
;
; Add initialization needed before setup of stackpointers here.
;
; Errata MAM.1Incorrect read of data from SRAM after Reset and MAM
; is not enabled or partially enabled.
; Work-around: User code should enable the MAM after Reset and before
; any RAM accesses
MAMCR DEFINE 0xE01FC000 ; MAM Control Register
MAMTIM DEFINE 0xE01FC004 ; MAM Timing register
ldr r0,=MAMCR
ldr r1,=MAMTIM
ldr r2,=0
str r2,[r0]
ldr r2,=3 ; 1 < 20 MHz; 20 MHz < 2 < 40 MHz; 40MHz > 3
str r2,[r1]
ldr r2,=2
str r2,[r0]
; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.
;
; --------------------
; Mode, correspords to bits 0-5 in CPSR
MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR
USR_MODE DEFINE 0x10 ; User mode
FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode
IRQ_MODE DEFINE 0x12 ; Interrupt Request mode
SVC_MODE DEFINE 0x13 ; Supervisor mode
ABT_MODE DEFINE 0x17 ; Abort mode
UND_MODE DEFINE 0x1B ; Undefined Instruction mode
SYS_MODE DEFINE 0x1F ; System mode
MRS r0, cpsr ; Original PSR value
BIC r0, r0, #MODE_BITS ; Clear the mode bits
ORR r0, r0, #ABT_MODE ; Set ABT mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(ABT_STACK) ; End of ABT_STACK
BIC r0, r0, #MODE_BITS ; Clear the mode bits
ORR r0, r0, #SVC_MODE ; Set SVC mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK
BIC r0, r0, #MODE_BITS ; Clear the mode bits
ORR r0, r0, #UND_MODE ; Set UND mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(UND_STACK) ; End of UND_STACK
BIC r0, r0, #MODE_BITS ; Clear the mode bits
ORR r0, r0, #FIQ_MODE ; Set FIQ mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
BIC r0, r0, #MODE_BITS ; Clear the mode bits
ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
BIC r0 ,r0, #MODE_BITS ; Clear the mode bits
ORR r0 ,r0, #SYS_MODE ; Set System mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(CSTACK) ; End of CSTACK
#ifdef __ARMVFP__
;; Enable the VFP coprocessor.
MOV r0, #0x40000000 ; Set EN bit in VFP
FMXR fpexc, r0 ; FPEXC, clear others.
;
; Disable underflow exceptions by setting flush to zero mode.
; For full IEEE 754 underflow compliance this code should be removed
; and the appropriate exception handler installed.
;
MOV r0, #0x01000000 ; Set FZ bit in VFP
FMXR fpscr, r0 ; FPSCR, clear others.
#endif
;
; Add more initialization here
;
BIC r0, r0, #MODE_BITS ; Clear the mode bits
ORR r0, r0, #SVC_MODE ; Set SVC mode bits
MSR cpsr_c, r0 ; Change the mode
; Continue to ?main for C-level initialization.
LDR r0, =?main
BX r0
END

279
FreeRTOS/Demo/ARM7_LPC2129_IAR/main.c Normal file
View File

@ -0,0 +1,279 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "flash.h"
#include "integer.h"
#include "PollQ.h"
#include "BlockQ.h"
#include "semtest.h"
#include "dynamic.h"
#include "partest.h"
#include "comtest2.h"
/* Priorities for the demo application tasks. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* Constants required by the 'Check' task. */
#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS )
#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS )
#define mainCHECK_TASK_LED ( 7 )
/* Constants for the ComTest tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 )
#define mainCOM_TEST_LED ( 4 )
#define mainTX_ENABLE ( ( unsigned long ) 0x0001 )
#define mainRX_ENABLE ( ( unsigned long ) 0x0004 )
/* Constants to setup the PLL. */
#define mainPLL_MUL_5 ( ( unsigned char ) 0x0004 )
#define mainPLL_DIV_1 ( ( unsigned char ) 0x0000 )
#define mainPLL_ENABLE ( ( unsigned char ) 0x0001 )
#define mainPLL_CONNECT ( ( unsigned char ) 0x0003 )
#define mainPLL_FEED_BYTE1 ( ( unsigned char ) 0xaa )
#define mainPLL_FEED_BYTE2 ( ( unsigned char ) 0x55 )
#define mainPLL_LOCK ( ( unsigned long ) 0x0400 )
/* Constants to setup the MAM. */
#define mainMAM_TIM_3 ( ( unsigned char ) 0x03 )
#define mainMAM_MODE_FULL ( ( unsigned char ) 0x02 )
/* Constants to setup the peripheral bus. */
#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 )
/* And finally, constant to setup the port for the LED's. */
#define mainLED_TO_OUTPUT ( ( unsigned long ) 0xff0000 )
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Configures the processor for use with this demo.
*/
static void prvSetupHardware( void );
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static long prvCheckOtherTasksAreStillRunning( void );
/*-----------------------------------------------------------*/
/*
* Starts all the other tasks, then starts the scheduler.
*/
void main( void )
{
/* Setup the processor. */
prvSetupHardware();
/* Start all the standard demo application tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vStartDynamicPriorityTasks();
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
/* Start the check task - which is defined in this file. */
xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Start the scheduler.
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used here.
*/
vTaskStartScheduler();
/* We should never get here as control is now taken by the scheduler. */
return;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Setup the PLL to multiply the XTAL input by 5. */
PLLCFG = ( mainPLL_MUL_5 | mainPLL_DIV_1 );
/* Activate the PLL by turning it on then feeding the correct sequence of
bytes. */
PLLCON = mainPLL_ENABLE;
PLLFEED = mainPLL_FEED_BYTE1;
PLLFEED = mainPLL_FEED_BYTE2;
/* Wait for the PLL to lock... */
while( !( PLLSTAT & mainPLL_LOCK ) );
/* ...before connecting it using the feed sequence again. */
PLLCON = mainPLL_CONNECT;
PLLFEED = mainPLL_FEED_BYTE1;
PLLFEED = mainPLL_FEED_BYTE2;
/* Setup and turn on the MAM. Three cycle access is used due to the fast
PLL used. It is possible faster overall performance could be obtained by
tuning the MAM and PLL settings. */
MAMTIM = mainMAM_TIM_3;
MAMCR = mainMAM_MODE_FULL;
/* Setup the peripheral bus to be the same as the PLL output. */
APBDIV = mainBUS_CLK_FULL;
/* Configure the RS2332 pins. All other pins remain at their default of 0. */
PINSEL0 |= mainTX_ENABLE;
PINSEL0 |= mainRX_ENABLE;
/* LED pins need to be output. */
IO1DIR = mainLED_TO_OUTPUT;
/* Setup the peripheral bus to be the same as the PLL output. */
APBDIV = mainBUS_CLK_FULL;
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
/* The parameters are not used in this task. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. If an error is detected then the delay period
is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
the on board LED flash rate will increase. */
for( ;; )
{
/* Delay until it is time to execute again. */
vTaskDelay( xDelayPeriod );
/* Check all the standard demo application tasks are executing without
error. */
if( prvCheckOtherTasksAreStillRunning() != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
vParTestToggleLED( mainCHECK_TASK_LED );
}
}
/*-----------------------------------------------------------*/
static long prvCheckOtherTasksAreStillRunning( void )
{
long lReturn = ( long ) pdPASS;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none of them have detected
an error. */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lReturn = ( long ) pdFAIL;
}
return lReturn;
}
/*-----------------------------------------------------------*/

47
FreeRTOS/Demo/ARM7_LPC2129_IAR/resource/lpc212x.icf Normal file
View File

@ -0,0 +1,47 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000044;
define symbol __ICFEDIT_region_ROM_end__ = 0x3FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x40000040;
define symbol __ICFEDIT_region_RAM_end__ = 0x40003FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x200;
define symbol __ICFEDIT_size_svcstack__ = 0x200;
define symbol __ICFEDIT_size_irqstack__ = 0x200;
define symbol __ICFEDIT_size_fiqstack__ = 0x00;
define symbol __ICFEDIT_size_undstack__ = 0x0;
define symbol __ICFEDIT_size_abtstack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x0;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP };

1379
FreeRTOS/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd Normal file
View File

File diff suppressed because it is too large Load Diff

1664
FreeRTOS/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp Normal file
View File

File diff suppressed because it is too large Load Diff

10
FreeRTOS/Demo/ARM7_LPC2129_IAR/rtosdemo.eww Normal file
View File

@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\rtosdemo.ewp</path>
</project>
<batchBuild/>
</workspace>

280
FreeRTOS/Demo/ARM7_LPC2129_IAR/serial/serial.c Normal file
View File

@ -0,0 +1,280 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Constants to setup and access the UART. */
#define serDLAB ( ( unsigned char ) 0x80 )
#define serENABLE_INTERRUPTS ( ( unsigned char ) 0x03 )
#define serNO_PARITY ( ( unsigned char ) 0x00 )
#define ser1_STOP_BIT ( ( unsigned char ) 0x00 )
#define ser8_BIT_CHARS ( ( unsigned char ) 0x03 )
#define serFIFO_ON ( ( unsigned char ) 0x01 )
#define serCLEAR_FIFO ( ( unsigned char ) 0x06 )
#define serWANTED_CLOCK_SCALING ( ( unsigned long ) 16 )
/* Constants to setup and access the VIC. */
#define serU0VIC_CHANNEL ( ( unsigned long ) 0x0006 )
#define serU0VIC_CHANNEL_BIT ( ( unsigned long ) 0x0040 )
#define serU0VIC_ENABLE ( ( unsigned long ) 0x0020 )
#define serCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )
/* Constants to determine the ISR source. */
#define serSOURCE_THRE ( ( unsigned char ) 0x02 )
#define serSOURCE_RX_TIMEOUT ( ( unsigned char ) 0x0c )
#define serSOURCE_ERROR ( ( unsigned char ) 0x06 )
#define serSOURCE_RX ( ( unsigned char ) 0x04 )
#define serINTERRUPT_SOURCE_MASK ( ( unsigned char ) 0x0f )
/* Misc. */
#define serINVALID_QUEUE ( ( QueueHandle_t ) 0 )
#define serHANDLE ( ( xComPortHandle ) 1 )
#define serNO_BLOCK ( ( TickType_t ) 0 )
/*-----------------------------------------------------------*/
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static QueueHandle_t xRxedChars;
static QueueHandle_t xCharsForTx;
static volatile long lTHREEmpty = pdFALSE;
/*-----------------------------------------------------------*/
/* The ISR. Note that this is called by a wrapper written in the file
SerialISR.s79. See the WEB documentation for this port for further
information. */
__arm void vSerialISR( void );
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned long ulDivisor, ulWantedClock;
xComPortHandle xReturn = serHANDLE;
extern void ( vSerialISREntry) ( void );
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
/* Initialise the THRE empty flag. */
lTHREEmpty = pdTRUE;
if(
( xRxedChars != serINVALID_QUEUE ) &&
( xCharsForTx != serINVALID_QUEUE ) &&
( ulWantedBaud != ( unsigned long ) 0 )
)
{
portENTER_CRITICAL();
{
/* Setup the baud rate: Calculate the divisor value. */
ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;
ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;
/* Set the DLAB bit so we can access the divisor. */
U0LCR |= serDLAB;
/* Setup the divisor. */
U0DLL = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );
ulDivisor >>= 8;
U0DLM = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );
/* Turn on the FIFO's and clear the buffers. */
U0FCR = ( serFIFO_ON | serCLEAR_FIFO );
/* Setup transmission format. */
U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;
/* Setup the VIC for the UART. */
VICIntSelect &= ~( serU0VIC_CHANNEL_BIT );
VICIntEnable |= serU0VIC_CHANNEL_BIT;
VICVectAddr1 = ( unsigned long ) vSerialISREntry;
VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE;
/* Enable UART0 interrupts. */
U0IER |= serENABLE_INTERRUPTS;
}
portEXIT_CRITICAL();
xReturn = ( xComPortHandle ) 1;
}
else
{
xReturn = ( xComPortHandle ) 0;
}
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
{
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
{
signed char *pxNext;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
( void ) usStringLength;
/* Send each character in the string, one at a time. */
pxNext = ( signed char * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
{
signed portBASE_TYPE xReturn;
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
portENTER_CRITICAL();
{
/* Is there space to write directly to the UART? */
if( lTHREEmpty == ( long ) pdTRUE )
{
/* We wrote the character directly to the UART, so was
successful. */
lTHREEmpty = pdFALSE;
U0THR = cOutChar;
xReturn = pdPASS;
}
else
{
/* We cannot write directly to the UART, so queue the character.
Block for a maximum of xBlockTime if there is no space in the
queue. It is ok to block within a critical section as each
task has it's own critical section management. */
xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
/* Depending on queue sizing and task prioritisation: While we
were blocked waiting to post interrupts were not disabled. It is
possible that the serial ISR has emptied the Tx queue, in which
case we need to start the Tx off again. */
if( lTHREEmpty == ( long ) pdTRUE )
{
xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
lTHREEmpty = pdFALSE;
U0THR = cOutChar;
}
}
}
portEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
__arm void vSerialISR( void )
{
signed char cChar;
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
/* What caused the interrupt? */
switch( U0IIR & serINTERRUPT_SOURCE_MASK )
{
case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */
cChar = U0LSR;
break;
case serSOURCE_THRE : /* The THRE is empty. If there is another
character in the Tx queue, send it now. */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
{
U0THR = cChar;
}
else
{
/* There are no further characters
queued to send so we can indicate
that the THRE is available. */
lTHREEmpty = pdTRUE;
}
break;
case serSOURCE_RX_TIMEOUT :
case serSOURCE_RX : /* A character was received. Place it in
the queue of received characters. */
cChar = U0RBR;
xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
break;
default : /* There is nothing to do, leave the ISR. */
break;
}
/* Exit the ISR. If a task was woken by either a character being received
or transmitted then a context switch will occur. */
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
/* Clear the ISR in the VIC. */
VICVectAddr = serCLEAR_VIC_INTERRUPT;
}
/*-----------------------------------------------------------*/

24
FreeRTOS/Demo/ARM7_LPC2129_IAR/serial/serialISR.s79 Normal file
View File

@ -0,0 +1,24 @@
RSEG ICODE:CODE
CODE32
EXTERN vSerialISR
PUBLIC vSerialISREntry
; Wrapper for the serial port interrupt service routine. This can cause a
; context switch so requires an assembly wrapper.
; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.
#include "ISR_Support.h"
vSerialISREntry:
portSAVE_CONTEXT ; Save the context of the current task.
bl vSerialISR ; Call the ISR routine.
portRESTORE_CONTEXT ; Restore the context of the current task -
; which may be different to the task that
; was interrupted.
END

71
FreeRTOS/Demo/ARM7_LPC2129_IAR/settings/Basic.dbgdt Normal file
View File

@ -0,0 +1,71 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<Project>
<Desktop>
<Static>
<Workspace>
<ColumnWidths>
<Column0>189</Column0><Column1>27</Column1><Column2>27</Column2></ColumnWidths>
</Workspace>
<Disassembly>
<PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly>
<Debug-Log/>
<Build/>
<Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register><QWatch><Column0>188</Column0><Column1>171</Column1><Column2>100</Column2><Column3>100</Column3></QWatch><Memory><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory><Watch><Format><struct_types/><watch_formats/></Format></Watch></Static>
<Windows>
<Wnd0>
<Tabs>
<Tab>
<Identity>TabID-23416-30482</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>rtosdemo</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd0>
<Wnd2>
<Tabs>
<Tab>
<Identity>TabID-12145-30489</Identity>
<TabName>Debug Log</TabName>
<Factory>Debug-Log</Factory>
<Session/>
</Tab>
<Tab>
<Identity>TabID-22894-30492</Identity>
<TabName>Build</TabName>
<Factory>Build</Factory>
<Session/>
</Tab>
</Tabs>
<SelectedTab>1</SelectedTab></Wnd2>
<Wnd4><Tabs><Tab><Identity>TabID-18780-12821</Identity><TabName>Memory</TabName><Factory>Memory</Factory><Session><SelectionAnchor>2097764</SelectionAnchor><SelectionEnd>2097764</SelectionEnd><UnitsPerGroup>1</UnitsPerGroup><EndianMode>0</EndianMode><DataCovEnabled>0</DataCovEnabled><DataCovShown>0</DataCovShown></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd4><Wnd5><Tabs><Tab><Identity>TabID-23506-14575</Identity><TabName>Watch</TabName><Factory>Watch</Factory><Session><Expressions><Expression><Expression>pxCurrentTCB</Expression></Expression><Expression><Expression>ulCriticalNesting</Expression></Expression></Expressions><TabId>0</TabId><Column0>176</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd5><Wnd1><Tabs><Tab><Identity>TabID-4859-22480</Identity><TabName>Disassembly</TabName><Factory>Disassembly</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1><Wnd3><Tabs><Tab><Identity>TabID-154-22568</Identity><TabName>Register</TabName><Factory>Register</Factory><Session><REG1>0</REG1><REG2>0</REG2><Group>0</Group><States>1</States><State0>CPSR</State0></Session></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>
<Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\main.c</Filename><XPos>0</XPos><YPos>10</YPos><SelStart>378</SelStart><SelEnd>378</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\source\include\task.h</Filename><XPos>0</XPos><YPos>778</YPos><SelStart>24283</SelStart><SelEnd>24283</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\tasks.c</Filename><XPos>0</XPos><YPos>939</YPos><SelStart>30511</SelStart><SelEnd>30511</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\SrcIAR\Cstartup.s79</Filename><XPos>0</XPos><YPos>48</YPos><SelStart>2226</SelStart><SelEnd>2226</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\Common\Minimal\flash.c</Filename><XPos>0</XPos><YPos>98</YPos><SelStart>4025</SelStart><SelEnd>4025</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portasm.s79</Filename><XPos>0</XPos><YPos>41</YPos><SelStart>1057</SelStart><SelEnd>1079</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\srciar\lib_AT91SAM7S64.h</Filename><XPos>0</XPos><YPos>2778</YPos><SelStart>108450</SelStart><SelEnd>108450</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c</Filename><XPos>0</XPos><YPos>136</YPos><SelStart>5326</SelStart><SelEnd>5326</SelEnd></Tab><ActiveTab>7</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\ParTest\ParTest.c</Filename><XPos>0</XPos><YPos>36</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portmacro.h</Filename><XPos>0</XPos><YPos>67</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-0084f8a0><key>IarIdePM1</key></Toolbar-0084f8a0></Sizes></Row0><Row1><Sizes><Toolbar-031ef990><key>DebuggerGui1</key></Toolbar-031ef990></Sizes></Row1></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>715</Bottom><Right>263</Right><x>-2</x><y>-2</y><xscreen>153</xscreen><yscreen>153</yscreen><sizeHorzCX>95625</sizeHorzCX><sizeHorzCY>136729</sizeHorzCY><sizeVertCX>165625</sizeVertCX><sizeVertCY>640750</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>715</Bottom><Right>647</Right><x>-2</x><y>-2</y><xscreen>190</xscreen><yscreen>190</yscreen><sizeHorzCX>118750</sizeHorzCX><sizeHorzCY>169794</sizeHorzCY><sizeVertCX>405625</sizeVertCX><sizeVertCY>640750</sizeVertCY></Rect></Wnd1></Sizes></Row0><Row1><Sizes><Wnd3><Rect><Top>-2</Top><Left>645</Left><Bottom>715</Bottom><Right>1025</Right><x>645</x><y>-2</y><xscreen>190</xscreen><yscreen>190</yscreen><sizeHorzCX>118750</sizeHorzCX><sizeHorzCY>169794</sizeHorzCY><sizeVertCX>237500</sizeVertCX><sizeVertCY>640750</sizeVertCY></Rect></Wnd3></Sizes></Row1></Right><Bottom><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>151</Bottom><Right>1602</Right><x>-2</x><y>-2</y><xscreen>1604</xscreen><yscreen>153</yscreen><sizeHorzCX>1002500</sizeHorzCX><sizeHorzCY>136729</sizeHorzCY><sizeVertCX>95625</sizeVertCX><sizeVertCY>136729</sizeVertCY></Rect></Wnd2></Sizes></Row0><Row1><Sizes><Wnd4><Rect><Top>149</Top><Left>-2</Left><Bottom>333</Bottom><Right>669</Right><x>-2</x><y>149</y><xscreen>671</xscreen><yscreen>184</yscreen><sizeHorzCX>419375</sizeHorzCX><sizeHorzCY>164432</sizeHorzCY><sizeVertCX>114375</sizeVertCX><sizeVertCY>163538</sizeVertCY></Rect></Wnd4><Wnd5><Rect><Top>149</Top><Left>667</Left><Bottom>333</Bottom><Right>1602</Right><x>667</x><y>149</y><xscreen>935</xscreen><yscreen>184</yscreen><sizeHorzCX>584375</sizeHorzCX><sizeHorzCY>164432</sizeHorzCY><sizeVertCX>115000</sizeVertCX><sizeVertCY>598748</sizeVertCY></Rect></Wnd5></Sizes></Row1></Bot
tom><Float><Sizes/></Float></Positions>
</Desktop>
</Project>

23
FreeRTOS/Demo/ARM7_LPC2129_IAR/settings/Basic.dni Normal file
View File

@ -0,0 +1,23 @@
[DisAssemblyWindow]
NumStates=_ 1
State 1=_ 1
[JLinkDriver]
WatchVectorCatch=_ 0
WatchCond=_ 0
Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
[Log file]
LoggingEnabled=_ 0
LogFile=_ ""
Category=_ 0
[TermIOLog]
LoggingEnabled=_ 0
LogFile=_ ""
[Disassemble mode]
mode=0
[Breakpoints]
Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c}.141.1@1" 1 0 0 0 "" 0 ""
Count=1
[Low Level]
Pipeline mode=0
Initialized=0

62
FreeRTOS/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dbgdt Normal file
View File

@ -0,0 +1,62 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<Project>
<Desktop>
<Static>
<Workspace>
<ColumnWidths>
<Column0>181</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Disassembly>
<PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><CodeCovEnabled>0</CodeCovEnabled><MixedMode>1</MixedMode><CodeCovShow>0</CodeCovShow></Disassembly>
<Debug-Log><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Build</Factory></Window></Windows></PreferedWindows></Debug-Log>
<Build><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window></Windows></PreferedWindows></Build>
<Register>
<PreferedWindows>
<Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows>
</Register>
<QWatch><Column0>161</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></QWatch><Memory><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory><Driver-Trace><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>300</Column0></Driver-Trace><Breakpoints/><Watch><Format><struct_types/><watch_formats/></Format><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>100</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></Watch><QuickWatch><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>100</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></QuickWatch></Static>
<Windows>
<Wnd3>
<Tabs>
<Tab>
<Identity>TabID-22256-14845</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>rtosdemo</ExpandedNode><ExpandedNode>rtosdemo/Demo Source</ExpandedNode><ExpandedNode>rtosdemo/Scheduler Source</ExpandedNode><ExpandedNode>rtosdemo/System Files</ExpandedNode><ExpandedNode>rtosdemo/USBSample.c</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd3><Wnd4><Tabs><Tab><Identity>TabID-32269-5949</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab><Tab><Identity>TabID-30271-4373</Identity><TabName>Breakpoints</TabName><Factory>Breakpoints</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd4><Wnd5><Tabs><Tab><Identity>TabID-279-12558</Identity><TabName>Disassembly</TabName><Factory>Disassembly</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd5></Windows>
<Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>C:\E\temp\rc\1\Demo\ARM7_LPC2129_IAR\SrcIAR\lpc2xxx_cstartup.s</Filename><XPos>0</XPos><YPos>85</YPos><SelStart>2866</SelStart><SelEnd>2866</SelEnd></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-01284348><key>iaridepm.enu1</key></Toolbar-01284348><Toolbar-096c5668><key>debuggergui.enu1</key></Toolbar-096c5668></Sizes></Row0></Top><Left><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>646</Bottom><Right>255</Right><x>-2</x><y>-2</y><xscreen>0</xscreen><yscreen>0</yscreen><sizeHorzCX>0</sizeHorzCX><sizeHorzCY>0</sizeHorzCY><sizeVertCX>183571</sizeVertCX><sizeVertCY>659878</sizeVertCY></Rect></Wnd3></Sizes></Row0></Left><Right><Row0><Sizes><Wnd5><Rect><Top>-2</Top><Left>-2</Left><Bottom>646</Bottom><Right>198</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>142857</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>142857</sizeVertCX><sizeVertCY>659878</sizeVertCY></Rect></Wnd5></Sizes></Row0></Right><Bottom><Row0><Sizes><Wnd4><Rect><Top>-2</Top><Left>-2</Left><Bottom>292</Bottom><Right>1402</Right><x>-2</x><y>-2</y><xscreen>1404</xscreen><yscreen>294</yscreen><sizeHorzCX>1002857</sizeHorzCX><sizeHorzCY>299389</sizeHorzCY><sizeVertCX>92857</sizeVertCX><sizeVertCY>132383</sizeVertCY></Rect></Wnd4></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Project>

46
FreeRTOS/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni Normal file
View File

@ -0,0 +1,46 @@
[DisAssemblyWindow]
NumStates=_ 1
State 1=_ 1
[JLinkDriver]
WatchVectorCatch=_ 0
WatchCond=_ 0
Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
[Low Level]
Pipeline mode=1
Initialized=0
[Interrupts]
Enabled=1
[MemoryMap]
Enabled=0
TypeVolition=1
UnspecRange=1
ActionState=1
[CodeCoverage]
Enabled=_ 0
[Profiling]
Enabled=0
[StackPlugin]
Enabled=1
OverflowWarningsEnabled=1
WarningThreshold=90
SpWarningsEnabled=1
WarnHow=0
UseTrigger=1
TriggerName=main
LimitSize=0
ByteLimit=50
[Log file]
LoggingEnabled=_ 0
LogFile=_ ""
Category=_ 0
[TermIOLog]
LoggingEnabled=_ 0
LogFile=_ ""
[TraceHelper]
Enabled=0
ShowSource=1
[Disassemble mode]
mode=0
[Breakpoints]
Count=0

60
FreeRTOS/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt Normal file
View File

@ -0,0 +1,60 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<Workspace>
<ConfigDictionary>
<CurrentConfigs><Project>rtosdemo/Flash Debug</Project></CurrentConfigs></ConfigDictionary>
<Desktop>
<Static>
<Workspace>
<ColumnWidths>
<Column0>244</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Build><ColumnWidth0>18</ColumnWidth0><ColumnWidth1>1155</ColumnWidth1><ColumnWidth2>308</ColumnWidth2><ColumnWidth3>77</ColumnWidth3></Build>
<Debug-Log/>
<TerminalIO/>
<CodeCoveragePlugin/>
<Profiling/>
<Watch>
<Format>
<struct_types/>
<watch_formats/>
</Format>
</Watch>
<Disassembly><CodeCovEnabled>0</CodeCovEnabled><MixedMode>1</MixedMode><CodeCovShow>0</CodeCovShow></Disassembly><Memory><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory><Find-in-Files><ColumnWidth0>552</ColumnWidth0><ColumnWidth1>78</ColumnWidth1><ColumnWidth2>946</ColumnWidth2></Find-in-Files><Breakpoints/></Static>
<Windows>
<Wnd2>
<Tabs>
<Tab>
<Identity>TabID-17425-14382</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>rtosdemo</ExpandedNode><ExpandedNode>rtosdemo/Demo Source</ExpandedNode><ExpandedNode>rtosdemo/System Files</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-22109-27077</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-12074-10873</Identity><TabName>Breakpoints</TabName><Factory>Breakpoints</Factory><Session/></Tab><Tab><Identity>TabID-18349-15872</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab><Tab><Identity>TabID-30013-18825</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>
<Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy\Demo\ARM7_LPC2129_IAR\main.c</Filename><XPos>0</XPos><YPos>57</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-00abae00><key>iaridepm.enu1</key></Toolbar-00abae00></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>605</Bottom><Right>318</Right><x>-2</x><y>-2</y><xscreen>0</xscreen><yscreen>0</yscreen><sizeHorzCX>0</sizeHorzCX><sizeHorzCY>0</sizeHorzCY><sizeVertCX>190476</sizeVertCX><sizeVertCY>618126</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>333</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>335</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>341141</sizeHorzCY><sizeVertCX>54762</sizeVertCX><sizeVertCY>78411</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Workspace>

17
FreeRTOS/Demo/ARM7_LPC2129_IAR/settings/rtosdemo_lnk.par Normal file
View File

@ -0,0 +1,17 @@
// IAR XLINK Setup
// Autogenerated file - do not edit
%
setrangelist($evec_ADR,[0-3F]);
setrangelist($internal_ROM,[8000-FFFFF]);
setrangelist($external_ROM,[]);
setrangelist($internal_RAM,[100000-7FFFFF]);
setrangelist($external_RAM,[]);
$CSTACK_SIZE=200;
$IRQSTACK_SIZE=400;
$HEAP_SIZE=4;
$COMMANDS="";
$STACK_LOCATION="Internal RAM";
$IRQSTACK_LOCATION="Internal RAM";
$HEAP_LOCATION="Internal RAM";
$iar_saved_xclfilename="E:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\resource\rtosdemo_lnk.xcl";
%

77
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/FreeRTOSConfig.h Normal file
View File

@ -0,0 +1,77 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <lpc21xx.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned long ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configMAX_PRIORITIES ( 4 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 90 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) 13 * 1024 )
#define configMAX_TASK_NAME_LEN ( 8 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configQUEUE_REGISTRY_SIZE 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

92
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/ParTest/ParTest.c Normal file
View File

@ -0,0 +1,92 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#include "FreeRTOS.h"
#include "portable.h"
#include "partest.h"
#define partstFIRST_IO ( ( unsigned long ) 0x10000 )
#define partstNUM_LEDS ( 8 )
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* This is performed from main() as the io bits are shared with other setup
functions. */
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned long ulLED = partstFIRST_IO;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 0. Only P16 to P23 have an LED
attached. */
ulLED <<= ( unsigned long ) uxLED;
/* Set or clear the output. */
if( xValue )
{
IOSET1 = ulLED;
}
else
{
IOCLR1 = ulLED;
}
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned long ulLED = partstFIRST_IO, ulCurrentState;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED
attached. */
ulLED <<= ( unsigned long ) uxLED;
/* If this bit is already set, clear it, and vice versa. */
ulCurrentState = IOPIN1;
if( ulCurrentState & ulLED )
{
IOCLR1 = ulLED;
}
else
{
IOSET1 = ulLED;
}
}
}

83
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/RTOSDemo.Opt Normal file
View File

@ -0,0 +1,83 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.s*; *.src; *.a*)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt; *.h; *.inc)
pExt (*.plm)
CppX (*.cpp)
DaveTm { 0,0,0,0,0,0,0,0 }
Target (RTOSDemo_ARM), 0x0004 // Tools: 'ARM-ADS'
Target (RTOSDemo_THUMB), 0x0004 // Tools: 'ARM-ADS'
GRPOPT 1,(Other),1,0,0
GRPOPT 2,(FreeRTOS),0,0,0
GRPOPT 3,(Stadard Demo),0,0,0
OPTFFF 1,1,2,0,0,0,0,0,<.\Startup.s><Startup.s>
OPTFFF 1,2,1,503316480,0,0,0,0,<.\ParTest\ParTest.c><ParTest.c>
OPTFFF 1,3,1,167772162,0,143,163,0,<.\main.c><main.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,66,0,0,0,66,0,0,0,135,4,0,0,33,2,0,0 }
OPTFFF 1,4,1,0,0,0,0,0,<.\serial\serial.c><serial.c>
OPTFFF 1,5,2,0,0,0,0,0,<.\serial\serialISR.s><serialISR.s>
OPTFFF 2,6,1,0,0,0,0,0,<..\..\Source\tasks.c><tasks.c>
OPTFFF 2,7,1,0,0,0,0,0,<..\..\Source\list.c><list.c>
OPTFFF 2,8,1,754974720,0,0,0,0,<..\..\Source\queue.c><queue.c>
OPTFFF 2,9,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM7_LPC21xx\port.c><port.c>
OPTFFF 2,10,1,520093696,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c>
OPTFFF 2,11,2,301989888,0,0,0,0,<..\..\Source\portable\RVDS\ARM7_LPC21xx\portASM.s><portASM.s>
OPTFFF 3,12,1,0,0,0,0,0,<..\Common\Minimal\flash.c><flash.c>
OPTFFF 3,13,1,0,0,0,0,0,<..\Common\Minimal\comtest.c><comtest.c>
OPTFFF 3,14,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c><BlockQ.c>
OPTFFF 3,15,1,0,0,0,0,0,<..\Common\Minimal\dynamic.c><dynamic.c>
OPTFFF 3,16,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c><PollQ.c>
OPTFFF 3,17,1,0,0,0,0,0,<..\Common\Minimal\semtest.c><semtest.c>
TARGOPT 1, (RTOSDemo_ARM)
ADSCLK=12000000
OPTTT 1,1,1,0
OPTHX 1,65535,0,0,0
OPTLX 79,66,8,<.\>
OPTOX 16
OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
OPTXL 1,1,1,1,1,1,1,0,0
OPTFL 1,0,0
OPTAX 8
OPTBL 0,(Data Sheet)<DATASHTS\PHILIPS\LPC2119_2129.PDF>
OPTBL 1,(User Manual)<DATASHTS\PHILIPS\user_manual_LPC2119_2129_2194_2292_2294.PDF>
OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)
OPTDBG 49150,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=932,102,1307,529,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
OPTKEY 0,(UL2ARM)(-UU0605F6E -O47 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)
OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
OPTKEY 0,(ARMDBGFLAGS)(-T5F)
OPTDF 0x86
OPTLE <>
OPTLC <>
EndOpt
TARGOPT 2, (RTOSDemo_THUMB)
ADSCLK=12000000
OPTTT 1,1,1,0
OPTHX 1,65535,0,0,0
OPTLX 79,66,8,<.\>
OPTOX 16
OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
OPTXL 1,1,1,1,1,1,1,0,0
OPTFL 1,0,1
OPTAX 8
OPTBL 0,(Data Sheet)<DATASHTS\PHILIPS\LPC2119_2129.PDF>
OPTBL 1,(User Manual)<DATASHTS\PHILIPS\user_manual_LPC2119_2129_2194_2292_2294.PDF>
OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)
OPTDBG 49150,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
OPTKEY 0,(UL2ARM)(-UU0605F6E -O39 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO19 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)
OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
OPTKEY 0,(ARMDBGFLAGS)(-T5F)
OPTDF 0x82
OPTLE <>
OPTLC <>
EndOpt

209
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/RTOSDemo.Uv2 Normal file
View File

@ -0,0 +1,209 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (RTOSDemo_ARM), 0x0004 // Tools: 'ARM-ADS'
Target (RTOSDemo_THUMB), 0x0004 // Tools: 'ARM-ADS'
Group (Other)
Group (FreeRTOS)
Group (Stadard Demo)
File 1,2,<.\Startup.s><Startup.s>
File 1,1,<.\ParTest\ParTest.c><ParTest.c>
File 1,1,<.\main.c><main.c>
File 1,1,<.\serial\serial.c><serial.c>
File 1,2,<.\serial\serialISR.s><serialISR.s>
File 2,1,<..\..\Source\tasks.c><tasks.c>
File 2,1,<..\..\Source\list.c><list.c>
File 2,1,<..\..\Source\queue.c><queue.c>
File 2,1,<..\..\Source\portable\RVDS\ARM7_LPC21xx\port.c><port.c>
File 2,1,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c>
File 2,2,<..\..\Source\portable\RVDS\ARM7_LPC21xx\portASM.s><portASM.s>
File 3,1,<..\Common\Minimal\flash.c><flash.c>
File 3,1,<..\Common\Minimal\comtest.c><comtest.c>
File 3,1,<..\Common\Minimal\BlockQ.c><BlockQ.c>
File 3,1,<..\Common\Minimal\dynamic.c><dynamic.c>
File 3,1,<..\Common\Minimal\PollQ.c><PollQ.c>
File 3,1,<..\Common\Minimal\semtest.c><semtest.c>
Options 1,0,0 // Target 'RTOSDemo_ARM'
Device (LPC2129)
Vendor (NXP (founded by Philips))
Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))
FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1))
StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code"))
FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000))
DevID (3648)
Rgf (LPC21xx.H)
Mem ()
C ()
A ()
RL ()
OH ()
DBC_IFX ()
DBC_CMS ()
DBC_AMS ()
DBC_LMS ()
UseEnv=0
EnvBin ()
EnvInc ()
EnvLib ()
EnvReg (ÿPhilips\)
OrgReg (ÿPhilips\)
TgStat=16
OutDir (.\)
OutName (RTOSDemo)
GenApp=1
GenLib=0
GenHex=0
Debug=1
Browse=1
LstDir (.\)
HexSel=1
MG32K=0
TGMORE=0
RunUsr 0 0 <>
RunUsr 1 0 <>
BrunUsr 0 0 <>
BrunUsr 1 0 <>
CrunUsr 0 0 <>
CrunUsr 1 0 <>
SVCSID <>
GLFLAGS=1790
ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ACPUTYP (ARM7TDMI)
RVDEV ()
ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSIRAM { 0,0,0,0,64,0,64,0,0 }
OCMADSIROM { 1,0,0,0,0,0,0,4,0 }
OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0 }
RV_STAVEC ()
ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSCMISC ()
ADSCDEFN (ARM7_LPC21xx_KEIL_RVDS)
ADSCUDEF ()
ADSCINCD (.;..\..\Source\portable\RVDS\ARM7_LPC21xx;..\Common\include;..\..\Source\include)
ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSAMISC ()
ADSADEFN ()
ADSAUDEF ()
ADSAINCD (..\..\Source\portable\RVDS\ARM7_LPC21xx)
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=1
AlwaysBuild=0
GenAsm=0
AsmAsm=0
PublicsOnly=0
StopCode=3
CustArgs ()
LibMods ()
ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSLDTA (0x00000000)
ADSLDDA (0x40000000)
ADSLDSC ()
ADSLDIB ()
ADSLDIC ()
ADSLDMC ()
ADSLDIF ()
ADSLDDW ()
OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)
OPTDBG 49150,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
FLASH1 { 1,0,0,0,1,0,0,0,0,16,0,0,0,0,0,0,0,0,0,0 }
FLASH2 (BIN\UL2ARM.DLL)
FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1))
FLASH4 ()
EndOpt
Options 2,0,0 // Target 'RTOSDemo_THUMB'
Device (LPC2129)
Vendor (NXP (founded by Philips))
Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))
FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1))
StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code"))
FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000))
DevID (3648)
Rgf (LPC21xx.H)
Mem ()
C ()
A ()
RL ()
OH ()
DBC_IFX ()
DBC_CMS ()
DBC_AMS ()
DBC_LMS ()
UseEnv=0
EnvBin ()
EnvInc ()
EnvLib ()
EnvReg (ÿPhilips\)
OrgReg (ÿPhilips\)
TgStat=16
OutDir (.\bin\)
OutName (RTOSDemo)
GenApp=1
GenLib=0
GenHex=1
Debug=1
Browse=1
LstDir (.\)
HexSel=1
MG32K=0
TGMORE=0
RunUsr 0 0 <>
RunUsr 1 0 <>
BrunUsr 0 0 <>
BrunUsr 1 0 <>
CrunUsr 0 0 <>
CrunUsr 1 0 <>
SVCSID <>
GLFLAGS=1790
ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ACPUTYP (ARM7TDMI)
RVDEV ()
ADSTFLGA { 0,12,0,2,99,4,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
OCMADSIRAM { 0,0,0,0,64,0,64,0,0 }
OCMADSIROM { 1,0,0,0,0,0,0,4,0 }
OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0 }
RV_STAVEC ()
ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSCMISC ()
ADSCDEFN (ARM7_LPC21xx_KEIL_RVDS KEIL_THUMB_INTERWORK)
ADSCUDEF ()
ADSCINCD (.;..\..\Source\portable\RVDS\ARM7_LPC21xx;..\Common\include;..\..\Source\include)
ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSAMISC ()
ADSADEFN ()
ADSAUDEF ()
ADSAINCD (..\..\Source\portable\RVDS\ARM7_LPC21xx)
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=1
AlwaysBuild=0
GenAsm=0
AsmAsm=0
PublicsOnly=0
StopCode=3
CustArgs ()
LibMods ()
ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSLDTA (0x00000000)
ADSLDDA (0x40000000)
ADSLDSC ()
ADSLDIB ()
ADSLDIC ()
ADSLDMC ()
ADSLDIF ()
ADSLDDW ()
OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)
OPTDBG 49150,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
FLASH1 { 1,0,0,0,1,0,0,0,0,16,0,0,0,0,0,0,0,0,0,0 }
FLASH2 (BIN\UL2ARM.DLL)
FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1))
FLASH4 ()
EndOpt

15
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/RTOSDemo.sct Normal file
View File

@ -0,0 +1,15 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00040000 { ; load region size_region
ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x40000000 0x00004000 { ; RW data
.ANY (+RW +ZI)
}
}

35
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/RTOSDemo.tra Normal file
View File

@ -0,0 +1,35 @@
*** Creating Trace Output File 'RTOSDemo.tra' Ok.
### Preparing for ADS-LD.
### Creating ADS-LD Command Line
### List of Objects: adding '"startup.o"'
### List of Objects: adding '"partest.o"'
### List of Objects: adding '"main.o"'
### List of Objects: adding '"serial.o"'
### List of Objects: adding '"serialisr.o"'
### List of Objects: adding '"tasks.o"'
### List of Objects: adding '"list.o"'
### List of Objects: adding '"queue.o"'
### List of Objects: adding '"port.o"'
### List of Objects: adding '"heap_2.o"'
### List of Objects: adding '".\portasm.o"'
### List of Objects: adding '"flash.o"'
### List of Objects: adding '"comtest.o"'
### List of Objects: adding '"blockq.o"'
### List of Objects: adding '"dynamic.o"'
### List of Objects: adding '"pollq.o"'
### List of Objects: adding '"semtest.o"'
### ADS-LD Command completed:
--device DARMP "startup.o" "partest.o" "main.o" "serial.o" "serialisr.o" "tasks.o" "list.o" "queue.o" "port.o" "heap_2.o" ".\portasm.o" "flash.o" "comtest.o" "blockq.o" "dynamic.o" "pollq.o" "semtest.o" --strict --scatter "RTOSDemo.sct"
--autoat --summary_stderr --info summarysizes --map --xref --callgraph --symbols
--info sizes --info totals --info unused --info veneers
--list ".\RTOSDemo.map" -o "RTOSDemo.axf"### Preparing Environment (PrepEnvAds)
### ADS-LD Output File: 'RTOSDemo.axf'
### ADS-LD Command File: 'RTOSDemo.lnp'
### Checking for dirty Components...
### Creating CmdFile 'RTOSDemo.lnp', Handle=0x000002E0
### Writing '.lnp' file
### ADS-LD Command file 'RTOSDemo.lnp' is ready.
### ADS-LD: About to start ADS-LD Thread.
### ADS-LD: executed with 0 errors
### Updating obj list
### LDADS_file() completed.

674
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/RTOSDemo.uvopt Normal file
View File

@ -0,0 +1,674 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>RTOSDemo_ARM</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>0</IsCurrentTarget>
</OPTFL>
<CpuCode>8</CpuCode>
<Books>
<Book>
<Number>0</Number>
<Title>Data Sheet</Title>
<Path>DATASHTS\PHILIPS\LPC2119_2129.PDF</Path>
</Book>
<Book>
<Number>1</Number>
<Title>User Manual</Title>
<Path>DATASHTS\PHILIPS\user_manual_LPC2119_2129_2194_2292_2294.PDF</Path>
</Book>
</Books>
<DllOpt>
<SimDllName>SARM.DLL</SimDllName>
<SimDllArguments>-cLPC2100</SimDllArguments>
<SimDlgDllName>DARMP.DLL</SimDlgDllName>
<SimDlgDllArguments>-pLPC21x9</SimDlgDllArguments>
<TargetDllName>SARM.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDllName>TARMP.DLL</TargetDlgDllName>
<TargetDlgDllArguments>-pLPC21x9</TargetDlgDllArguments>
</DllOpt>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>0</tRtrace>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<nTsel>0</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\UL2ARM.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=932,102,1307,529,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2ARM</Key>
<Name>-UU0605F6E -O47 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGDARM</Key>
<Name>(134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name>-T5F</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
</TargetOption>
</Target>
<Target>
<TargetName>RTOSDemo_THUMB</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>8</CpuCode>
<Books>
<Book>
<Number>0</Number>
<Title>Data Sheet</Title>
<Path>DATASHTS\PHILIPS\LPC2119_2129.PDF</Path>
</Book>
<Book>
<Number>1</Number>
<Title>User Manual</Title>
<Path>DATASHTS\PHILIPS\user_manual_LPC2119_2129_2194_2292_2294.PDF</Path>
</Book>
</Books>
<DllOpt>
<SimDllName>SARM.DLL</SimDllName>
<SimDllArguments>-cLPC2100</SimDllArguments>
<SimDlgDllName>DARMP.DLL</SimDlgDllName>
<SimDlgDllArguments>-pLPC21x9</SimDlgDllArguments>
<TargetDllName>SARM.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDllName>TARMP.DLL</TargetDlgDllName>
<TargetDlgDllArguments>-pLPC21x9</TargetDlgDllArguments>
</DllOpt>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>0</tRtrace>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<nTsel>0</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\UL2ARM.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2ARM</Key>
<Name>-UU0605F6E -O39 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO19 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGDARM</Key>
<Name>(134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name>-T5F</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
</TargetOption>
</Target>
<Group>
<GroupName>Other</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>228</TopLine>
<CurrentLine>240</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\Startup.s</PathWithFileName>
<FilenameWithoutPath>Startup.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>30</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\ParTest\ParTest.c</PathWithFileName>
<FilenameWithoutPath>ParTest.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>78</TopLine>
<CurrentLine>179</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
<WindowPosition>
<length>44</length>
<flags>2</flags>
<showCmd>3</showCmd>
<MinPosition>
<xPos>-1</xPos>
<yPos>-1</yPos>
</MinPosition>
<MaxPosition>
<xPos>-4</xPos>
<yPos>-23</yPos>
</MaxPosition>
<NormalPosition>
<Top>66</Top>
<Left>66</Left>
<Right>1159</Right>
<Bottom>545</Bottom>
</NormalPosition>
</WindowPosition>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\serial\serial.c</PathWithFileName>
<FilenameWithoutPath>serial.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\serial\serialISR.s</PathWithFileName>
<FilenameWithoutPath>serialISR.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>FreeRTOS</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>1729</TopLine>
<CurrentLine>1735</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\tasks.c</PathWithFileName>
<FilenameWithoutPath>tasks.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\list.c</PathWithFileName>
<FilenameWithoutPath>list.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>45</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\queue.c</PathWithFileName>
<FilenameWithoutPath>queue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\portable\RVDS\ARM7_LPC21xx\port.c</PathWithFileName>
<FilenameWithoutPath>port.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>31</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\portable\MemMang\heap_2.c</PathWithFileName>
<FilenameWithoutPath>heap_2.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>11</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>97</TopLine>
<CurrentLine>130</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\..\Source\portable\RVDS\ARM7_LPC21xx\portASM.s</PathWithFileName>
<FilenameWithoutPath>portASM.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Stadard Demo</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\flash.c</PathWithFileName>
<FilenameWithoutPath>flash.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\comtest.c</PathWithFileName>
<FilenameWithoutPath>comtest.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>14</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\BlockQ.c</PathWithFileName>
<FilenameWithoutPath>BlockQ.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\dynamic.c</PathWithFileName>
<FilenameWithoutPath>dynamic.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\PollQ.c</PathWithFileName>
<FilenameWithoutPath>PollQ.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>..\Common\Minimal\semtest.c</PathWithFileName>
<FilenameWithoutPath>semtest.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
</ProjectOpt>

979
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/RTOSDemo.uvproj Normal file
View File

@ -0,0 +1,979 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
<SchemaVersion>1.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>RTOSDemo_ARM</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>LPC2129</Device>
<Vendor>NXP (founded by Philips)</Vendor>
<Cpu>IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI)</Cpu>
<FlashUtilSpec>LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1)</FlashUtilSpec>
<StartupFile>"STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code")</StartupFile>
<FlashDriverDll>UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)</FlashDriverDll>
<DeviceId>3648</DeviceId>
<RegisterFile>LPC21xx.H</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile></SFDFile>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath>Philips\</RegisterFilePath>
<DBRegisterFilePath>Philips\</DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\</OutputDirectory>
<OutputName>RTOSDemo</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
</CommonProperty>
<DllOption>
<SimDllName>SARM.DLL</SimDllName>
<SimDllArguments>-cLPC2100</SimDllArguments>
<SimDlgDll>DARMP.DLL</SimDlgDll>
<SimDlgDllArguments>-pLPC21x9</SimDlgDllArguments>
<TargetDllName>SARM.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TARMP.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pLPC21x9</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>0</RestoreTracepoints>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>0</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
<Driver>BIN\UL2ARM.DLL</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<Flash2>BIN\UL2ARM.DLL</Flash2>
<Flash3>"LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1)</Flash3>
<Flash4></Flash4>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>ARM7TDMI</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x40000000</StartAddress>
<Size>0x4000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x40000000</StartAddress>
<Size>0x4000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls></MiscControls>
<Define>ARM7_LPC21xx_KEIL_RVDS</Define>
<Undefine></Undefine>
<IncludePath>.;..\..\Source\portable\RVDS\ARM7_LPC21xx;..\Common\include;..\..\Source\include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\Source\portable\RVDS\ARM7_LPC21xx</IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x40000000</DataAddressRange>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Other</GroupName>
<Files>
<File>
<FileName>Startup.s</FileName>
<FileType>2</FileType>
<FilePath>.\Startup.s</FilePath>
</File>
<File>
<FileName>ParTest.c</FileName>
<FileType>1</FileType>
<FilePath>.\ParTest\ParTest.c</FilePath>
</File>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>.\main.c</FilePath>
</File>
<File>
<FileName>serial.c</FileName>
<FileType>1</FileType>
<FilePath>.\serial\serial.c</FilePath>
</File>
<File>
<FileName>serialISR.s</FileName>
<FileType>2</FileType>
<FilePath>.\serial\serialISR.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>FreeRTOS</GroupName>
<Files>
<File>
<FileName>tasks.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\tasks.c</FilePath>
</File>
<File>
<FileName>list.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\list.c</FilePath>
</File>
<File>
<FileName>queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\queue.c</FilePath>
</File>
<File>
<FileName>port.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\portable\RVDS\ARM7_LPC21xx\port.c</FilePath>
</File>
<File>
<FileName>heap_2.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\portable\MemMang\heap_2.c</FilePath>
</File>
<File>
<FileName>portASM.s</FileName>
<FileType>2</FileType>
<FilePath>..\..\Source\portable\RVDS\ARM7_LPC21xx\portASM.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Stadard Demo</GroupName>
<Files>
<File>
<FileName>flash.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\flash.c</FilePath>
</File>
<File>
<FileName>comtest.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\comtest.c</FilePath>
</File>
<File>
<FileName>BlockQ.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\BlockQ.c</FilePath>
</File>
<File>
<FileName>dynamic.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\dynamic.c</FilePath>
</File>
<File>
<FileName>PollQ.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\PollQ.c</FilePath>
</File>
<File>
<FileName>semtest.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\semtest.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
<Target>
<TargetName>RTOSDemo_THUMB</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>LPC2129</Device>
<Vendor>NXP (founded by Philips)</Vendor>
<Cpu>IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI)</Cpu>
<FlashUtilSpec>LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1)</FlashUtilSpec>
<StartupFile>"STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code")</StartupFile>
<FlashDriverDll>UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)</FlashDriverDll>
<DeviceId>3648</DeviceId>
<RegisterFile>LPC21xx.H</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile></SFDFile>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath>Philips\</RegisterFilePath>
<DBRegisterFilePath>Philips\</DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\bin\</OutputDirectory>
<OutputName>RTOSDemo</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
</CommonProperty>
<DllOption>
<SimDllName>SARM.DLL</SimDllName>
<SimDllArguments>-cLPC2100</SimDllArguments>
<SimDlgDll>DARMP.DLL</SimDlgDll>
<SimDlgDllArguments>-pLPC21x9</SimDlgDllArguments>
<TargetDllName>SARM.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TARMP.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pLPC21x9</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>0</RestoreTracepoints>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>0</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
<Driver>BIN\UL2ARM.DLL</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<Flash2>BIN\UL2ARM.DLL</Flash2>
<Flash3>"LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1)</Flash3>
<Flash4></Flash4>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>ARM7TDMI</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>1</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x40000000</StartAddress>
<Size>0x4000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x40000000</StartAddress>
<Size>0x4000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls></MiscControls>
<Define>ARM7_LPC21xx_KEIL_RVDS KEIL_THUMB_INTERWORK</Define>
<Undefine></Undefine>
<IncludePath>.;..\..\Source\portable\RVDS\ARM7_LPC21xx;..\Common\include;..\..\Source\include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\Source\portable\RVDS\ARM7_LPC21xx</IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x40000000</DataAddressRange>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Other</GroupName>
<Files>
<File>
<FileName>Startup.s</FileName>
<FileType>2</FileType>
<FilePath>.\Startup.s</FilePath>
</File>
<File>
<FileName>ParTest.c</FileName>
<FileType>1</FileType>
<FilePath>.\ParTest\ParTest.c</FilePath>
</File>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>.\main.c</FilePath>
</File>
<File>
<FileName>serial.c</FileName>
<FileType>1</FileType>
<FilePath>.\serial\serial.c</FilePath>
</File>
<File>
<FileName>serialISR.s</FileName>
<FileType>2</FileType>
<FilePath>.\serial\serialISR.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>FreeRTOS</GroupName>
<Files>
<File>
<FileName>tasks.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\tasks.c</FilePath>
</File>
<File>
<FileName>list.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\list.c</FilePath>
</File>
<File>
<FileName>queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\queue.c</FilePath>
</File>
<File>
<FileName>port.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\portable\RVDS\ARM7_LPC21xx\port.c</FilePath>
</File>
<File>
<FileName>heap_2.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\Source\portable\MemMang\heap_2.c</FilePath>
</File>
<File>
<FileName>portASM.s</FileName>
<FileType>2</FileType>
<FilePath>..\..\Source\portable\RVDS\ARM7_LPC21xx\portASM.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Stadard Demo</GroupName>
<Files>
<File>
<FileName>flash.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\flash.c</FilePath>
</File>
<File>
<FileName>comtest.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\comtest.c</FilePath>
</File>
<File>
<FileName>BlockQ.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\BlockQ.c</FilePath>
</File>
<File>
<FileName>dynamic.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\dynamic.c</FilePath>
</File>
<File>
<FileName>PollQ.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\PollQ.c</FilePath>
</File>
<File>
<FileName>semtest.c</FileName>
<FileType>1</FileType>
<FilePath>..\Common\Minimal\semtest.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
</Project>

40
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/RTOSDemoSignal.UVL Normal file
View File

@ -0,0 +1,40 @@
[Signal 1]
DispName=Port1
PlotType=1
Color=16711935
MinDec=0
MinVal=0.
MaxDec=0
MaxVal=-1.
Mask=65536
Offset=16
[Signal 2]
DispName=Port1
PlotType=1
Color=255
MinDec=0
MinVal=0.
MaxDec=0
MaxVal=-1.
Mask=131072
Offset=17
[Signal 3]
DispName=Port1
PlotType=1
Color=32768
MinDec=0
MinVal=0.
MaxDec=0
MaxVal=-1.
Mask=262144
Offset=18
[Signal 4]
DispName=Port1
PlotType=1
Color=16711680
MinDec=0
MinVal=0.
MaxDec=0
MaxVal=-1.
Mask=524288
Offset=19

2
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/RTOSDemo_Target 1.dep Normal file
View File

@ -0,0 +1,2 @@
Dependencies for Project 'RTOSDemo', Target 'Target 1': (DO NOT MODIFY !)
F (.\Startup.s)(0x47F4A5D0)(--device DARMP -g --apcs=interwork -I "C:\Devtools\Keil305_2\ARM\INC\Philips" --list "Startup.lst" --xref -o "Startup.o")

429
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/Startup.s Normal file
View File

@ -0,0 +1,429 @@
;/*****************************************************************************/
;/* STARTUP.S: Startup file for Philips LPC2000 */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>> */
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools. */
;/* Copyright (c) 2005-2007 Keil Software. All rights reserved. */
;/* This software may only be used under the terms of a valid, current, */
;/* end user licence from KEIL for a compatible version of KEIL software */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/
;/*
; * The STARTUP.S code is executed after CPU Reset. This file may be
; * translated with the following SET symbols. In uVision these SET
; * symbols are entered under Options - ASM - Define.
; *
; * REMAP: when set the startup code initializes the register MEMMAP
; * which overwrites the settings of the CPU configuration pins. The
; * startup and interrupt vectors are remapped from:
; * 0x00000000 default setting (not remapped)
; * 0x80000000 when EXTMEM_MODE is used
; * 0x40000000 when RAM_MODE is used
; *
; * EXTMEM_MODE: when set the device is configured for code execution
; * from external memory starting at address 0x80000000.
; *
; * RAM_MODE: when set the device is configured for code execution
; * from on-chip RAM starting at address 0x40000000.
; *
; * EXTERNAL_MODE: when set the PIN2SEL values are written that enable
; * the external BUS at startup.
; */
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>
UND_Stack_Size EQU 0x00000008
SVC_Stack_Size EQU 0x00000300
ABT_Stack_Size EQU 0x00000008
FIQ_Stack_Size EQU 0x00000008
IRQ_Stack_Size EQU 0x00000300
USR_Stack_Size EQU 0x00000008
Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size )
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
;__initial_sp SPACE ISR_Stack_Size
Stack_Top EQU Stack_Mem + Stack_Size
;// <h> Heap Configuration
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
; VPBDIV definitions
VPBDIV EQU 0xE01FC100 ; VPBDIV Address
;// <e> VPBDIV Setup
;// <i> Peripheral Bus Clock Rate
;// <o1.0..1> VPBDIV: VPB Clock
;// <0=> VPB Clock = CPU Clock / 4
;// <1=> VPB Clock = CPU Clock
;// <2=> VPB Clock = CPU Clock / 2
;// <o1.4..5> XCLKDIV: XCLK Pin
;// <0=> XCLK Pin = CPU Clock / 4
;// <1=> XCLK Pin = CPU Clock
;// <2=> XCLK Pin = CPU Clock / 2
;// </e>
VPBDIV_SETUP EQU 0
VPBDIV_Val EQU 0x00000000
; Phase Locked Loop (PLL) definitions
PLL_BASE EQU 0xE01FC080 ; PLL Base Address
PLLCON_OFS EQU 0x00 ; PLL Control Offset
PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset
PLLSTAT_OFS EQU 0x08 ; PLL Status Offset
PLLFEED_OFS EQU 0x0C ; PLL Feed Offset
PLLCON_PLLE EQU (1<<0) ; PLL Enable
PLLCON_PLLC EQU (1<<1) ; PLL Connect
PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier
PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider
PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status
;// <e> PLL Setup
;// <o1.0..4> MSEL: PLL Multiplier Selection
;// <1-32><#-1>
;// <i> M Value
;// <o1.5..6> PSEL: PLL Divider Selection
;// <0=> 1 <1=> 2 <2=> 4 <3=> 8
;// <i> P Value
;// </e>
PLL_SETUP EQU 1
PLLCFG_Val EQU 0x00000024
; Memory Accelerator Module (MAM) definitions
MAM_BASE EQU 0xE01FC000 ; MAM Base Address
MAMCR_OFS EQU 0x00 ; MAM Control Offset
MAMTIM_OFS EQU 0x04 ; MAM Timing Offset
;// <e> MAM Setup
;// <o1.0..1> MAM Control
;// <0=> Disabled
;// <1=> Partially Enabled
;// <2=> Fully Enabled
;// <i> Mode
;// <o2.0..2> MAM Timing
;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
;// <4=> 4 <5=> 5 <6=> 6 <7=> 7
;// <i> Fetch Cycles
;// </e>
MAM_SETUP EQU 1
MAMCR_Val EQU 0x00000002
MAMTIM_Val EQU 0x00000004
; External Memory Controller (EMC) definitions
EMC_BASE EQU 0xFFE00000 ; EMC Base Address
BCFG0_OFS EQU 0x00 ; BCFG0 Offset
BCFG1_OFS EQU 0x04 ; BCFG1 Offset
BCFG2_OFS EQU 0x08 ; BCFG2 Offset
BCFG3_OFS EQU 0x0C ; BCFG3 Offset
;// <e> External Memory Controller (EMC)
EMC_SETUP EQU 0
;// <e> Bank Configuration 0 (BCFG0)
;// <o1.0..3> IDCY: Idle Cycles <0-15>
;// <o1.5..9> WST1: Wait States 1 <0-31>
;// <o1.11..15> WST2: Wait States 2 <0-31>
;// <o1.10> RBLE: Read Byte Lane Enable
;// <o1.26> WP: Write Protect
;// <o1.27> BM: Burst ROM
;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
;// <2=> 32-bit <3=> Reserved
;// </e>
BCFG0_SETUP EQU 0
BCFG0_Val EQU 0x0000FBEF
;// <e> Bank Configuration 1 (BCFG1)
;// <o1.0..3> IDCY: Idle Cycles <0-15>
;// <o1.5..9> WST1: Wait States 1 <0-31>
;// <o1.11..15> WST2: Wait States 2 <0-31>
;// <o1.10> RBLE: Read Byte Lane Enable
;// <o1.26> WP: Write Protect
;// <o1.27> BM: Burst ROM
;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
;// <2=> 32-bit <3=> Reserved
;// </e>
BCFG1_SETUP EQU 0
BCFG1_Val EQU 0x0000FBEF
;// <e> Bank Configuration 2 (BCFG2)
;// <o1.0..3> IDCY: Idle Cycles <0-15>
;// <o1.5..9> WST1: Wait States 1 <0-31>
;// <o1.11..15> WST2: Wait States 2 <0-31>
;// <o1.10> RBLE: Read Byte Lane Enable
;// <o1.26> WP: Write Protect
;// <o1.27> BM: Burst ROM
;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
;// <2=> 32-bit <3=> Reserved
;// </e>
BCFG2_SETUP EQU 0
BCFG2_Val EQU 0x0000FBEF
;// <e> Bank Configuration 3 (BCFG3)
;// <o1.0..3> IDCY: Idle Cycles <0-15>
;// <o1.5..9> WST1: Wait States 1 <0-31>
;// <o1.11..15> WST2: Wait States 2 <0-31>
;// <o1.10> RBLE: Read Byte Lane Enable
;// <o1.26> WP: Write Protect
;// <o1.27> BM: Burst ROM
;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
;// <2=> 32-bit <3=> Reserved
;// </e>
BCFG3_SETUP EQU 0
BCFG3_Val EQU 0x0000FBEF
;// </e> End of EMC
; External Memory Pins definitions
PINSEL2 EQU 0xE002C014 ; PINSEL2 Address
PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3,
; D0..31, A2..23, JTAG Pins
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.
AREA RESET, CODE, READONLY
ARM
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
IMPORT vPortYieldProcessor
Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
; LDR PC, IRQ_Addr
LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SWI_Addr DCD vPortYieldProcessor
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
Undef_Handler B Undef_Handler
SWI_Handler B SWI_Handler
PAbt_Handler B PAbt_Handler
DAbt_Handler B DAbt_Handler
IRQ_Handler B IRQ_Handler
FIQ_Handler B FIQ_Handler
; Reset Handler
EXPORT Reset_Handler
Reset_Handler
; Setup External Memory Pins
IF :DEF:EXTERNAL_MODE
LDR R0, =PINSEL2
LDR R1, =PINSEL2_Val
STR R1, [R0]
ENDIF
; Setup External Memory Controller
IF EMC_SETUP <> 0
LDR R0, =EMC_BASE
IF BCFG0_SETUP <> 0
LDR R1, =BCFG0_Val
STR R1, [R0, #BCFG0_OFS]
ENDIF
IF BCFG1_SETUP <> 0
LDR R1, =BCFG1_Val
STR R1, [R0, #BCFG1_OFS]
ENDIF
IF BCFG2_SETUP <> 0
LDR R1, =BCFG2_Val
STR R1, [R0, #BCFG2_OFS]
ENDIF
IF BCFG3_SETUP <> 0
LDR R1, =BCFG3_Val
STR R1, [R0, #BCFG3_OFS]
ENDIF
ENDIF ; EMC_SETUP
; Setup VPBDIV
IF VPBDIV_SETUP <> 0
LDR R0, =VPBDIV
LDR R1, =VPBDIV_Val
STR R1, [R0]
ENDIF
; Setup PLL
IF PLL_SETUP <> 0
LDR R0, =PLL_BASE
MOV R1, #0xAA
MOV R2, #0x55
; Configure and Enable PLL
MOV R3, #PLLCFG_Val
STR R3, [R0, #PLLCFG_OFS]
MOV R3, #PLLCON_PLLE
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
; Wait until PLL Locked
PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]
ANDS R3, R3, #PLLSTAT_PLOCK
BEQ PLL_Loop
; Switch to PLL Clock
MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
ENDIF ; PLL_SETUP
; Setup MAM
IF MAM_SETUP <> 0
LDR R0, =MAM_BASE
MOV R1, #MAMTIM_Val
STR R1, [R0, #MAMTIM_OFS]
MOV R1, #MAMCR_Val
STR R1, [R0, #MAMCR_OFS]
ENDIF ; MAM_SETUP
; Memory Mapping (when Interrupt Vectors are in RAM)
MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
IF :DEF:REMAP
LDR R0, =MEMMAP
IF :DEF:EXTMEM_MODE
MOV R1, #3
ELIF :DEF:RAM_MODE
MOV R1, #2
ELSE
MOV R1, #1
ENDIF
STR R1, [R0]
ENDIF
; Initialise Interrupt System
; ...
; Setup Stack for each mode
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
; Enter the C code
IMPORT __main
LDR R0, =__main
BX R0
IF :DEF:__MICROLIB
EXPORT __heap_base
EXPORT __heap_limit
ELSE
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + IRQ_Stack_Size + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDIF
END

250
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/main.c Normal file
View File

@ -0,0 +1,250 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "partest.h"
#include "flash.h"
#include "comtest2.h"
#include "serial.h"
#include "PollQ.h"
#include "BlockQ.h"
#include "semtest.h"
#include "dynamic.h"
/*-----------------------------------------------------------*/
/* Constants to setup I/O and processor. */
#define mainTX_ENABLE ( ( unsigned long ) 0x00010000 ) /* UART1. */
#define mainRX_ENABLE ( ( unsigned long ) 0x00040000 ) /* UART1. */
#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 )
#define mainLED_TO_OUTPUT ( ( unsigned long ) 0xff0000 )
/* Constants for the ComTest demo application tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 )
#define mainCOM_TEST_LED ( 3 )
/* Priorities for the demo application tasks. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
/* Constants used by the "check" task. As described at the head of this file
the check task toggles an LED. The rate at which the LED flashes is used to
indicate whether an error has been detected or not. If the LED toggles every
3 seconds then no errors have been detected. If the rate increases to 500ms
then an error has been detected in at least one of the demo application tasks. */
#define mainCHECK_LED ( 7 )
#define mainNO_ERROR_FLASH_PERIOD ( ( TickType_t ) 3000 / portTICK_PERIOD_MS )
#define mainERROR_FLASH_PERIOD ( ( TickType_t ) 500 / portTICK_PERIOD_MS )
/*-----------------------------------------------------------*/
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static long prvCheckOtherTasksAreStillRunning( void );
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Configure the processor for use with the Keil demo board. This is very
* minimal as most of the setup is managed by the settings in the project
* file.
*/
static void prvSetupHardware( void );
/*-----------------------------------------------------------*/
/*
* Application entry point:
* Starts all the other tasks, then starts the scheduler.
*/
int main( void )
{
/* Setup the hardware for use with the Keil demo board. */
prvSetupHardware();
/* Start the demo/test application tasks. */
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartDynamicPriorityTasks();
/* Start the check task - which is defined in this file. This is the task
that periodically checks to see that all the other tasks are executing
without error. */
xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Now all the tasks have been started - start the scheduler.
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used here. */
vTaskStartScheduler();
/* Should never reach here! If you do then there was not enough heap
available for the idle task to be created. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
TickType_t xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
/* Parameters are not used. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. If an error is detected then the delay period
is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
the on board LED flash rate will increase.
This task runs at the highest priority. */
for( ;; )
{
/* The period of the delay depends on whether an error has been
detected or not. If an error has been detected then the period
is reduced to increase the LED flash rate. */
vTaskDelay( xDelayPeriod );
if( prvCheckOtherTasksAreStillRunning() != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
/* Toggle the LED before going back to wait for the next cycle. */
vParTestToggleLED( mainCHECK_LED );
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Perform the hardware setup required. This is minimal as most of the
setup is managed by the settings in the project file. */
/* Configure the UART1 pins. All other pins remain at their default of 0. */
PINSEL0 |= mainTX_ENABLE;
PINSEL0 |= mainRX_ENABLE;
/* LED pins need to be output. */
IODIR1 = mainLED_TO_OUTPUT;
/* Setup the peripheral bus to be the same as the PLL output. */
VPBDIV = mainBUS_CLK_FULL;
}
/*-----------------------------------------------------------*/
static long prvCheckOtherTasksAreStillRunning( void )
{
long lReturn = pdPASS;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none of them have detected
an error. */
if( xAreComTestTasksStillRunning() != pdPASS )
{
lReturn = pdFAIL;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
return lReturn;
}
/*-----------------------------------------------------------*/

306
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/serial/serial.c Normal file
View File

@ -0,0 +1,306 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
Note this driver is used to test the FreeRTOS port. It is NOT intended to
be an example of an efficient implementation!
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Constants to setup and access the UART. */
#define serDLAB ( ( unsigned char ) 0x80 )
#define serENABLE_INTERRUPTS ( ( unsigned char ) 0x03 )
#define serNO_PARITY ( ( unsigned char ) 0x00 )
#define ser1_STOP_BIT ( ( unsigned char ) 0x00 )
#define ser8_BIT_CHARS ( ( unsigned char ) 0x03 )
#define serFIFO_ON ( ( unsigned char ) 0x01 )
#define serCLEAR_FIFO ( ( unsigned char ) 0x06 )
#define serWANTED_CLOCK_SCALING ( ( unsigned long ) 16 )
/* Constants to setup and access the VIC. */
#define serU1VIC_CHANNEL ( ( unsigned long ) 0x0007 )
#define serU1VIC_CHANNEL_BIT ( ( unsigned long ) 0x0080 )
#define serU1VIC_ENABLE ( ( unsigned long ) 0x0020 )
/* Misc. */
#define serINVALID_QUEUE ( ( QueueHandle_t ) 0 )
#define serHANDLE ( ( xComPortHandle ) 1 )
#define serNO_BLOCK ( ( TickType_t ) 0 )
/* Constant to access the VIC. */
#define serCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )
/* Constants to determine the ISR source. */
#define serSOURCE_THRE ( ( unsigned char ) 0x02 )
#define serSOURCE_RX_TIMEOUT ( ( unsigned char ) 0x0c )
#define serSOURCE_ERROR ( ( unsigned char ) 0x06 )
#define serSOURCE_RX ( ( unsigned char ) 0x04 )
#define serINTERRUPT_SOURCE_MASK ( ( unsigned char ) 0x0f )
#define serINTERRUPT_IS_PENDING ( ( unsigned char ) 0x01 )
/*-----------------------------------------------------------*/
/*
* The asm wrapper for the interrupt service routine.
*/
extern void vUART_ISREntry( void );
/*
* The C function called from the asm wrapper.
*/
void vUART_ISRHandler( void );
/*-----------------------------------------------------------*/
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static QueueHandle_t xRxedChars;
static QueueHandle_t xCharsForTx;
/* Communication flag between the interrupt service routine and serial API. */
static volatile long lTHREEmpty;
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned long ulDivisor, ulWantedClock;
xComPortHandle xReturn = serHANDLE;
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
/* Initialise the THRE empty flag. */
lTHREEmpty = pdTRUE;
if(
( xRxedChars != serINVALID_QUEUE ) &&
( xCharsForTx != serINVALID_QUEUE ) &&
( ulWantedBaud != ( unsigned long ) 0 )
)
{
portENTER_CRITICAL()
{
/* Setup the baud rate: Calculate the divisor value. */
ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;
ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;
/* Set the DLAB bit so we can access the divisor. */
U1LCR |= serDLAB;
/* Setup the divisor. */
U1DLL = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );
ulDivisor >>= 8;
U1DLM = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );
/* Turn on the FIFO's and clear the buffers. */
U1FCR = ( serFIFO_ON | serCLEAR_FIFO );
/* Setup transmission format. */
U1LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;
/* Setup the VIC for the UART. */
VICIntSelect &= ~( serU1VIC_CHANNEL_BIT );
VICIntEnable |= serU1VIC_CHANNEL_BIT;
VICVectAddr1 = ( unsigned long ) vUART_ISREntry;
VICVectCntl1 = serU1VIC_CHANNEL | serU1VIC_ENABLE;
/* Enable UART0 interrupts. */
U1IER |= serENABLE_INTERRUPTS;
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
{
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
{
signed char *pxNext;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
( void ) usStringLength;
/* Send each character in the string, one at a time. */
pxNext = ( signed char * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
{
signed portBASE_TYPE xReturn;
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
portENTER_CRITICAL();
{
/* Is there space to write directly to the UART? */
if( lTHREEmpty == ( long ) pdTRUE )
{
/* We wrote the character directly to the UART, so was
successful. */
lTHREEmpty = pdFALSE;
U1THR = cOutChar;
xReturn = pdPASS;
}
else
{
/* We cannot write directly to the UART, so queue the character.
Block for a maximum of xBlockTime if there is no space in the
queue. It is ok to block within a critical section as each
task has it's own critical section management. */
xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
/* Depending on queue sizing and task prioritisation: While we
were blocked waiting to post interrupts were not disabled. It is
possible that the serial ISR has emptied the Tx queue, in which
case we need to start the Tx off again. */
if( lTHREEmpty == ( long ) pdTRUE )
{
xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
lTHREEmpty = pdFALSE;
U1THR = cOutChar;
}
}
}
portEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
void vUART_ISRHandler( void )
{
signed char cChar;
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
unsigned char ucInterrupt;
ucInterrupt = U1IIR;
/* The interrupt pending bit is active low. */
while( ( ucInterrupt & serINTERRUPT_IS_PENDING ) == 0 )
{
/* What caused the interrupt? */
switch( ucInterrupt & serINTERRUPT_SOURCE_MASK )
{
case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */
cChar = U1LSR;
break;
case serSOURCE_THRE : /* The THRE is empty. If there is another
character in the Tx queue, send it now. */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
{
U1THR = cChar;
}
else
{
/* There are no further characters
queued to send so we can indicate
that the THRE is available. */
lTHREEmpty = pdTRUE;
}
break;
case serSOURCE_RX_TIMEOUT :
case serSOURCE_RX : /* A character was received. Place it in
the queue of received characters. */
cChar = U1RBR;
xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
break;
default : /* There is nothing to do, leave the ISR. */
break;
}
ucInterrupt = U1IIR;
}
/* Clear the ISR in the VIC. */
VICVectAddr = serCLEAR_VIC_INTERRUPT;
/* Exit the ISR. If a task was woken by either a character being received
or transmitted then a context switch will occur. */
portEXIT_SWITCHING_ISR( xHigherPriorityTaskWoken );
}
/*-----------------------------------------------------------*/

63
FreeRTOS/Demo/ARM7_LPC2129_Keil_RVDS/serial/serialISR.s Normal file
View File

@ -0,0 +1,63 @@
;/*
; * FreeRTOS V202111.00
; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
; * the Software without restriction, including without limitation the rights to
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
; * the Software, and to permit persons to whom the Software is furnished to do so,
; * subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all
; * copies or substantial portions of the Software.
; *
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; *
; * http://www.FreeRTOS.org
; * http://aws.amazon.com/freertos
; *
; * 1 tab == 4 spaces!
; */
INCLUDE portmacro.inc
;The UART interrupt entry point is defined within an assembly wrapper
;within this file. This takes care of the task context saving before it
;calls the main handler (vUART_ISRHandler()) which is written in C within
;serial.c. The execution of the handler can unblock tasks that were blocked
;waiting for UART events. Once the handler completes the asm wrapper
;finishes off by restoring the context of whichever task is now selected to
;enter the RUNNING state (which might now be a different task to that which
;was originally interrupted.
IMPORT vUART_ISRHandler
EXPORT vUART_ISREntry
;/* Interrupt entry must always be in ARM mode. */
ARM
AREA |.text|, CODE, READONLY
vUART_ISREntry
PRESERVE8
; Save the context of the interrupted task.
portSAVE_CONTEXT
; Call the C handler function - defined within serial.c.
LDR R0, =vUART_ISRHandler
MOV LR, PC
BX R0
; Finish off by restoring the context of the task that has been chosen to
; run next - which might be a different task to that which was originally
; interrupted.
portRESTORE_CONTEXT
END

94
FreeRTOS/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h Normal file
View File

@ -0,0 +1,94 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <LPC21xx.h>
#define vPortYieldProcessor swi_handler
/* For compatibility with the LPC2106 header. */
#define T0_IR T0IR
#define T0_PR T0PR
#define T0_MR0 T0MR0
#define T0_MCR T0MCR
#define T0_TCR T0TCR
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
/* In this case configCPU_CLOCK_HZ is actually set to the pclk frequency, not
the CPU frequency. */
#define configCPU_CLOCK_HZ ( 58982400UL ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configMAX_PRIORITIES ( 6 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 128 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 15 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configUSE_RECURSIVE_MUTEXES 1
#define configCHECK_FOR_STACK_OVERFLOW 2
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_eTaskGetState 1
/* This demo makes use of one or more example stats formatting functions. These
format the raw data provided by the uxTaskGetSystemState() function in to human
readable ASCII form. See the notes in the implementation of vTaskList() within
FreeRTOS/Source/tasks.c for limitations. */
#define configUSE_STATS_FORMATTING_FUNCTIONS 1
#endif /* FREERTOS_CONFIG_H */

5599
FreeRTOS/Demo/ARM7_LPC2138_Rowley/LPC21xx.h Normal file
View File

File diff suppressed because it is too large Load Diff

57
FreeRTOS/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzp Normal file
View File

@ -0,0 +1,57 @@
<!DOCTYPE CrossStudio_Project_File>
<solution Name="RTOSDemo" version="2">
<project Name="RTOSDemo">
<configuration Name="Common" Target="LPC2138" arm_architecture="v4T" arm_core_type="ARM7TDMI-S" arm_simulator_memory_simulation_filename="$(TargetsDir)/Philips_LPC210X/LPC2000SimulatorMemory.dll" arm_simulator_memory_simulation_parameter="LPC21;0x80000;0x10000" arm_target_debug_interface_type="ARM7TDI" arm_target_loader_parameter="14745600" c_only_additional_options="-Wall;-Wextra" gcc_entry_point="reset_handler" link_include_startup_code="No" linker_additional_files="$(PackagesDir)/lib/liblpc2000$(LibExt)$(LIB)" linker_memory_map_file="$(TargetsDir)/Philips_LPC210X/Philips_LPC2138_MemoryMap.xml" oscillator_frequency="14.7456MHz" project_directory="" project_type="Executable" property_groups_file_path="$(TargetsDir)/Philips_LPC210X/propertyGroups.xml"/>
<configuration Name="RAM" Placement="RAM" linker_section_placement_file="$(StudioDir)/targets/sram_placement.xml" target_reset_script="SRAMReset()"/>
<configuration Name="Flash" Placement="Flash" arm_target_flash_loader_file_path="$(TargetsDir)/Philips_LPC210X/Release/Loader.elf" arm_target_flash_loader_type="Comms Channel Loader" linker_section_placement_file="$(StudioDir)/targets/flash_placement.xml" target_reset_script="FLASHReset()"/>
<folder Name="Source Files">
<configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc"/>
<folder Name="RTOS Source">
<file Name="tasks.c" file_name="../../Source/tasks.c">
<configuration Name="THUMB Flash Debug" build_exclude_from_build="No"/>
</file>
<file Name="list.c" file_name="../../Source/list.c"/>
<file Name="queue.c" file_name="../../Source/queue.c"/>
<file Name="heap_1.c" file_name="../../Source/portable/MemMang/heap_1.c"/>
<file Name="portISR.c" file_name="../../Source/portable/GCC/ARM7_LPC2000/portISR.c">
<configuration Name="THUMB" arm_instruction_set="ARM"/>
</file>
<file Name="port.c" file_name="../../Source/portable/GCC/ARM7_LPC2000/port.c"/>
</folder>
<folder Name="Demo Source">
<file Name="main.c" file_name="main.c"/>
<file Name="PollQ.c" file_name="../Common/Minimal/PollQ.c"/>
<file Name="BlockQ.c" file_name="../Common/Minimal/BlockQ.c"/>
<file Name="death.c" file_name="../Common/Minimal/death.c"/>
<file Name="dynamic.c" file_name="../Common/Minimal/dynamic.c"/>
<file Name="integer.c" file_name="../Common/Minimal/integer.c"/>
<file Name="semtest.c" file_name="../Common/Minimal/semtest.c"/>
<file Name="mainISR.c" file_name="mainISR.c">
<configuration Name="THUMB" arm_instruction_set="ARM"/>
</file>
<file Name="blocktim.c" file_name="../Common/Minimal/blocktim.c"/>
<file Name="recmutex.c" file_name="../Common/Minimal/recmutex.c"/>
</folder>
</folder>
<folder Name="System Files">
<file Name="crt0.s" file_name="$(StudioDir)/source/crt0.s"/>
<file Name="Philips_LPC210X_Startup.s" file_name="$(TargetsDir)/Philips_LPC210X/Philips_LPC210X_Startup.s"/>
<file Name="Philips_LPC210X_Target.js" file_name="$(TargetsDir)/Philips_LPC210X/Philips_LPC210X_Target.js">
<configuration Name="Common" file_type="Reset Script"/>
</file>
</folder>
<file Name="threads.js" file_name="threads.js"/>
<configuration Name="THUMB Flash Debug" build_quietly="No" c_only_additional_options=""/>
<configuration Name="Release" gcc_optimization_level="Level 3"/>
</project>
<configuration Name="ARM Flash Debug" inherited_configurations="ARM;Flash;Debug"/>
<configuration Name="ARM" arm_instruction_set="ARM" arm_library_instruction_set="ARM" c_preprocessor_definitions="__ARM" hidden="Yes"/>
<configuration Name="Flash" c_preprocessor_definitions="__FLASH_BUILD" hidden="Yes"/>
<configuration Name="Debug" build_debug_information="Yes" c_preprocessor_definitions="DEBUG" gcc_optimization_level="None" hidden="Yes" link_include_startup_code="No"/>
<configuration Name="ARM Flash Release" inherited_configurations="ARM;Flash;Release"/>
<configuration Name="Release" build_debug_information="No" c_preprocessor_definitions="NDEBUG;STARTUP_FROM_RESET" gcc_optimization_level="Level 1" hidden="Yes" link_include_startup_code="No"/>
<configuration Name="THUMB Flash Debug" inherited_configurations="THUMB;Flash;Debug"/>
<configuration Name="THUMB" arm_instruction_set="THUMB" arm_library_instruction_set="THUMB" c_preprocessor_definitions="__THUMB;THUMB_INTERWORK" hidden="Yes"/>
<configuration Name="THUMB Flash Release" inherited_configurations="THUMB;Flash;Release"/>
<configuration Name="Common" c_additional_options="-fomit-frame-pointer" c_preprocessor_definitions="GCC_ARM7;SUPERVISOR_START;VECTORED_IRQ_INTERRUPTS" c_system_include_directories="$(StudioDir)/include;$(StudioDir)/include/targets" c_user_include_directories=".;..\\..\\Source\\include;..\\..\\Source\\GCC\\ARM7_LPC2000;..\\Common\\Include"/>
</solution>

62
FreeRTOS/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzs Normal file
View File

@ -0,0 +1,62 @@
<!DOCTYPE CrossStudio_for_ARM_Session_File>
<session>
<Bookmarks/>
<Breakpoints/>
<ExecutionCountWindow/>
<Memory1>
<MemoryWindow autoEvaluate="0" addressText="0x102248" numColumns="8" sizeText="128" dataSize="1" radix="16" addressSpace="" />
</Memory1>
<Memory2>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
</Memory2>
<Memory3>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
</Memory3>
<Memory4>
<MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
</Memory4>
<Project>
<ProjectSessionItem path="RTOSDemo" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;RTOSDemo" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;RTOSDemo;Source Files" name="unnamed" />
<ProjectSessionItem path="RTOSDemo;RTOSDemo;Source Files;Demo Source" name="unnamed" />
</Project>
<Register1>
<RegisterWindow openNodes="CPU - Current Mode;CPU - Current Mode/cpsr" binaryNodes="" unsignedNodes="" visibleGroups="CPU - Current Mode" decimalNodes="" octalNodes="" asciiNodes="" />
</Register1>
<Register2>
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
</Register2>
<Register3>
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
</Register3>
<Register4>
<RegisterWindow openNodes="" binaryNodes="" unsignedNodes="" visibleGroups="" decimalNodes="" octalNodes="" asciiNodes="" />
</Register4>
<TargetWindow programAction="" uploadFileType="" programLoadAddress="" programSize="" uploadFileName="" uploadMemoryInterface="" programFileName="" uploadStartAddress="" programFileType="" uploadSize="" programMemoryInterface="" />
<TraceWindow>
<Trace enabled="Yes" />
</TraceWindow>
<Watch1>
<Watches active="1" update="Never" >
<Watchpoint evalMode="1" linenumber="0" evalType="1" radix="-1" name="pxCurrentTCB" expression="pxCurrentTCB" filename="" />
</Watches>
</Watch1>
<Watch2>
<Watches active="0" update="Never" />
</Watch2>
<Watch3>
<Watches active="0" update="Never" />
</Watch3>
<Watch4>
<Watches active="0" update="Never" >
<Watchpoint evalMode="1" linenumber="0" evalType="1" radix="-1" name="(xQUEUE *)xMutex" expression="(xQUEUE *)xMutex" filename="" />
<Watchpoint evalMode="1" linenumber="0" evalType="1" radix="-1" name="pxCurrentTCB" expression="pxCurrentTCB" filename="" />
<Watchpoint evalMode="1" linenumber="0" evalType="1" radix="16" name="pxMutex" expression="pxMutex" filename="" />
</Watches>
</Watch4>
<Files>
<SessionOpenFile useTextEdit="1" useBinaryEdit="0" codecName="Latin1" x="0" debugPath="C:\E\Dev\FreeRTOS\WorkingCopy\Demo\ARM7_LPC2138_Rowley\main.c" y="391" path="C:\E\Dev\FreeRTOS\WorkingCopy\Demo\ARM7_LPC2138_Rowley\main.c" left="0" selected="1" name="unnamed" top="42" />
</Files>
<ARMCrossStudioWindow activeProject="RTOSDemo" autoConnectTarget="USB CrossConnect for ARM" debugSearchFileMap="" fileDialogInitialDirectory="C:\E\Dev\FreeRTOS\Demo\Common\Minimal" fileDialogDefaultFilter="*.*" autoConnectCapabilities="388479" debugSearchPath="" buildConfiguration="ARM Flash Debug" />
</session>

380
FreeRTOS/Demo/ARM7_LPC2138_Rowley/main.c Normal file
View File

@ -0,0 +1,380 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/*
* This file contains a demo created to execute on the Rowley Associates
* LPC2138 CrossFire development board.
*
* main() creates all the demo application tasks, then starts the scheduler.
* The WEB documentation provides more details of the standard demo application
* tasks.
*
* Main.c also creates a task called "Check". This only executes every few
* seconds but has a high priority so is guaranteed to get processor time.
* Its function is to check that all the other tasks are still operational.
* Each standard demo task maintains a unique count that is incremented each
* time the task successfully completes its function. Should any error occur
* within such a task the count is permanently halted. The check task inspects
* the count of each task to ensure it has changed since the last time the
* check task executed. If all the count variables have changed all the tasks
* are still executing error free, and the check task writes "PASS" to the
* CrossStudio terminal IO window. Should any task contain an error at any time
* the error is latched and "FAIL" written to the terminal IO window.
*
* Finally, main() sets up an interrupt service routine and task to handle
* pushes of the button that is built into the CrossFire board. When the button
* is pushed the ISR wakes the button task - which generates a table of task
* status information which is also displayed on the terminal IO window.
*
* A print task is defined to ensure exclusive and consistent access to the
* terminal IO. This is the only task that is allowed to access the terminal.
* The check and button task therefore do not access the terminal directly but
* instead pass a pointer to the message they wish to display to the print task.
*/
/* Standard includes. */
#include <__cross_studio_io.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
/* Demo app includes. */
#include "BlockQ.h"
#include "death.h"
#include "dynamic.h"
#include "integer.h"
#include "PollQ.h"
#include "blocktim.h"
#include "recmutex.h"
#include "semtest.h"
/* Hardware configuration definitions. */
#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 )
#define mainLED_BIT 0x80000000
#define mainP0_14__EINT_1 ( 2 << 28 )
#define mainEINT_1_EDGE_SENSITIVE 2
#define mainEINT_1_FALLING_EDGE_SENSITIVE 0
#define mainEINT_1_CHANNEL 15
#define mainEINT_1_VIC_CHANNEL_BIT ( 1 << mainEINT_1_CHANNEL )
#define mainEINT_1_ENABLE_BIT ( 1 << 5 )
/* Demo application definitions. */
#define mainQUEUE_SIZE ( 3 )
#define mainLED_DELAY ( ( TickType_t ) 500 / portTICK_PERIOD_MS )
#define mainERROR_LED_DELAY ( ( TickType_t ) 50 / portTICK_PERIOD_MS )
#define mainCHECK_DELAY ( ( TickType_t ) 5000 / portTICK_PERIOD_MS )
#define mainLIST_BUFFER_SIZE 2048
#define mainNO_DELAY ( 0 )
#define mainSHORT_DELAY ( 150 / portTICK_PERIOD_MS )
/* Task priorities. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainPRINT_TASK_PRIORITY ( tskIDLE_PRIORITY + 0 )
/*-----------------------------------------------------------*/
/* The semaphore used to wake the button task from within the external interrupt
handler. */
SemaphoreHandle_t xButtonSemaphore;
/* The queue that is used to send message to vPrintTask for display in the
terminal output window. */
QueueHandle_t xPrintQueue;
/* The rate at which the LED will toggle. The toggle rate increases if an
error is detected in any task. */
static TickType_t xLED_Delay = mainLED_DELAY;
/*-----------------------------------------------------------*/
/*
* Simply flashes the on board LED every mainLED_DELAY milliseconds.
*/
static void vLEDTask( void *pvParameters );
/*
* Checks the status of all the demo tasks then prints a message to the
* CrossStudio terminal IO windows. The message will be either PASS or FAIL
* depending on the status of the demo applications tasks. A FAIL status will
* be latched.
*
* Messages are not written directly to the terminal, but passed to vPrintTask
* via a queue.
*/
static void vCheckTask( void *pvParameters );
/*
* Controls all terminal output. If a task wants to send a message to the
* terminal IO it posts a pointer to the text to vPrintTask via a queue. This
* ensures serial access to the terminal IO.
*/
static void vPrintTask( void *pvParameter );
/*
* Simply waits for an interrupt to be generated from the built in button, then
* generates a table of tasks states that is then written by vPrintTask to the
* terminal output window within CrossStudio.
*/
static void vButtonHandlerTask( void *pvParameters );
/*-----------------------------------------------------------*/
int main( void )
{
/* Setup the peripheral bus to be the same as the PLL output. */
VPBDIV = mainBUS_CLK_FULL;
/* Create the queue used to pass message to vPrintTask. */
xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( char * ) );
/* Create the semaphore used to wake vButtonHandlerTask(). */
vSemaphoreCreateBinary( xButtonSemaphore );
xSemaphoreTake( xButtonSemaphore, 0 );
/* Start the standard demo tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartDynamicPriorityTasks();
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
#if configUSE_PREEMPTION == 1
{
/* The timing of console output when not using the preemptive
scheduler causes the block time tests to detect a timing problem. */
vCreateBlockTimeTasks();
}
#endif
vStartRecursiveMutexTasks();
/* Start the tasks defined within this file. */
xTaskCreate( vLEDTask, "LED", configMINIMAL_STACK_SIZE, NULL, mainLED_TASK_PRIORITY, NULL );
xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainPRINT_TASK_PRIORITY, NULL );
xTaskCreate( vButtonHandlerTask, "Button", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Start the scheduler. */
vTaskStartScheduler();
/* The scheduler should now be running, so we will only ever reach here if we
ran out of heap space. */
return 0;
}
/*-----------------------------------------------------------*/
static void vLEDTask( void *pvParameters )
{
/* Just to remove compiler warnings. */
( void ) pvParameters;
/* Configure IO. */
IO0DIR |= mainLED_BIT;
IO0SET = mainLED_BIT;
for( ;; )
{
/* Not very exiting - just delay... */
vTaskDelay( xLED_Delay );
/* ...set the IO ... */
IO0CLR = mainLED_BIT;
/* ...delay again... */
vTaskDelay( xLED_Delay );
/* ...then clear the IO. */
IO0SET = mainLED_BIT;
}
}
/*-----------------------------------------------------------*/
static void vCheckTask( void *pvParameters )
{
portBASE_TYPE xErrorOccurred = pdFALSE;
TickType_t xLastExecutionTime;
const char * const pcPassMessage = "PASS\n";
const char * const pcFailMessage = "FAIL\n";
/* Just to remove compiler warnings. */
( void ) pvParameters;
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
works correctly. */
xLastExecutionTime = xTaskGetTickCount();
for( ;; )
{
/* Perform this check every mainCHECK_DELAY milliseconds. */
vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY );
/* Has an error been found in any task? */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
#if configUSE_PREEMPTION == 1
{
/* The timing of console output when not using the preemptive
scheduler causes the block time tests to detect a timing problem. */
if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
}
#endif
if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
xErrorOccurred = pdTRUE;
}
/* Send either a pass or fail message. If an error is found it is
never cleared again. */
if( xErrorOccurred == pdTRUE )
{
xLED_Delay = mainERROR_LED_DELAY;
xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY );
}
else
{
xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY );
}
}
}
/*-----------------------------------------------------------*/
static void vPrintTask( void *pvParameters )
{
char *pcMessage;
/* Just to stop compiler warnings. */
( void ) pvParameters;
for( ;; )
{
/* Wait for a message to arrive. */
while( xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ) != pdPASS );
/* Write the message to the terminal IO. */
#ifndef NDEBUG
debug_printf( "%s", pcMessage );
#endif
}
}
/*-----------------------------------------------------------*/
static void vButtonHandlerTask( void *pvParameters )
{
static char cListBuffer[ mainLIST_BUFFER_SIZE ];
const char *pcList = &( cListBuffer[ 0 ] );
const char * const pcHeader = "\nTask State Priority Stack #\n************************************************";
extern void (vButtonISRWrapper) ( void );
/* Just to stop compiler warnings. */
( void ) pvParameters;
/* Configure the interrupt. */
portENTER_CRITICAL();
{
/* Configure P0.14 to generate interrupts. */
PINSEL0 |= mainP0_14__EINT_1;
EXTMODE = mainEINT_1_EDGE_SENSITIVE;
EXTPOLAR = mainEINT_1_FALLING_EDGE_SENSITIVE;
/* Setup the VIC for EINT 1. */
VICIntSelect &= ~mainEINT_1_VIC_CHANNEL_BIT;
VICIntEnable |= mainEINT_1_VIC_CHANNEL_BIT;
VICVectAddr1 = ( long ) vButtonISRWrapper;
VICVectCntl1 = mainEINT_1_ENABLE_BIT | mainEINT_1_CHANNEL;
}
portEXIT_CRITICAL();
for( ;; )
{
/* For debouncing, wait a while then clear the semaphore. */
vTaskDelay( mainSHORT_DELAY );
xSemaphoreTake( xButtonSemaphore, mainNO_DELAY );
/* Wait for an interrupt. */
xSemaphoreTake( xButtonSemaphore, portMAX_DELAY );
/* Send the column headers to the print task for display. */
xQueueSend( xPrintQueue, &pcHeader, portMAX_DELAY );
/* Create the list of task states. */
vTaskList( cListBuffer );
/* Send the task status information to the print task for display. */
xQueueSend( xPrintQueue, &pcList, portMAX_DELAY );
}
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
{
/* Check pcTaskName for the name of the offending task, or pxCurrentTCB
if pcTaskName has itself been corrupted. */
( void ) pxTask;
( void ) pcTaskName;
for( ;; );
}

77
FreeRTOS/Demo/ARM7_LPC2138_Rowley/mainISR.c Normal file
View File

@ -0,0 +1,77 @@
/*
* FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#include "FreeRTOS.h"
#include "semphr.h"
#define isrCLEAR_EINT_1 2
/*
* Interrupt routine that simply wakes vButtonHandlerTask on each interrupt
* generated by a push of the built in button. The wrapper takes care of
* the ISR entry. This then calls the actual handler function to perform
* the work. This work should not be done in the wrapper itself unless
* you are absolutely sure that no stack space is used.
*/
void vButtonISRWrapper( void ) __attribute__ ((naked));
void vButtonHandler( void ) __attribute__ ((noinline));
void vButtonHandler( void )
{
extern SemaphoreHandle_t xButtonSemaphore;
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
xSemaphoreGiveFromISR( xButtonSemaphore, &xHigherPriorityTaskWoken );
if( xHigherPriorityTaskWoken )
{
/* We have woken a task. Calling "yield from ISR" here will ensure
the interrupt returns to the woken task if it has a priority higher
than the interrupted task. */
portYIELD_FROM_ISR();
}
EXTINT = isrCLEAR_EINT_1;
VICVectAddr = 0;
}
/*-----------------------------------------------------------*/
void vButtonISRWrapper( void )
{
/* Save the context of the interrupted task. */
portSAVE_CONTEXT();
/* Call the handler to do the work. This must be a separate function to
the wrapper to ensure the correct stack frame is set up. */
__asm volatile( "bl vButtonHandler" );
/* Restore the context of whichever task is going to run once the interrupt
completes. */
portRESTORE_CONTEXT();
}

105
FreeRTOS/Demo/ARM7_LPC2138_Rowley/threads.js Normal file
View File

@ -0,0 +1,105 @@
function decode_stack(sp)
{
var i;
var a = new Array();
sp += 4; /* skip stored ulCriticalNesting */
a[16] = Debug.evaluate("*(unsigned long*)" + sp);
for (i = 0; i <= 15; i++)
{
sp += 4;
a[i] = Debug.evaluate("*(unsigned long*)" + sp);
}
return a;
}
function add_task(task, state)
{
var tcb, task_name, current_task, regs;
current_task = Debug.evaluate("pxCurrentTCB");
tcb = Debug.evaluate("*(tskTCB *)" + task);
task_name = Debug.evaluate("(char*)&(*(tskTCB *)" + task + ").pcTaskName[0]");
task_name = "#" + tcb.uxTCBNumber + " \"" + task_name + "\"";
if (task == current_task)
{
state = "executing";
regs = [];
}
else
{
regs = decode_stack(tcb.pxTopOfStack);
}
Threads.add(task_name, tcb.uxPriority, state, regs);
}
function add_list(list, state)
{
var i, index, item, task;
if (list && list.uxNumberOfItems>0)
{
index = list.xListEnd.pxNext;
for (i = 0; i < list.uxNumberOfItems; i++)
{
item = Debug.evaluate("*(ListItem_t *)" + index);
task = item ? item.pvOwner : 0;
if (task)
add_task(task, state);
index = item.pxNext;
}
}
}
function update()
{
var i, list, lists, max_priority;
Threads.clear();
if( Debug.evaluate("pxCurrentTCB") == 0 )
return;
max_priority = Debug.evaluate("uxTopUsedPriority");
Threads.newqueue("Ready");
for (i = max_priority; i >= 0; i--)
{
list = Debug.evaluate("pxReadyTasksLists[" + i + "]");
add_list(list, "ready");
}
Threads.newqueue("Blocked");
list = Debug.evaluate("pxDelayedTaskList");
if (list)
{
list = Debug.evaluate("*(xList *)" + list);
add_list(list, "blocked");
}
list = Debug.evaluate("pxOverflowDelayedTaskList");
if (list)
{
list = Debug.evaluate("*(xList *)" + list);
add_list(list, "blocked");
}
Threads.newqueue("Suspended");
list = Debug.evaluate("xSuspendedTaskList");
if (list)
{
add_list(list, "suspended");
}
}

Some files were not shown because too many files have changed in this diff Show More