alwin.berger/FRET-LibAFL
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Commit Graph

  • 01d90db599 target/arm: Use tcg_constant in translate-m-nocp.c Richard Henderson 2022-04-17 10:43:44 -07:00
  • c89a9d139b target/arm: Simplify aa32 DISAS_WFI Richard Henderson 2022-04-17 10:43:42 -07:00
  • 099d1c2088 target/arm: Simplify gen_sar Richard Henderson 2022-04-17 10:43:41 -07:00
  • fe12080c5f target/arm: Simplify GEN_SHIFT in translate.c Richard Henderson 2022-04-17 10:43:40 -07:00
  • e01aa38d48 target/arm: Split out gen_rebuild_hflags Richard Henderson 2022-04-17 10:43:38 -07:00
  • 667a4e6235 target/arm: Split out set_btype_raw Richard Henderson 2022-04-17 10:43:37 -07:00
  • a4c88675d6 target/arm: Remove fpexc32_access Richard Henderson 2022-04-17 10:43:36 -07:00
  • 063bbd8061 target/arm: Change CPUArchState.thumb to bool Richard Henderson 2022-04-17 10:43:35 -07:00
  • 2ab370873f target/arm: Change DisasContext.thumb to bool Richard Henderson 2022-04-17 10:43:34 -07:00
  • 4f4c2a4ba2 target/arm: Extend store_cpu_offset to take field size Richard Henderson 2022-04-17 10:43:33 -07:00
  • 5322155240 target/arm: Change CPUArchState.aarch64 to bool Richard Henderson 2022-04-17 10:43:32 -07:00
  • a3bc906f8e target/arm: Change DisasContext.aarch64 to bool Richard Henderson 2022-04-17 10:43:31 -07:00
  • ad1e60184c target/arm: Update SCTLR bits to ARMv9.2 Richard Henderson 2022-04-17 10:43:30 -07:00
  • f527d66183 target/arm: Update SCR_EL3 bits to ARMv8.8 Richard Henderson 2022-04-17 10:43:29 -07:00
  • c42fb26b13 target/arm: Update ISAR fields for ARMv8.8 Richard Henderson 2022-04-17 10:43:28 -07:00
  • 7cf3f8d243 hw/arm/virt: Support TCG GICv4 Peter Maydell 2022-04-08 15:15:50 +01:00
  • f31985a77a hw/arm/virt: Abstract out calculation of redistributor region capacity Peter Maydell 2022-04-08 15:15:49 +01:00
  • 5a389a9aec hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic() Peter Maydell 2022-04-08 15:15:48 +01:00
  • 445d5825da hw/intc/arm_gicv3: Allow 'revision' property to be set to 4 Peter Maydell 2022-04-08 15:15:47 +01:00
  • e2d5e189aa hw/intc/arm_gicv3: Update ID and feature registers for GICv4 Peter Maydell 2022-04-08 15:15:46 +01:00
  • 1b19ccfa38 hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi() Peter Maydell 2022-04-08 15:15:45 +01:00
  • e031346d98 hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall() Peter Maydell 2022-04-08 15:15:44 +01:00
  • c6f797d519 hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi() Peter Maydell 2022-04-08 15:15:43 +01:00
  • ab6ef25179 hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling Peter Maydell 2022-04-08 15:15:42 +01:00
  • 932f0480d0 hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending() Peter Maydell 2022-04-08 15:15:41 +01:00
  • d7d39749e6 hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi() Peter Maydell 2022-04-08 15:15:40 +01:00
  • b76eb5f4db hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code Peter Maydell 2022-04-08 15:15:39 +01:00
  • 6631480c9a hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes Peter Maydell 2022-04-08 15:15:38 +01:00
  • 99ba56d25b hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic Peter Maydell 2022-04-08 15:15:37 +01:00
  • e97be73c97 hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logic Peter Maydell 2022-04-08 15:15:36 +01:00
  • 189d1d9d57 hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily Peter Maydell 2022-04-08 15:15:35 +01:00
  • c3f21b065a hw/intc/arm_gicv3_cpuif: Support vLPIs Peter Maydell 2022-04-08 15:15:34 +01:00
  • 10337638bb hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update() Peter Maydell 2022-04-08 15:15:33 +01:00
  • 641be69745 hw/intc/arm_gicv3: Implement new GICv4 redistributor registers Peter Maydell 2022-04-08 15:15:32 +01:00
  • ae3b3ba15c hw/intc/arm_gicv3: Implement GICv4's new redistributor frame Peter Maydell 2022-04-08 15:15:31 +01:00
  • c6dd2f9950 hw/intc/arm_gicv3_its: Implement VINVALL Peter Maydell 2022-04-08 15:15:30 +01:00
  • 3c64a42c0b hw/intc/arm_gicv3_its: Implement VMOVI Peter Maydell 2022-04-08 15:15:29 +01:00
  • d4014320a4 hw/intc/arm_gicv3_its: Implement INV for virtual interrupts Peter Maydell 2022-04-08 15:15:28 +01:00
  • a686e85d2b hw/intc/arm_gicv3_its: Implement INV command properly Peter Maydell 2022-04-08 15:15:27 +01:00
  • f76ba95a03 hw/intc/arm_gicv3_its: Implement VSYNC Peter Maydell 2022-04-08 15:15:26 +01:00
  • 3851af4585 hw/intc/arm_gicv3_its: Implement VMOVP Peter Maydell 2022-04-08 15:15:25 +01:00
  • f7f40b8198 Merge tag 'dump-pull-request' of gitlab.com:marcandre.lureau/qemu into staging Richard Henderson 2022-04-22 04:43:57 -07:00
  • 67ae042737 hw/display/vmware_vga: do not discard screen updates Carwyn Ellis 2022-02-06 18:39:56 +00:00
  • f5daa8293b dump/win_dump: add 32-bit guest Windows support Viktor Prutyanov 2022-04-06 20:15:58 +03:00
  • c4fe30921f include/qemu: add 32-bit Windows dump structures Viktor Prutyanov 2022-04-06 20:15:57 +03:00
  • fb21efe99a dump/win_dump: add helper macros for Windows dump header access Viktor Prutyanov 2022-04-06 20:15:56 +03:00
  • a64b4e179a include/qemu: rename Windows context definitions to expose bitness Viktor Prutyanov 2022-04-06 20:15:55 +03:00
  • c68124738b dump: Consolidate elf note function Janosch Frank 2022-03-30 12:36:03 +00:00
  • 5ff2e5a3e1 dump: Cleanup dump_begin write functions Janosch Frank 2022-03-30 12:36:02 +00:00
  • bc7d558017 dump: Consolidate phdr note writes Janosch Frank 2022-03-30 12:36:01 +00:00
  • 05bbaa5040 dump: Introduce dump_is_64bit() helper function Janosch Frank 2022-03-30 12:36:00 +00:00
  • e71d353360 dump: Add more offset variables Janosch Frank 2022-03-30 12:35:59 +00:00
  • 344107e07b dump: Remove the section if when calculating the memory offset Janosch Frank 2022-03-30 12:35:58 +00:00
  • 862a395858 dump: Introduce shdr_num to decrease complexity Janosch Frank 2022-03-30 12:35:57 +00:00
  • 046bc4160b dump: Remove the sh_info variable Janosch Frank 2022-04-07 09:48:24 +00:00
  • 86a518bba4 dump: Use ERRP_GUARD() Janosch Frank 2022-03-30 12:35:55 +00:00
  • 7c087bd330 hw/intc/arm_gicv3: Keep pointers to every connected ITS Peter Maydell 2022-04-08 15:15:24 +01:00
  • 469cf23bf8 hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd() Peter Maydell 2022-04-08 15:15:23 +01:00
  • 2d692e2b31 hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt code Peter Maydell 2022-04-08 15:15:22 +01:00
  • c411db7bf7 hw/intc/arm_gicv3_its: Factor out CTE lookup sequence Peter Maydell 2022-04-08 15:15:21 +01:00
  • f0175135e7 hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid" Peter Maydell 2022-04-08 15:15:20 +01:00
  • 93f4fdcd4d hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUE Peter Maydell 2022-04-08 15:15:19 +01:00
  • 0cdf7a5dc8 hw/intc/arm_gicv3_its: Implement VMAPP Peter Maydell 2022-04-08 15:15:18 +01:00
  • 9de53de60c hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI Peter Maydell 2022-04-08 15:15:17 +01:00
  • 50d84584d3 hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4 Peter Maydell 2022-04-08 15:15:16 +01:00
  • c3c9a09073 hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?" Peter Maydell 2022-04-08 15:15:15 +01:00
  • 9acd2d3373 target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2 Peter Maydell 2022-04-08 15:15:14 +01:00
  • 50a3a309e1 hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers Peter Maydell 2022-04-08 15:15:13 +01:00
  • 671927a116 hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count Peter Maydell 2022-04-08 15:15:12 +01:00
  • 89ac9d0cba hw/intc/arm_gicv3: Sanity-check num-cpu property Peter Maydell 2022-04-08 15:15:11 +01:00
  • 2a19903697 hw/intc/arm_gicv3_its: Add missing blank line Peter Maydell 2022-04-08 15:15:10 +01:00
  • 10cd282ee4 Merge tag 'pull-riscv-to-apply-20220422-1' of github.com:alistair23/qemu into staging Richard Henderson 2022-04-21 22:03:34 -07:00
  • a74782936d Merge tag 'pull-migration-20220421a' of https://gitlab.com/dagrh/qemu into staging Richard Henderson 2022-04-21 18:48:18 -07:00
  • faee5441a0 hw/riscv: boot: Support 64bit fdt address. Dylan Jhong 2022-04-19 19:59:45 +08:00
  • 013577de8f hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Bin Meng 2022-04-21 08:33:24 +08:00
  • c9711bd778 target/riscv: cpu: Enable native debug feature Bin Meng 2022-04-21 08:33:23 +08:00
  • 38b4e781a4 target/riscv: machine: Add debug state description Bin Meng 2022-04-21 08:33:22 +08:00
  • b6092544fc target/riscv: csr: Hook debug CSR read/write Bin Meng 2022-04-21 08:33:21 +08:00
  • 1acdb3b013 target/riscv: cpu: Add a config option for native debug Bin Meng 2022-04-21 08:33:20 +08:00
  • b5f6379d13 target/riscv: debug: Implement debug related TCGCPUOps Bin Meng 2022-04-21 08:33:19 +08:00
  • 8124f819d0 hw/intc: riscv_aclint: Add reset function of ACLINT devices Jim Shu 2022-04-20 16:09:00 +08:00
  • e2f01f3c2e hw/intc: Make RISC-V ACLINT mtime MMIO register writable Frank Chang 2022-04-20 16:08:59 +08:00
  • d42df0ea5d hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT Frank Chang 2022-04-20 16:08:58 +08:00
  • 231a90c085 hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT Frank Chang 2022-04-20 16:08:57 +08:00
  • d6db2c0fab hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled Niklas Cassel 2022-04-14 17:55:10 +02:00
  • 6248a8fe4d target/riscv/pmp: fix NAPOT range computation overflow Nicolas Pitre 2022-04-08 12:25:07 -04:00
  • 8f013700eb hw/riscv: virt: Exit if the user provided -bios in combination with KVM Ralf Ramsauer 2022-04-01 14:18:42 +02:00
  • ac684717c3 target/riscv: Use cpu_loop_exit_restore directly from mmu faults Richard Henderson 2022-04-01 06:59:47 -06:00
  • f06193c40b target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 Weiwei Li 2022-03-30 10:13:16 +08:00
  • a775398be2 target/riscv: Add isa extenstion strings to the device tree Atish Patra 2022-03-29 12:56:57 -07:00
  • 0e2c377023 target/riscv: misa to ISA string conversion fix Tsukasa OI 2022-03-28 22:11:23 +09:00
  • f32d82f6c3 target/riscv: optimize helper for vmv<nr>r.v Weiwei Li 2022-03-25 16:59:02 +08:00
  • c341e886d9 target/riscv: optimize condition assign for scale < 0 Weiwei Li 2022-03-25 16:59:01 +08:00
  • 95799e36c1 target/riscv: Add initial support for the Sdtrig extension Bin Meng 2022-03-15 14:55:23 +08:00
  • 33fe584f70 target/riscv: Allow software access to MIP SEIP Alistair Francis 2022-03-17 16:18:17 +10:00
  • 8b5c807bc0 target/riscv: cpu: Fixup indentation Alistair Francis 2022-03-17 16:18:16 +10:00
  • 7100fe6c24 target/riscv: Enable privileged spec version 1.12 Atish Patra 2022-03-03 10:54:40 -08:00
  • 29a9ec9bd8 target/riscv: Add *envcfg* CSRs support Atish Patra 2022-03-03 10:54:39 -08:00
  • 3e6a417c8a target/riscv: Add support for mconfigptr Atish Patra 2022-03-03 10:54:38 -08:00
  • a4b2fa4331 target/riscv: Introduce privilege version field in the CSR ops. Atish Patra 2022-03-03 10:54:37 -08:00