alwin.berger/FRET-LibAFL
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Commit Graph

  • 5e9d14f2be Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220121-1' into staging Peter Maydell 2022-01-21 10:31:25 +00:00
  • 03c020f4bd
         Asan fix (#485) Dongjia Zhang 2022-01-21 17:08:21 +09:00
  • f297245f6a target/riscv: Relax UXL field for debugging LIU Zhiwei 2022-01-20 20:20:50 +08:00
  • f310df58bd target/riscv: Enable uxl field write LIU Zhiwei 2022-01-20 20:20:49 +08:00
  • 5a2ae2350e target/riscv: Set default XLEN for hypervisor LIU Zhiwei 2022-01-20 20:20:48 +08:00
  • d8c40c24fd target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei 2022-01-20 20:20:47 +08:00
  • d6b9d93023 target/riscv: Adjust vector address with mask LIU Zhiwei 2022-01-20 20:20:46 +08:00
  • 01d09525da target/riscv: Fix check range for first fault only LIU Zhiwei 2022-01-20 20:20:45 +08:00
  • eef11ce325 target/riscv: Remove VILL field in VTYPE LIU Zhiwei 2022-01-20 20:20:44 +08:00
  • 31961cfe50 target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei 2022-01-20 20:20:43 +08:00
  • d96a271a8d target/riscv: Split out the vill from vtype LIU Zhiwei 2022-01-20 20:20:42 +08:00
  • 4208dc7e9e target/riscv: Split pm_enabled into mask and base LIU Zhiwei 2022-01-20 20:20:41 +08:00
  • 4302bef9e1 target/riscv: Calculate address according to XLEN LIU Zhiwei 2022-01-20 20:20:40 +08:00
  • 0cff460de9 target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei 2022-01-20 20:20:39 +08:00
  • 40bfa5f695 target/riscv: Create current pm fields in env LIU Zhiwei 2022-01-20 20:20:38 +08:00
  • 83b519b8a4 target/riscv: Adjust csr write mask with XLEN LIU Zhiwei 2022-01-20 20:20:37 +08:00
  • 47bdec821b target/riscv: Relax debug check for pm write LIU Zhiwei 2022-01-20 20:20:36 +08:00
  • 1191be09a9 target/riscv: Use gdb xml according to max mxlen LIU Zhiwei 2022-01-20 20:20:35 +08:00
  • bf9e776ec1 target/riscv: Extend pc for runtime pc write LIU Zhiwei 2022-01-20 20:20:34 +08:00
  • 8c796f1a15 target/riscv: Ignore the pc bits above XLEN LIU Zhiwei 2022-01-20 20:20:33 +08:00
  • 440544e1cf target/riscv: Create xl field in env LIU Zhiwei 2022-01-20 20:20:32 +08:00
  • 40f0c2046c target/riscv: Sign extend pc for different XLEN LIU Zhiwei 2022-01-20 20:20:31 +08:00
  • a14db52f7f target/riscv: Sign extend link reg for jal and jalr LIU Zhiwei 2022-01-20 20:20:30 +08:00
  • b655dc7cd9 target/riscv: Don't save pc when exception return LIU Zhiwei 2022-01-20 20:20:29 +08:00
  • 79f26b3b95 target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei 2022-01-20 20:20:28 +08:00
  • 4211fc5532 roms/opensbi: Remove ELF images Anup Patel 2022-01-18 14:00:35 +05:30
  • 092dc6df92 hw/riscv: Remove macros for ELF BIOS image names Anup Patel 2022-01-18 13:38:56 +05:30
  • 8d8897accb hw/riscv: spike: Allow using binary firmware as bios Anup Patel 2022-01-13 20:20:39 +05:30
  • 2fc1b44dd0 target/riscv: rvv-1.0: Allow Zve32f extension to be turned on Frank Chang 2022-01-18 09:45:20 +08:00
  • 6db02328a7 target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns Frank Chang 2022-01-18 09:45:19 +08:00
  • f4dcf51cdc target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns Frank Chang 2022-01-18 09:45:18 +08:00
  • 8527b5db72 target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns Frank Chang 2022-01-18 09:45:17 +08:00
  • abe2d74032 target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns Frank Chang 2022-01-18 09:45:16 +08:00
  • da61f1256f target/riscv: rvv-1.0: Add Zve32f support for configuration insns Frank Chang 2022-01-18 09:45:15 +08:00
  • 32e579b8c5 target/riscv: rvv-1.0: Add Zve32f extension into RISC-V Frank Chang 2022-01-18 09:45:14 +08:00
  • bfefe406b7 target/riscv: rvv-1.0: Allow Zve64f extension to be turned on Frank Chang 2022-01-18 09:45:13 +08:00
  • 68fa38970e target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns Frank Chang 2022-01-18 09:45:12 +08:00
  • 235d1161d4 target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns Frank Chang 2022-01-18 09:45:11 +08:00
  • 193fb5c9bd target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns Frank Chang 2022-01-18 09:45:10 +08:00
  • 40d78c85f6 target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns Frank Chang 2022-01-18 09:45:09 +08:00
  • 13dbc826fd target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns Frank Chang 2022-01-18 09:45:08 +08:00
  • aaae69942f target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns Frank Chang 2022-01-18 09:45:07 +08:00
  • 494104093f target/riscv: rvv-1.0: Add Zve64f support for load and store insns Frank Chang 2022-01-18 09:45:06 +08:00
  • c7a26fb2f6 target/riscv: rvv-1.0: Add Zve64f support for configuration insns Frank Chang 2022-01-18 09:45:05 +08:00
  • b4a99d4027 target/riscv: rvv-1.0: Add Zve64f extension into RISC-V Frank Chang 2022-01-18 09:45:04 +08:00
  • 22599b795c softmmu/device_tree: Remove redundant pointer assignment Yanan Wang 2022-01-11 11:27:58 +08:00
  • cfeeeb482a softmmu/device_tree: Silence compiler warning with --enable-sanitizers Thomas Huth 2022-01-07 14:38:44 +01:00
  • fbf43c7dbf target/riscv: enable riscv kvm accel Yifei Jiang 2022-01-12 16:13:29 +08:00
  • 1eb9a5da31 target/riscv: Support virtual time context synchronization Yifei Jiang 2022-01-12 16:13:28 +08:00
  • 9ad3e016ae target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang 2022-01-12 16:13:27 +08:00
  • 27abe66f31 target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang 2022-01-12 16:13:26 +08:00
  • 10f1ca27e0 target/riscv: Add host cpu type Yifei Jiang 2022-01-12 16:13:25 +08:00
  • 4eb471258b target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang 2022-01-12 16:13:24 +08:00
  • 2b650fbbcc target/riscv: Support setting external interrupt by KVM Yifei Jiang 2022-01-12 16:13:23 +08:00
  • ad40be2708 target/riscv: Support start kernel directly by KVM Yifei Jiang 2022-01-12 16:13:22 +08:00
  • 9997cc1e19 target/riscv: Implement kvm_arch_put_registers Yifei Jiang 2022-01-12 16:13:21 +08:00
  • 937f0b4512 target/riscv: Implement kvm_arch_get_registers Yifei Jiang 2022-01-12 16:13:20 +08:00
  • 0a312b85cb target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang 2022-01-12 16:13:19 +08:00
  • 91654e613b target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang 2022-01-12 16:13:18 +08:00
  • b91a0fa70c update-linux-headers: Add asm-riscv/kvm.h Yifei Jiang 2022-01-12 16:13:17 +08:00
  • dda94e5c66 hw: timer: ibex_timer: update/add reg address Wilfred Mallawa 2022-01-11 17:10:25 +10:00
  • 0df470c388 riscv: opentitan: fixup plic stride len Wilfred Mallawa 2022-01-11 17:10:24 +10:00
  • 28ca4689ae hw: timer: ibex_timer: Fixup reading w/o register Wilfred Mallawa 2022-01-10 15:16:06 +10:00
  • 45bdab5000 struct parsing experiment Alwin Berger 2022-01-21 00:17:17 +01:00
  • cc0880e784
         Monitor with UI based on tui-rs (#480) Andrea Fioraldi 2022-01-20 23:55:48 +01:00
  • ab7d16347f
         [libafl_qemu] map_fixed and mprotect target memory (#483) Evan Richter 2022-01-20 15:06:26 -06:00
  • 2c89b5af5e Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220120-1' into staging Peter Maydell 2022-01-20 16:13:17 +00:00
  • b9d383ab79 hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR Philippe Mathieu-Daudé 2021-12-15 19:24:19 +01:00
  • 58b88779f0 hw/intc/arm_gicv3_its: Range-check ICID before indexing into collection table Peter Maydell 2022-01-11 17:10:48 +00:00
  • b13148d918 hw/intc/arm_gicv3_its: Check indexes before use, not after Peter Maydell 2022-01-11 17:10:47 +00:00
  • d050f80f8c hw/intc/arm_gicv3_its: Factor out "find address of table entry" code Peter Maydell 2022-01-11 17:10:46 +00:00
  • 00d46e72e9 hw/intc/arm_gicv3_its: Fix return codes in process_mapd() Peter Maydell 2022-01-11 17:10:45 +00:00
  • f667519614 hw/intc/arm_gicv3_its: Fix return codes in process_mapc() Peter Maydell 2022-01-11 17:10:44 +00:00
  • 0241f73160 hw/intc/arm_gicv3_its: Fix return codes in process_mapti() Peter Maydell 2022-01-11 17:10:43 +00:00
  • be0ed8fb7f hw/intc/arm_gicv3_its: Refactor process_its_cmd() to reduce nesting Peter Maydell 2022-01-11 17:10:42 +00:00
  • 593a7cc2d3 hw/intc/arm_gicv3_its: Fix return codes in process_its_cmd() Peter Maydell 2022-01-11 17:10:41 +00:00
  • ef011555da hw/intc/arm_gicv3_its: Use enum for return value of process_* functions Peter Maydell 2022-01-11 17:10:40 +00:00
  • f0b4b2a28c hw/intc/arm_gicv3_its: Don't use data if reading command failed Peter Maydell 2022-01-11 17:10:39 +00:00
  • 7d62b2dcdb hw/intc/arm_gicv3_its: Fix handling of process_its_cmd() return value Peter Maydell 2022-01-11 17:10:38 +00:00
  • 905720f18d hw/intc/arm_gicv3_its: Convert int ID check to num_intids convention Peter Maydell 2022-01-11 17:10:37 +00:00
  • 8f809f6992 hw/intc/arm_gicv3_its: Fix event ID bounds checks Peter Maydell 2022-01-11 17:10:36 +00:00
  • 3222165dcb hw/arm/aspeed: Add the i3c device to the AST2600 SoC Troy Lee 2022-01-11 16:45:46 +08:00
  • 119df56bf0 hw/misc/aspeed_i3c.c: Introduce a dummy AST2600 I3C model. Troy Lee 2022-01-11 16:45:45 +08:00
  • 0419e6a867 hw/arm: kudo add lm75s behind bus 1 switch at 75 Patrick Venture 2022-01-11 09:23:38 -08:00
  • 2dcb74e5c2 hw/arm/virt: Drop superfluous checks against highmem Marc Zyngier 2022-01-14 14:07:41 +00:00
  • d9afe24c29 hw/arm/virt: Disable highmem devices that don't fit in the PA range Marc Zyngier 2022-01-14 14:07:40 +00:00
  • 3715c251cc hw/arm/virt: Use the PA range to compute the memory map Marc Zyngier 2022-01-14 14:07:39 +00:00
  • 0152b169ce hw/arm/virt: Honor highmem setting when computing the memory map Marc Zyngier 2022-01-14 14:07:38 +00:00
  • a63618b147 hw/arm/virt: Add a control for the the highmem redistributors Marc Zyngier 2022-01-14 14:07:37 +00:00
  • c8f008c40f hw/arm/virt: Add a control for the the highmem PCIe MMIO Marc Zyngier 2022-01-14 14:07:36 +00:00
  • 5e66daec9e hw/intc/arm_gic: Allow reset of the running priority Petr Pavlu 2022-01-13 16:19:16 +01:00
  • a66a24585f hw/intc/arm_gic: Implement read of GICC_IIDR Petr Pavlu 2022-01-13 16:19:15 +01:00
  • b1b87327a9 hw/arm/virt: Support for virtio-mem-pci Gavin Shan 2022-01-11 14:33:29 +08:00
  • 1263615efe virtio-mem: Correct default THP size for ARM64 Gavin Shan 2022-01-11 14:33:28 +08:00
  • 87f14eaa51 docs/can: convert to restructuredText Lucas Ramage 2022-01-05 20:56:28 +00:00
  • 3cda85b203 tests/acpi/bios-table-test: Update expected virt/PPTT file Yanan Wang 2022-01-07 16:32:32 +08:00
  • 88d0278aa7 hw/acpi/aml-build: Support cluster level in PPTT generation Yanan Wang 2022-01-07 16:32:31 +08:00
  • 291f6dd566 tests/acpi/bios-tables-test: Allow changes to virt/PPTT file Yanan Wang 2022-01-07 16:32:30 +08:00
  • 11b9eb1b8a hw/acpi/aml-build: Improve scalability of PPTT generation Yanan Wang 2022-01-07 16:32:29 +08:00
  • 28a60a59c0 hw/arm/virt: Support cluster level in DT cpu-map Yanan Wang 2022-01-07 16:32:28 +08:00