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• cced3a7230 MAINTAINERS: Add entry for QEMU Guest Agent Windows components Kostiantyn Kostiuk 2022-01-05 09:09:42 +00:00
• de5264efad Clippy Andrea Fioraldi 2022-01-10 13:34:24 +01:00
• 180883acb7 Panic when using nautilus with stable Rust Andrea Fioraldi 2022-01-10 12:17:32 +01:00
• d7dbd021a4 Specialization feature in nightly Andrea Fioraldi 2022-01-10 11:49:13 +01:00
• 8870c50ff5 Do not build QEMU when generating docs Andrea Fioraldi 2022-01-10 11:27:53 +01:00
• eed864eb36 switch to rustversion Andrea Fioraldi 2022-01-10 10:12:26 +01:00
• 1c127fa8e2 pseries: Update SLOF firmware image Alexey Kardashevskiy 2022-01-10 15:27:45 +11:00
• 327ff98ea1
  Asan fix (#460) Dongjia Zhang 2022-01-10 05:00:04 +09:00
• 82194c5fe5
  Fix windows build (#462) Dongjia Zhang 2022-01-10 04:57:43 +09:00
• 5ac3cd6b5a
  Optional signal value for kill on timeouts in TimeoutForkserverExecutor (#461) buherator 2022-01-09 14:31:14 +01:00
• 31144eb639 target/m68k: don't word align SP in stack frame if M68K_FEATURE_UNALIGNED_DATA feature enabled Mark Cave-Ayland 2022-01-08 18:04:53 +00:00
• 4e136629f0 macfb: fix VRAM dirty memory region logging Mark Cave-Ayland 2022-01-08 16:41:47 +00:00
• 0969e00b39 q800: fix segfault with invalid MacROM Laurent Vivier 2022-01-07 11:50:49 +01:00
• 214bdf8e71 hw: m68k: Add virt compat machine type for 7.0 Laurent Vivier 2021-12-18 12:43:40 +01:00
• df722e33d5 Merge tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu into staging Richard Henderson 2022-01-08 09:37:59 -08:00
• afe3326258 Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into staging Richard Henderson 2022-01-07 22:09:24 -08:00
• 18fe5d99f2 bsd-user: add arm target build Warner Losh 2021-09-23 15:30:45 -06:00
• ca4fc704a4 bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZE Warner Losh 2021-11-04 17:21:48 -06:00
• 3ac34cc985 bsd-user/arm/signal.c: arm get_ucontext_sigreturn Warner Losh 2021-09-23 15:24:19 -06:00
• d6d4509a9f bsd-user/arm/signal.c: arm set_mcontext Warner Losh 2021-09-23 15:23:13 -06:00
• 38ce1471c9 bsd-user/arm/signal.c: arm get_mcontext Warner Losh 2021-09-23 15:22:12 -06:00
• 781be8666c bsd-user/arm/signal.c: arm set_sigtramp_args Warner Losh 2021-09-23 15:19:33 -06:00
• 2cb1e6432f bsd-user/arm/target_arch_signal.h: Define size of *context_t Warner Losh 2021-11-04 17:08:04 -06:00
• 03fd4028f1 bsd-user/arm/target_arch_signal.h: arm machine context and trapframe for signals Warner Losh 2021-09-23 15:17:03 -06:00
• 156d75579f bsd-user/arm/target_arch_signal.h: arm specific signal registers and stack Warner Losh 2021-09-23 15:15:08 -06:00
• 883d19ccf9 bsd-user/arm/target_arch_elf.h: arm get_hwcap2 impl Warner Losh 2021-09-23 14:48:18 -06:00
• 6c5d60fa78 bsd-user/arm/target_arch_elf.h: arm get hwcap Warner Losh 2021-09-23 14:42:42 -06:00
• 082e65314b bsd-user/arm/target_arch_elf.h: arm defines for ELF Warner Losh 2021-09-23 14:34:56 -06:00
• f10521cc22 bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread Warner Losh 2021-09-23 09:16:15 -06:00
• eacb50b8d9 bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for arm Warner Losh 2021-09-23 09:14:08 -06:00
• dacfdf3ba4 bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space Warner Losh 2021-09-23 09:12:12 -06:00
• bcacf30808 bsd-user/arm/target_arch_reg.h: Implement core dump register copying Warner Losh 2021-09-23 09:10:27 -06:00
• 8d450c9a30 bsd-user/arm/target_arch_cpu.h: Implement system call dispatch Warner Losh 2021-09-23 09:08:21 -06:00
• ef1412bd84 bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions Warner Losh 2021-09-23 08:57:14 -06:00
• 70985aec1c bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptions Warner Losh 2021-09-23 08:54:17 -06:00
• 06efe3bfce bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation Warner Losh 2021-09-23 08:47:16 -06:00
• e17d4c9a37 bsd-user/arm/target_arch_cpu.h: Implement target_cpu_clone_regs Warner Losh 2021-09-23 08:44:05 -06:00
• ca5d32a3f3 bsd-user/arm/target_arch_cpu.h: CPU Loop definitions Warner Losh 2021-09-23 08:41:13 -06:00
• 8c98705bb9 bsd-user/arm/target_arch_cpu.c: Target specific TLS routines Warner Losh 2021-09-23 08:32:06 -06:00
• 559d09a6cd bsd-user/arm/target_syscall.h: Add copyright and update name Warner Losh 2021-09-23 08:29:39 -06:00
• c186aa67de bsd-user/arm/target_arch_sysarch.h: Use consistent include guards Warner Losh 2021-09-23 08:28:24 -06:00
• 108fffe536 bsd-user/target_os_signal.h: Move signal prototypes to target_os_ucontext.h Warner Losh 2021-11-05 10:55:35 -06:00
• 1b4e358a61 bsd-user/x86_64: Move functions into signal.c Warner Losh 2021-11-04 16:53:13 -06:00
• 164f94bc30 bsd-user/x86_64/target_arch_signal.h: Fill in mcontext_t Warner Losh 2021-11-04 16:51:50 -06:00
• c104b7505b bsd-user/x86_64/target_arch_signal.h: use new target_os_ucontext.h Warner Losh 2021-10-29 09:07:02 -06:00
• fc1fc2c78e bsd-user/x86_64/target_arch_signal.h: Remove target_sigcontext Warner Losh 2021-10-29 08:27:50 -06:00
• f7d5ed6184 bsd-user/i386: Move the inlines into signal.c Warner Losh 2021-11-04 16:45:26 -06:00
• 679041b1ef bsd-user/i386/target_arch_signal.h: Update mcontext_t to match FreeBSD Warner Losh 2021-11-04 16:41:55 -06:00
• c504713f34 bsd-user/i386/target_arch_signal.h: use new target_os_ucontext.h Warner Losh 2021-10-29 09:07:59 -06:00
• 4dca396631 bsd-user/i386/target_arch_signal.h: Remove target_sigcontext Warner Losh 2021-10-29 08:25:45 -06:00
• 19bf129f82 bsd-user: create a per-arch signal.c file Warner Losh 2021-11-04 16:34:48 -06:00
• aa3a242830 bsd-user/freebsd: Create common target_os_ucontext.h file Warner Losh 2021-10-29 08:39:01 -06:00
• 73d72229fc bsd-user/mips*: Remove mips support Warner Losh 2021-11-04 16:31:27 -06:00
• 48eaeb56de target/riscv: Implement the stval/mtval illegal instruction Alistair Francis 2021-12-20 16:49:16 +10:00
• 86d0c45739 target/riscv: Fixup setting GVA Alistair Francis 2021-12-20 16:49:15 +10:00
• ea7b5d5af6 target/riscv: Set the opcode in DisasContext Alistair Francis 2021-12-20 16:49:14 +10:00
• 457c360f9c target/riscv: actual functions to realize crs 128-bit insns Frédéric Pétrot 2022-01-06 22:01:08 +01:00
• 7934fdeee7 target/riscv: modification of the trans_csrxx for 128-bit support Frédéric Pétrot 2022-01-06 22:01:07 +01:00
• 961738ffea target/riscv: helper functions to wrap calls to 128-bit csr insns Frédéric Pétrot 2022-01-06 22:01:06 +01:00
• 2c64ab66c1 target/riscv: adding high part of some csrs Frédéric Pétrot 2022-01-06 22:01:05 +01:00
• b3a5d1fbeb target/riscv: support for 128-bit M extension Frédéric Pétrot 2022-01-06 22:01:04 +01:00
• 7fd40f8679 target/riscv: support for 128-bit arithmetic instructions Frédéric Pétrot 2022-01-06 22:01:03 +01:00
• 6bf4bbed20 target/riscv: support for 128-bit shift instructions Frédéric Pétrot 2022-01-06 22:01:02 +01:00
• 57c108b864 target/riscv: support for 128-bit U-type instructions Frédéric Pétrot 2022-01-06 22:01:01 +01:00
• 568f247f69 target/riscv: support for 128-bit bitwise instructions Frédéric Pétrot 2022-01-06 22:01:00 +01:00
• a2f827ff4f target/riscv: accessors to registers upper part and 128-bit load/store Frédéric Pétrot 2022-01-06 22:00:59 +01:00
• 76a361066f target/riscv: moving some insns close to similar insns Frédéric Pétrot 2022-01-06 22:00:58 +01:00
• 332dab6878 target/riscv: setup everything for rv64 to support rv128 execution Frédéric Pétrot 2022-01-06 22:00:57 +01:00
• 2b5470843a target/riscv: array for the 64 upper bits of 128-bit registers Frédéric Pétrot 2022-01-06 22:00:56 +01:00
• a1a3aac448 target/riscv: separation of bitwise logic and arithmetic helpers Frédéric Pétrot 2022-01-06 22:00:55 +01:00
• 344b4a82fc target/riscv: additional macros to check instruction support Frédéric Pétrot 2022-01-06 22:00:54 +01:00
• e9d07601f6 qemu/int128: addition of div/rem 128-bit operations Frédéric Pétrot 2022-01-06 22:00:53 +01:00
• c7f9dd5465 exec/memop: Adding signed quad and octo defines Frédéric Pétrot 2022-01-06 22:00:52 +01:00
• fc313c6434 exec/memop: Adding signedness to quad definitions Frédéric Pétrot 2022-01-06 22:00:51 +01:00
• dfdb46a376 target/riscv: Fix position of 'experimental' comment Philipp Tomsich 2022-01-06 14:40:20 +01:00
• 79e6176ea0 target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns Frank Chang 2022-01-05 10:22:46 +08:00
• 91cade44cd target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns Frank Chang 2022-01-05 10:22:45 +08:00
• 629ccdaa4e target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns Frank Chang 2022-01-05 10:22:44 +08:00
• b3e0204968 roms/opensbi: Upgrade from v0.9 to v1.0 Bin Meng 2022-01-05 09:42:48 +08:00
• d4452c6924 hw/riscv: virt: Allow support for 32 cores Alistair Francis 2022-01-06 07:39:37 +10:00
• 8f972e5b4b hw/riscv: Use error_fatal for SoC realisation Alistair Francis 2022-01-06 07:39:36 +10:00
• 07cb270a9a target/riscv: Enable the Hypervisor extension by default Alistair Francis 2022-01-06 07:39:35 +10:00
• 6ca7155a8c target/riscv: Mark the Hypervisor extension as non experimental Alistair Francis 2022-01-06 07:39:34 +10:00
• 41bcc44a25 hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis 2022-01-06 07:39:33 +10:00
• b79e1c76c0 hw/intc: sifive_plic: Cleanup the read function Alistair Francis 2022-01-06 07:39:32 +10:00
• fb926d57cc hw/intc: sifive_plic: Cleanup the write function Alistair Francis 2022-01-06 07:39:31 +10:00
• 83b92b8efc hw/intc: sifive_plic: Add a reset function Alistair Francis 2022-01-06 07:39:30 +10:00
• e6b0408a17 hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers Jim Shu 2022-01-04 14:34:08 +08:00
• 6fd3f397ca hw/dma: sifive_pdma: support high 32-bit access of 64-bit register Jim Shu 2022-01-04 14:34:07 +08:00
• 0fbb5d2d3c target/riscv/pmp: fix no pmp illegal intrs Nikita Shubin 2021-12-14 12:26:59 +03:00
• d70075373a Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging Richard Henderson 2022-01-07 17:24:24 -08:00
• ca745d2277 tests: acpi: Add updated TPM related tables Stefan Berger 2022-01-04 12:58:06 -05:00
• 5903646d39 acpi: tpm: Add missing device identification objects Stefan Berger 2022-01-04 12:58:05 -05:00
• b193e5f9cc tests: acpi: prepare for updated TPM related tables Stefan Berger 2022-01-04 12:58:04 -05:00
• d731ab3119 virtio/vhost-vsock: don't double close vhostfd, remove redundant cleanup Daniil Tatianin 2021-11-29 15:52:04 +03:00
• 539ba1acac hw/scsi/vhost-scsi: don't double close vhostfd on error Daniil Tatianin 2021-11-29 16:23:58 +03:00
• b259772afc hw/scsi/vhost-scsi: don't leak vqs on error Daniil Tatianin 2021-11-29 16:23:57 +03:00
• 14dc58e3e0 docs: reSTify virtio-balloon-stats documentation and move to docs/interop Thomas Huth 2022-01-05 12:52:45 +01:00
• 44bff3767c hw/i386/pc: Add missing property descriptions Thomas Huth 2021-12-06 14:42:55 +01:00
• 784802689f acpihp: simplify acpi_pcihp_disable_root_bus Ani Sinha 2021-12-29 13:27:53 +05:30