alwin.berger/FRET-qemu
1
0
Fork 1
Code Issues Pull Requests Projects Releases Wiki Activity
109,688 Commits 13 Branches 3 Tags
Commit Graph

202 Commits

Author SHA1 Message Date
Romain Malmain
7c3c7877d8 Update to QEMU 9.0.0 (#67) 
* Update to QEMU v9.0.0

---------

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Zheyu Ma <zheyuma97@gmail.com>
Signed-off-by: Ido Plat <ido.plat@ibm.com>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Signed-off-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Thomas Lamprecht <t.lamprecht@proxmox.com>
Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
Signed-off-by: Gregory Price <gregory.price@memverge.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Lorenz Brun <lorenz@brun.one>
Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Joonas Kankaala <joonas.a.kankaala@gmail.com>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Oleg Sviridov <oleg.sviridov@red-soft.ru>
Signed-off-by: Artem Chernyshev <artem.chernyshev@red-soft.ru>
Signed-off-by: Yajun Wu <yajunw@nvidia.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
Signed-off-by: Lei Wang <lei4.wang@intel.com>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Signed-off-by: Martin Hundebøll <martin@geanix.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Wafer <wafer@jaguarmicro.com>
Signed-off-by: Yuxue Liu <yuxue.liu@jaguarmicro.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Nguyen Dinh Phi <phind.uet@gmail.com>
Signed-off-by: Zack Buhman <zack@buhman.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Yuquan Wang wangyuquan1236@phytium.com.cn
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Cindy Lu <lulu@redhat.com>
Co-authored-by: Peter Maydell <peter.maydell@linaro.org>
Co-authored-by: Fabiano Rosas <farosas@suse.de>
Co-authored-by: Peter Xu <peterx@redhat.com>
Co-authored-by: Thomas Huth <thuth@redhat.com>
Co-authored-by: Cédric Le Goater <clg@redhat.com>
Co-authored-by: Zheyu Ma <zheyuma97@gmail.com>
Co-authored-by: Ido Plat <ido.plat@ibm.com>
Co-authored-by: Ilya Leoshkevich <iii@linux.ibm.com>
Co-authored-by: Markus Armbruster <armbru@redhat.com>
Co-authored-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Co-authored-by: Paolo Bonzini <pbonzini@redhat.com>
Co-authored-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Co-authored-by: David Hildenbrand <david@redhat.com>
Co-authored-by: Kevin Wolf <kwolf@redhat.com>
Co-authored-by: Stefan Reiter <s.reiter@proxmox.com>
Co-authored-by: Fiona Ebner <f.ebner@proxmox.com>
Co-authored-by: Gregory Price <gregory.price@memverge.com>
Co-authored-by: Lorenz Brun <lorenz@brun.one>
Co-authored-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
Co-authored-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Co-authored-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Co-authored-by: BALATON Zoltan <balaton@eik.bme.hu>
Co-authored-by: Igor Mammedov <imammedo@redhat.com>
Co-authored-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Co-authored-by: Sven Schnelle <svens@stackframe.org>
Co-authored-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Co-authored-by: Helge Deller <deller@kernel.org>
Co-authored-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Co-authored-by: Benjamin Gray <bgray@linux.ibm.com>
Co-authored-by: Nicholas Piggin <npiggin@gmail.com>
Co-authored-by: Avihai Horon <avihaih@nvidia.com>
Co-authored-by: Michael Tokarev <mjt@tls.msk.ru>
Co-authored-by: Joonas Kankaala <joonas.a.kankaala@gmail.com>
Co-authored-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Co-authored-by: Stefan Weil <sw@weilnetz.de>
Co-authored-by: Dayu Liu <liu.dayu@zte.com.cn>
Co-authored-by: Zhao Liu <zhao1.liu@intel.com>
Co-authored-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Co-authored-by: Artem Chernyshev <artem.chernyshev@red-soft.ru>
Co-authored-by: Yajun Wu <yajunw@nvidia.com>
Co-authored-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Co-authored-by: Pierre-Clément Tosi <ptosi@google.com>
Co-authored-by: Wei Wang <wei.w.wang@intel.com>
Co-authored-by: Martin Hundebøll <martin@geanix.com>
Co-authored-by: Michael S. Tsirkin <mst@redhat.com>
Co-authored-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Co-authored-by: Wafer <wafer@jaguarmicro.com>
Co-authored-by: lyx634449800 <yuxue.liu@jaguarmicro.com>
Co-authored-by: Gerd Hoffmann <kraxel@redhat.com>
Co-authored-by: Nguyen Dinh Phi <phind.uet@gmail.com>
Co-authored-by: Zack Buhman <zack@buhman.org>
Co-authored-by: Keith Packard <keithp@keithp.com>
Co-authored-by: Yuquan Wang <wangyuquan1236@phytium.com.cn>
Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Co-authored-by: Cindy Lu <lulu@redhat.com>
 2024-05-01 16:10:20 +02:00
Helge Deller
a01491a238 target/hppa: Fix 64-bit SHRPD instruction 
When shifting the two joined 64-bit registers right, shift the upper
64-bit register to the left and the lower 64-bit register to the right
before merging them with OR.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-17 18:36:36 +01:00
Richard Henderson
451d993d58 target/hppa: Replace MMU_PHYS_IDX with MMU_ABS_IDX, MMU_ABS_W_IDX 
Align the language with pa2.0, separating absolute and physical.
The translation from absolute to physical depends on PSW.W, and
we prefer not to flush between changes, therefore use 2 mmu_idx.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-13 09:20:43 -08:00
Richard Henderson
17fe594c59 target/hppa: Introduce MMU_IDX_MMU_DISABLED 
Reduce the number of direct checks against MMU_PHYS_IDX.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-13 09:17:21 -08:00
Richard Henderson
e5d487c972 target/hppa: Use only low 2 immediate bits for PROBEI 
During the conversion to decodetree, the 2-bit mask was lost.

Fixes: deee69a19fd ("target/hppa: Convert memory management insns")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-13 09:16:36 -08:00
Helge Deller
881d1073d0 target/hppa: Mask reserved PSW bits in expand_sm_imm 
The system mask is a restricted subset of the psw, with only
a couple of reserved bits.  It is better to handle this up
front in the translator than require helper_swap_system_mask
to use cpu_hppa_get_psw and cpu_hppa_put_psw.

Signed-off-by: Helge Deller <deller@gmx.de>
[rth: Handle this in expand_sm_imm not helper_swap_system_mask.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-12 09:01:22 -08:00
Richard Henderson
f5b5c85760 target/hppa: Add unwind_breg to CPUHPPAState 
Fill in the insn_start value during form_gva, and copy
it out to the env field in hppa_restore_state_to_opc.
The value is not yet consumed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Helge Deller
4c34bab0d3 target/hppa: Clear upper bits in mtctl for pa1.x 
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Helge Deller
eb25d10f4d target/hppa: Add pa2.0 cpu local tlb flushes 
The previous decoding misnamed the bit it called "local".
Other than the name, the implementation was correct for pa1.x.
Rename this field to "tlbe".

PA2.0 adds (a real) local bit to PxTLB, and also adds a range
of pages to flush in GR[b].

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
b5caa17cda target/hppa: Implement pa2.0 data prefetch instructions 
These are aliased onto the normal integer loads to %g0.
Since we don't emulate caches, prefetch is a nop.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
bc3da3cf62 target/hppa: Return zero for r0 from load_gpr 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
a4db4a7811 target/hppa: Precompute zero into DisasContext 
Reduce the number of times we look for the constant 0.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
4e7abdb120 target/hppa: Implement PERMH 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
c2a7ee3f9d target/hppa: Implement MIXH, MIXW 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
3bbb8e4832 target/hppa: Implement HSHLADD, HSHRADD 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
151f309b98 target/hppa: Implement HSHL, HSHR 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
1b3cb7c874 target/hppa: Implement HAVG 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
10c9e58d5c target/hppa: Implement HSUB 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
0843563f3e target/hppa: Implement HADD 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
d265360f07 target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
aac0f603de target/hppa: Use tcg_temp_new_i64 not tcg_temp_new 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
967662cd5a target/hppa: Remove remaining TARGET_REGISTER_BITS redirections 
The conversions to/from i64 can be eliminated entirely,
folding computation into adjacent operations.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
6fd0c7bc91 target/hppa: Remove most of the TARGET_REGISTER_BITS redirections 
Remove all but those intended to change type to or from i64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
c53e401ed9 target/hppa: Remove TARGET_REGISTER_BITS 
Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
8577f35479 target/hppa: Implement IDTLBT, IITLBT 
Rename the existing insert tlb helpers to emphasize that they
are for pa1.1 cpus.  Implement a combined i/d tlb for pa2.0.
Still missing is the new 'P' tlb bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
25460fc5a7 target/hppa: Implement STDBY 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
a8966ba70a target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
f7b775a9c0 target/hppa: Implement SHRPD 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
bd792da354 target/hppa: Implement EXTRD 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
72ae4f2b82 target/hppa: Implement DEPD, DEPDI 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
51416c4e41 target/hppa: Implement LDD, LDCD, LDDA, STD, STDA 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
f25d316098 target/hppa: Decode ADDB double-word 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
c65c3ee16b target/hppa: Decode CMPIB double-word 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
e9efd4bcdc target/hppa: Decode d for cmpb instructions 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
84e224d422 target/hppa: Decode d for bb instructions 
Manipulate the shift count so that the bit to be tested
is always placed at the MSB.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
63c427c615 target/hppa: Decode d for sub instructions 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
faf97ba157 target/hppa: Decode d for add instructions 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
345aa35f15 target/hppa: Decode d for cmpclr instructions 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
af24075333 target/hppa: Decode d for unit instructions 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
fa8e3bed38 target/hppa: Decode d for logical instructions 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
08db178544 target/hppa: Remove TARGET_HPPA64 
Allow both user-only and system mode to run pa2.0 cpus.
Avoid creating a separate qemu-system-hppa64 binary;
force the qemu-hppa binary to use TARGET_ABI32.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:34 -08:00
Richard Henderson
59963d8fdf target/hppa: Pass d to do_unit_cond 
Hoist the resolution of d up one level above do_unit_cond.
All computations are logical, and are simplified by using a mask of the
correct width, after which the result may be compared with zero.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
4fa52edf91 target/hppa: Pass d to do_sed_cond 
Hoist the resolution of d up one level above do_sed_cond.
The MOVB comparison and the existing shift/extract/deposit
are all 32-bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
b5af84233d target/hppa: Pass d to do_log_cond 
Hoist the resolution of d up one level above do_log_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
4fe9533acc target/hppa: Pass d to do_sub_cond 
Hoist the resolution of d up one level above do_sub_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
a751eb31b6 target/hppa: Pass d to do_cond 
Hoist the resolution of d up one level above do_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Helge Deller
f3618f59f3 target/hppa: sar register allows only 5 bits on 32-bit CPU 
The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.

The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.

Signed-off-by: Helge Deller <deller@gmx.de>
 2023-11-06 18:49:33 -08:00
Richard Henderson
f13bf343cc target/hppa: Mask inputs in copy_iaoq_entry 
Ensure that the destination is always a valid GVA offset.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
9a91dd8452 target/hppa: Use copy_iaoq_entry for link in do_ibranch 
We need to make sure the link is masked properly along the
use_nullify_skip path.  The other three settings of a link
register already use this.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00
Richard Henderson
a01809737e target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb] 
This will be how we ensure that the IAOQ is always
valid per PSW.W, therefore all stores to these two
variables must be done with this function.

Use third argument -1 if the destination is always dynamic,
and fourth argument NULL if the destination is always static.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2023-11-06 18:49:33 -08:00