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  • 714b03c125 target/loongarch: Add loongarch kvm into meson build Tianrui Zhao 2024-01-05 15:58:04 +08:00
  • 8dcbad5128 target/loongarch: Implement set vcpu intr for kvm Tianrui Zhao 2024-01-10 10:41:52 +01:00
  • 2d45085a72 target/loongarch: Restrict TCG-specific code Tianrui Zhao 2024-01-10 10:41:51 +01:00
  • a05a950f2f target/loongarch: Implement kvm_arch_handle_exit Tianrui Zhao 2024-01-05 15:58:02 +08:00
  • d11681c94f target/loongarch: Implement kvm_arch_init_vcpu Tianrui Zhao 2024-01-05 15:58:01 +08:00
  • 41958c99e5 target/loongarch: Implement kvm_arch_init function Tianrui Zhao 2024-01-05 15:58:00 +08:00
  • f8447436d3 target/loongarch: Implement kvm get/set registers Tianrui Zhao 2024-01-05 15:57:59 +08:00
  • 6278465696 target/loongarch: Supplement vcpu env initial when vcpu reset Tianrui Zhao 2024-01-05 15:57:58 +08:00
  • 537ba9da17 target/loongarch: Define some kvm_arch interfaces Tianrui Zhao 2024-01-05 15:57:57 +08:00
  • 5817db6890 linux-headers: Synchronize linux headers from linux v6.7.0-rc8 Tianrui Zhao 2024-01-05 15:57:56 +08:00
  • f614acb745 Merge tag 'pull-target-arm-20240111' of https://git.linaro.org/people/pmaydell/qemu-arm into staging Peter Maydell 2024-01-11 11:05:44 +00:00
  • af09421f0d Merge tag 'pull-tcg-20240111' of https://gitlab.com/rth7680/qemu into staging Peter Maydell 2024-01-11 11:05:29 +00:00
  • cdd30f369a gitlab: fix s390x tag for avocado-system-centos Nicholas Piggin 2024-01-08 03:01:11 +10:00
  • c98873ee4a tests/qtest/virtio-ccw: Fix device presence checking Samuel Tardieu 2024-01-06 14:01:21 +01:00
  • f51d3fb14d qtest: ensure netdev-socket tests have non-overlapping names Daniel P. Berrangé 2024-01-04 16:29:42 +00:00
  • 9cd67f0cce net: handle QIOTask completion to report useful error message Daniel P. Berrangé 2024-01-04 16:29:41 +00:00
  • cc91ca64d8 net: add explicit info about connecting/listening state Daniel P. Berrangé 2024-01-04 16:29:40 +00:00
  • a298293866 Revert "tests/qtest/netdev-socket: Raise connection timeout to 120 seconds" Daniel P. Berrangé 2024-01-04 16:29:39 +00:00
  • 1a2253c712 Revert "osdep: add getloadavg" Daniel P. Berrangé 2024-01-04 16:29:38 +00:00
  • 9f7ac8e869 Revert "netdev: set timeout depending on loadavg" Daniel P. Berrangé 2024-01-04 16:29:37 +00:00
  • b01932889d qtest: use correct boolean type for failover property Daniel P. Berrangé 2024-01-03 12:30:05 +00:00
  • eea9f76300 q800: move dp8393x_prom memory region to Q800MachineState Mark Cave-Ayland 2023-12-27 21:02:12 +00:00
  • 1d513e06d9 util: fix build with musl libc on ppc64le Natanael Copa 2023-12-19 11:51:29 +01:00
  • ca5bed07d0 tcg/ppc: Use new registers for LQ destination Richard Henderson 2024-01-02 01:27:18 +00:00
  • afa37be4b4 tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates Paolo Bonzini 2023-12-28 13:05:24 +01:00
  • 64708db302 tcg/i386: convert add/sub of 128 to sub/add of -128 Paolo Bonzini 2023-12-28 13:05:14 +01:00
  • 34eac35f89 Merge tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu into staging Peter Maydell 2024-01-10 11:41:56 +00:00
  • eb7b9b2913 Merge tag 'qemu-sparc-20240110' of https://github.com/mcayland/qemu into staging Peter Maydell 2024-01-10 11:41:47 +00:00
  • 71b76da33a target/riscv: Ensure mideleg is set correctly on reset Alistair Francis 2024-01-08 10:13:28 +10:00
  • 1525d8aa3a target/riscv: Don't adjust vscause for exceptions Alistair Francis 2024-01-08 10:13:27 +10:00
  • 9a7c6da4cd target/riscv: Assert that the CSR numbers will be correct Alistair Francis 2024-01-08 10:13:26 +10:00
  • 1a25e59c62 target/riscv: pmp: Ignore writes when RW=01 and MML=0 Ivan Klokov 2023-12-20 18:32:05 +03:00
  • 2abf0da22c roms/opensbi: Upgrade from v1.3.1 to v1.4 Bin Meng 2024-01-02 22:47:33 +08:00
  • e0299f71b3 docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions Bin Meng 2024-01-04 15:15:23 +08:00
  • 3ca78c0689 target/riscv/kvm: add RVV and Vector CSR regs Daniel Henrique Barboza 2023-12-18 17:43:21 -03:00
  • 0d71f0a349 target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize() Daniel Henrique Barboza 2023-12-18 17:43:20 -03:00
  • 1583ca8aa6 linux-headers: riscv: add ptrace.h Daniel Henrique Barboza 2023-12-18 17:43:19 -03:00
  • efb91426af linux-headers: Update to Linux v6.7-rc5 Daniel Henrique Barboza 2023-12-18 17:43:18 -03:00
  • 871dad3a19 target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket Yong-Xuan Wang 2023-12-18 09:05:41 +00:00
  • dfa3c4c57e target/riscv: add rva22s64 cpu Daniel Henrique Barboza 2023-12-18 09:53:34 -03:00
  • af651969eb target/riscv: add RVA22S64 profile Daniel Henrique Barboza 2023-12-18 09:53:33 -03:00
  • 79593ca4b0 target/riscv: add 'parent' in profile description Daniel Henrique Barboza 2023-12-18 09:53:32 -03:00
  • 55398025e7 target/riscv: add satp_mode profile support Daniel Henrique Barboza 2023-12-18 09:53:31 -03:00
  • e7acc1cb93 target/riscv/cpu.c: add riscv_cpu_is_32bit() Daniel Henrique Barboza 2023-12-18 09:53:30 -03:00
  • ab77a9d507 target/riscv/cpu.c: finalize satp_mode earlier Daniel Henrique Barboza 2023-12-18 09:53:29 -03:00
  • 1a7d4fcb3f target/riscv: add priv ver restriction to profiles Daniel Henrique Barboza 2023-12-18 09:53:28 -03:00
  • 48531f5adb target/riscv: implement svade Daniel Henrique Barboza 2023-12-18 09:53:27 -03:00
  • fba92a92e3 target/riscv: add 'rva22u64' CPU Daniel Henrique Barboza 2023-12-18 09:53:26 -03:00
  • 6394b67615 riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Daniel Henrique Barboza 2023-12-18 09:53:25 -03:00
  • 2af005d610 target/riscv/tcg: validate profiles during finalize Daniel Henrique Barboza 2023-12-18 09:53:24 -03:00
  • 8b3b345105 target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza 2023-12-18 09:53:23 -03:00
  • 5187ba5b30 target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza 2023-12-18 09:53:22 -03:00
  • 3ba8462c4c target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza 2023-12-18 09:53:21 -03:00
  • a8c31f935c target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza 2023-12-18 09:53:20 -03:00
  • 21915d16c6 target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza 2023-12-18 09:53:19 -03:00
  • b30ea1677b target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza 2023-12-18 09:53:18 -03:00
  • 1a567c5cff target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza 2023-12-18 09:53:17 -03:00
  • 3f3618474a target/riscv: add rva22u64 profile definition Daniel Henrique Barboza 2023-12-18 09:53:16 -03:00
  • a88154835a riscv-qmp-cmds.c: expose named features in cpu_model_expansion Daniel Henrique Barboza 2023-12-18 09:53:15 -03:00
  • 5fe2800b85 target/riscv/tcg: add 'zic64b' support Daniel Henrique Barboza 2023-12-18 09:53:14 -03:00
  • cc2bf69a36 target/riscv: add zicbop extension flag Daniel Henrique Barboza 2023-12-18 09:53:13 -03:00
  • d379c748a3 target/riscv: add rv64i CPU Daniel Henrique Barboza 2023-12-18 09:53:12 -03:00
  • fdcefa91a1 target/riscv/tcg: update priv_ver on user_set extensions Daniel Henrique Barboza 2023-12-18 09:53:11 -03:00
  • 7fc3796219 target/riscv/tcg: do not use "!generic" CPU checks Daniel Henrique Barboza 2023-12-18 09:53:10 -03:00
  • ee557ad531 target/riscv: create TYPE_RISCV_VENDOR_CPU Daniel Henrique Barboza 2023-12-18 09:53:09 -03:00
  • 60db7a03c4 docs/system/riscv: document acpi parameter of virt machine Heinrich Schuchardt 2023-12-20 20:34:36 +01:00
  • 6c848c192e disas/riscv: Add amocas.[w,d,q] instructions Rob Bradford 2023-12-07 15:32:31 +00:00
  • b52d49e97f target/riscv: Add support for Zacas extension Weiwei Li 2023-12-07 15:32:30 +00:00
  • ca334e10dc hw/riscv/virt.c: fix the interrupts-extended property format of PLIC Yong-Xuan Wang 2023-12-18 09:05:40 +00:00
  • d641da6ed4 hw/riscv/virt-acpi-build.c: Add PLIC in MADT Sunil V L 2023-12-18 20:32:47 +05:30
  • 55ecd83b36 hw/riscv/virt-acpi-build.c: Add IO controllers and devices Sunil V L 2023-12-18 20:32:46 +05:30
  • e86e95270e hw/riscv/virt: Update GPEX MMIO related properties Sunil V L 2023-12-18 20:32:45 +05:30
  • 8f6a487488 hw/pci-host/gpex: Define properties for MMIO ranges Sunil V L 2023-12-18 20:32:44 +05:30
  • a52aea263e hw/riscv/virt-acpi-build.c: Add MMU node in RHCT Sunil V L 2023-12-18 20:32:43 +05:30
  • e810a5177c hw/riscv/virt-acpi-build.c: Add CMO information in RHCT Sunil V L 2023-12-18 20:32:42 +05:30
  • 7d189186f6 hw/riscv/virt-acpi-build.c: Add APLIC in the MADT Sunil V L 2023-12-18 20:32:41 +05:30
  • 66ac45b759 hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT Sunil V L 2023-12-18 20:32:40 +05:30
  • 0efb12b713 hw/riscv/virt-acpi-build.c: Add AIA support in RINTC Sunil V L 2023-12-18 20:32:39 +05:30
  • 68c8b403c7 hw/riscv: virt: Make few IMSIC macros and functions public Sunil V L 2023-12-18 20:32:38 +05:30
  • 8199bf48ea hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT Sunil V L 2023-12-18 20:32:37 +05:30
  • 57ba843628 hw/arm/virt-acpi-build.c: Migrate virtio creation to common location Sunil V L 2023-12-18 20:32:36 +05:30
  • 4c7f4f4f05 hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location Sunil V L 2023-12-18 20:32:35 +05:30
  • da14fc74d5 target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong() Daniel Henrique Barboza 2023-12-08 15:38:35 -03:00
  • f25974f46a target/riscv/kvm: add RISCV_CONFIG_REG() Daniel Henrique Barboza 2023-12-08 15:38:34 -03:00
  • 10f86d1b84 target/riscv/kvm: change timer regs size to u64 Daniel Henrique Barboza 2023-12-08 15:38:33 -03:00
  • 450bd6618f target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64 Daniel Henrique Barboza 2023-12-08 15:38:32 -03:00
  • 49c211ffca target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32 Daniel Henrique Barboza 2023-12-08 15:38:31 -03:00
  • 8d326cb88b target/riscv/cpu.c: fix machine IDs getters Daniel Henrique Barboza 2023-12-11 14:07:32 -03:00
  • 6f5bb7d405 target/riscv/pmp: Use hwaddr instead of target_ulong for RV32 Ivan Klokov 2023-11-23 12:12:14 +03:00
  • 7767f8b122 target/riscv: Not allow write mstatus_vs without RVV LIU Zhiwei 2023-12-15 10:33:13 +08:00
  • 564a28bda1 target/riscv: Fix th.dcache.cval1 priviledge check LIU Zhiwei 2023-12-08 17:43:15 +08:00
  • 79fc6d38a8 target/riscv: The whole vector register move instructions depend on vsew Max Chou 2023-11-30 01:03:58 +08:00
  • 4eff52cd46 target/riscv: Add vill check for whole vector register move instructions Max Chou 2023-11-30 01:03:57 +08:00
  • 995d8348eb util/fifo8: Introduce fifo8_peek_buf() Philippe Mathieu-Daudé 2023-11-09 20:28:06 +01:00
  • cd04033dbe util/fifo8: Allow fifo8_pop_buf() to not populate popped length Philippe Mathieu-Daudé 2023-11-09 20:28:05 +01:00
  • e2862554c2 target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs Peter Maydell 2024-01-09 14:43:57 +00:00
  • 3b32140e70 target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry Peter Maydell 2024-01-09 14:43:57 +00:00
  • bde0e60be4 target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps Peter Maydell 2024-01-09 14:43:56 +00:00
  • b1b7a2b555 hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers Peter Maydell 2024-01-09 14:43:56 +00:00
  • f5bd261a61 target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC) Peter Maydell 2024-01-09 14:43:56 +00:00