alwin.berger/FRET-qemu
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  • f13bf343cc target/hppa: Mask inputs in copy_iaoq_entry Richard Henderson 2023-10-26 19:03:34 -07:00
  • 9a91dd8452 target/hppa: Use copy_iaoq_entry for link in do_ibranch Richard Henderson 2023-10-26 18:55:54 -07:00
  • a01809737e target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb] Richard Henderson 2023-10-26 18:51:25 -07:00
  • 741322f471 target/hppa: Pass DisasContext to copy_iaoq_entry Richard Henderson 2023-10-26 18:34:01 -07:00
  • 698240d19b target/hppa: Fix hppa64 addressing Richard Henderson 2023-09-16 16:52:51 -07:00
  • 5718fe4cfe target/hppa: Adjust hppa_cpu_dump_state for hppa64 Richard Henderson 2023-09-19 15:43:57 +02:00
  • ccdf741c48 target/hppa: Handle absolute addresses for pa2.0 Richard Henderson 2023-09-17 14:54:16 -07:00
  • 931adff314 target/hppa: Update cpu_hppa_get/put_psw for hppa64 Richard Henderson 2023-09-21 10:13:35 +02:00
  • ca4c2008f5 target/hppa: Implement hppa_cpu_class_by_name Richard Henderson 2023-09-17 18:42:27 -07:00
  • d3ae32d4d2 target/hppa: Implement cpu_list Richard Henderson 2023-09-17 18:38:59 -07:00
  • 9cf2112be4 target/hppa: Make HPPA_BTLB_ENTRIES variable Richard Henderson 2023-10-12 17:46:55 -07:00
  • bd6243a33f target/hppa: Introduce TYPE_HPPA64_CPU Richard Henderson 2023-09-17 15:31:47 -07:00
  • d781cb7798 target/hppa: Fix extrw and depw with sar for hppa64 Richard Henderson 2023-09-19 16:07:14 +02:00
  • 1e9ab9fbe0 target/hppa: Fix bb_sar for hppa64 Richard Henderson 2023-10-17 16:39:47 -07:00
  • bdcccc17ac target/hppa: Fix do_add, do_sub for hppa64 Richard Henderson 2023-10-17 16:16:03 -07:00
  • 72ca87535e target/hppa: Fix trans_ds for hppa64 Richard Henderson 2023-09-16 16:28:23 -07:00
  • e1d635e871 target/hppa: Truncate rotate count in trans_shrpw_sar Richard Henderson 2023-09-16 16:22:14 -07:00
  • c1f55d9795 target/hppa: Fix load in do_load_32 Richard Henderson 2023-09-16 16:20:28 -07:00
  • 0238e678eb target/hppa: Fix hppa64 case in machine.c Richard Henderson 2023-09-16 16:19:27 -07:00
  • d4e5803316 target/hppa: Remove load_const Richard Henderson 2023-09-20 11:47:02 +02:00
  • a6779861fd target/hppa: Remove get_temp_tl Richard Henderson 2023-09-16 21:05:03 -07:00
  • e12c63090b target/hppa: Remove get_temp Richard Henderson 2023-09-16 21:02:42 -07:00
  • d7553f3591 target/hppa: Populate an interval tree with valid tlb entries Richard Henderson 2023-10-27 00:24:30 -07:00
  • 09cae8255f target/hppa: Split out hppa_flush_tlb_range Richard Henderson 2023-11-01 16:07:48 -07:00
  • f8cda28b8d target/hppa: Always report one page to tlb_set_page Richard Henderson 2023-10-27 01:09:21 -07:00
  • 66866cc74f target/hppa: Use IntervalTreeNode in HPPATLBEntry Richard Henderson 2023-10-26 22:21:47 -07:00
  • 729cd3506d target/hppa: Rename hppa_tlb_entry to HPPATLBEntry Richard Henderson 2023-10-26 22:13:12 -07:00
  • bb67ec32a0 target/hppa: Include PSW_P in tb flags and mmu index Richard Henderson 2023-11-01 15:17:04 -07:00
  • 80aaef96b1 Merge tag 'pull-block-2023-11-06' of https://gitlab.com/hreitz/qemu into staging Stefan Hajnoczi 2023-11-07 09:42:17 +08:00
  • f6b174ff96 Merge tag 'pull-target-arm-20231106' of https://git.linaro.org/people/pmaydell/qemu-arm into staging Stefan Hajnoczi 2023-11-07 09:42:07 +08:00
  • bb59f3548f Merge tag 'pull-vfio-20231106' of https://github.com/legoater/qemu into staging Stefan Hajnoczi 2023-11-07 09:41:52 +08:00
  • 17735e9371 Merge tag 'pull-hv-balloon-20231106' of https://github.com/maciejsszmigiero/qemu into staging Stefan Hajnoczi 2023-11-07 09:41:42 +08:00
  • 9f33cf2a89 Merge tag 'gpu-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging Stefan Hajnoczi 2023-11-07 09:41:33 +08:00
  • 54e97162db Merge tag 'pull-xenfv-stable-20231106' of git://git.infradead.org/users/dwmw2/qemu into staging Stefan Hajnoczi 2023-11-07 09:41:24 +08:00
  • b8cdbe0e4c Merge tag 'q800-for-8.2-pull-request' of https://github.com/vivier/qemu-m68k into staging Stefan Hajnoczi 2023-11-07 09:41:10 +08:00
  • bc5e844534 docs/about/deprecated: Document RISC-V "pmu-num" deprecation Rob Bradford 2023-10-31 15:37:17 +00:00
  • 69b3849bff target/riscv: Add "pmu-mask" property to replace "pmu-num" Rob Bradford 2023-10-31 15:37:16 +00:00
  • 2571a6427c target/riscv: Use existing PMU counter mask in FDT generation Rob Bradford 2023-10-31 15:37:15 +00:00
  • 7c1bb1d8d4 target/riscv: Don't assume PMU counters are continuous Rob Bradford 2023-10-31 15:37:14 +00:00
  • 755b41d09f target/riscv: Propagate error from PMU setup Rob Bradford 2023-10-31 15:37:13 +00:00
  • c541b07de7 target/riscv: cpu: Set the OpenTitan priv to 1.12.0 Alistair Francis 2023-11-02 10:34:24 +10:00
  • d53ead7206 hw/ssi: ibex_spi_host: Clear the interrupt even if disabled Alistair Francis 2023-11-02 10:34:23 +10:00
  • 251385fd44 disas/riscv: Replace TABs with space Max Chou 2023-10-26 23:18:21 +08:00
  • 9d92f56d4a disas/riscv: Add support for vector crypto extensions Max Chou 2023-10-26 23:18:20 +08:00
  • 434c609bef disas/riscv: Add rv_codec_vror_vi for vror.vi Max Chou 2023-10-26 23:18:19 +08:00
  • ea363626ff disas/riscv: Add rv_fmt_vd_vs2_uimm format Max Chou 2023-10-26 23:18:18 +08:00
  • ea61ef7097 target/riscv: Move vector crypto extensions to riscv_cpu_extensions Max Chou 2023-10-26 23:18:17 +08:00
  • b43419f2dc target/riscv: Expose Zvks[c|g] extnesion properties Max Chou 2023-10-26 23:18:16 +08:00
  • 8f913d1004 target/riscv: Add cfg properties for Zvks[c|g] extensions Max Chou 2023-10-26 23:18:15 +08:00
  • 23aaefb9c9 target/riscv: Expose Zvkn[c|g] extnesion properties Max Chou 2023-10-26 23:18:14 +08:00
  • 7cdc8ddb08 target/riscv: Add cfg properties for Zvkn[c|g] extensions Max Chou 2023-10-26 23:18:13 +08:00
  • f209cb0a83 target/riscv: Expose Zvkb extension property Max Chou 2023-10-26 23:18:12 +08:00
  • 1db699f8c2 target/riscv: Replace Zvbb checking by Zvkb Max Chou 2023-10-26 23:18:11 +08:00
  • 389b2e7014 target/riscv: Add cfg property for Zvkb extension Max Chou 2023-10-26 23:18:10 +08:00
  • 1c32b63066 target/riscv: Expose Zvkt extension property Max Chou 2023-10-26 23:18:09 +08:00
  • 5ddbc83ff2 target/riscv: Add cfg property for Zvkt extension Max Chou 2023-10-26 23:18:08 +08:00
  • c0ce1f2a88 MAINTAINERS: update mail address for Weiwei Li Weiwei Li 2023-10-30 16:16:07 +08:00
  • 2f32dcabc2 target/riscv: correct csr_ops[CSR_MSECCFG] Heinrich Schuchardt 2023-10-30 12:21:05 +02:00
  • 672ec6061f target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot Daniel Henrique Barboza 2023-10-31 17:51:50 -03:00
  • b4ceb3f2f3 target/riscv/kvm: add zihpm reg Daniel Henrique Barboza 2023-10-23 12:39:27 -03:00
  • 0824121660 target/riscv: add zihpm extension flag for TCG Daniel Henrique Barboza 2023-10-23 12:39:26 -03:00
  • b31dee8a7d target/riscv/kvm: add zicntr reg Daniel Henrique Barboza 2023-10-23 12:39:25 -03:00
  • c004099330 target/riscv: add zicntr extension flag for TCG Daniel Henrique Barboza 2023-10-23 12:39:24 -03:00
  • ac66f2f0d1 target/riscv: pmp: Ignore writes when RW=01 Mayuresh Chitale 2023-10-19 12:27:05 +05:30
  • 4bf501dc01 target/riscv: pmp: Clear pmp/smepmp bits on reset Mayuresh Chitale 2023-10-19 12:26:44 +05:30
  • 095fe72a12 Add epmp to extensions list and rename it to smepmp Himanshu Chauhan 2023-10-19 12:25:46 +05:30
  • a3abecbef0 target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion Daniel Henrique Barboza 2023-10-18 16:56:38 -03:00
  • ef58fad0fd target/riscv: add riscv_cpu_accelerator_compatible() Daniel Henrique Barboza 2023-10-18 16:56:37 -03:00
  • 1df4f540d6 target/riscv: handle custom props in qmp_query_cpu_model_expansion Daniel Henrique Barboza 2023-10-18 16:56:36 -03:00
  • a13a6082c7 target/riscv/tcg: add tcg_cpu_finalize_features() Daniel Henrique Barboza 2023-10-18 16:56:35 -03:00
  • aeb2bc5950 qapi,risc-v: add query-cpu-model-expansion Daniel Henrique Barboza 2023-10-18 16:56:34 -03:00
  • 456a65546f target/riscv/kvm/kvm-cpu.c: add missing property getters() Daniel Henrique Barboza 2023-10-18 16:56:33 -03:00
  • 257cfaed47 docs/system/riscv: update 'virt' machine core limit Daniel Henrique Barboza 2023-10-20 17:02:47 -03:00
  • 4d84cc5887 linux-user/riscv: change default cpu to 'max' Daniel Henrique Barboza 2023-10-20 04:45:01 -03:00
  • 40336d5b1d target/riscv: Add HS-mode virtual interrupt and IRQ filtering support. Rajnesh Kanwal 2023-10-16 12:17:36 +01:00
  • 1697837ed9 target/riscv: Add M-mode virtual interrupt and IRQ filtering support. Rajnesh Kanwal 2023-10-16 12:17:35 +01:00
  • 1ebad505f3 target/riscv: Split interrupt logic from riscv_cpu_update_mip. Rajnesh Kanwal 2023-10-16 12:17:34 +01:00
  • b901c7eb70 target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled Rajnesh Kanwal 2023-10-16 12:17:33 +01:00
  • d17bcae5f7 target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. Rajnesh Kanwal 2023-10-16 12:17:32 +01:00
  • a7b6917025 target/riscv: Without H-mode mask all HS mode inturrupts in mie. Rajnesh Kanwal 2023-10-16 12:17:31 +01:00
  • e57039ddab target/riscv: rename ext_icboz to ext_zicboz Daniel Henrique Barboza 2023-10-12 13:46:04 -03:00
  • a326a2b0b2 target/riscv: rename ext_icbom to ext_zicbom Daniel Henrique Barboza 2023-10-12 13:46:03 -03:00
  • 960b389b7d target/riscv: rename ext_icsr to ext_zicsr Daniel Henrique Barboza 2023-10-12 13:46:02 -03:00
  • 12b12a14c7 target/riscv: rename ext_ifencei to ext_zifencei Daniel Henrique Barboza 2023-10-12 13:46:01 -03:00
  • d36ce28be4 tcg/sparc64: Implement tcg_out_extrl_i64_i32 Richard Henderson 2023-10-24 14:17:07 -07:00
  • f245757701 tcg/optimize: Canonicalize sub2 with constants to add2 Richard Henderson 2023-10-25 18:39:44 -07:00
  • 6334a968ee tcg/optimize: Canonicalize subi to addi during optimization Richard Henderson 2023-10-25 18:39:43 -07:00
  • 1551004eeb tcg: Canonicalize subi to addi during opcode generation Richard Henderson 2023-10-25 18:39:42 -07:00
  • 26aac97c84 tcg/optimize: Split out arg_new_constant Richard Henderson 2023-10-23 12:31:57 -07:00
  • 3eaadaeb4e tcg: Eliminate duplicate env store operations Richard Henderson 2023-08-23 23:13:06 -07:00
  • ab84dc398b tcg/optimize: Optimize env memory operations Richard Henderson 2023-08-23 23:04:24 -07:00
  • 9f75e52828 tcg/optimize: Split out cmp_better_copy Richard Henderson 2023-11-02 13:37:46 -07:00
  • 986cac1d2a tcg/optimize: Pipe OptContext into reset_ts Richard Henderson 2023-01-09 13:59:35 -08:00
  • 9628d008bd tcg: Don't free vector results Richard Henderson 2023-08-23 20:35:05 -07:00
  • b701f195d3 tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} Richard Henderson 2023-10-25 21:14:04 -07:00
  • 0fbee2b764 tcg/loongarch64: Implement neg opcodes Richard Henderson 2023-10-25 21:14:03 -07:00
  • e0448a8b71 tcg/mips: Implement neg opcodes Richard Henderson 2023-10-25 21:14:02 -07:00
  • 3871be753f tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} Richard Henderson 2023-10-25 21:14:01 -07:00
  • 2cff741da8 tcg/mips: Always implement movcond Richard Henderson 2023-10-25 21:14:00 -07:00
  • 42221a64da tcg/mips: Split out tcg_out_setcond_int Richard Henderson 2023-10-25 21:13:59 -07:00