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Romain Malmain 67dabac1ed v9.1.1 release 
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Merge tag 'v9.1.1' into update_qemu_9_1_0

v9.1.1 release
2024-10-25 22:10:51 +02:00
..
insn_trans
target/riscv: Relax fld alignment requirement
2024-08-06 14:18:41 +10:00
kvm
target/riscv/kvm: update KVM regs to Linux 6.10-rc5
2024-07-18 12:08:44 +10:00
tcg
target/riscv: Add zcmop extension
2024-07-18 12:00:42 +10:00
arch_dump.c
target/riscv: Fix format for comments
2023-05-05 10:49:50 +10:00
bitmanip_helper.c
target/riscv: rvk: add support for zbkx extension
2022-04-29 10:47:45 +10:00
common-semi-target.h
semihosting: Split out common-semi-target.h
2022-06-28 04:35:07 +05:30
cpu_bits.h
target/riscv: Add cycle & instret privilege mode filtering support
2024-07-18 12:08:44 +10:00
cpu_cfg.h
target/riscv: Add cycle & instret privilege mode filtering properties
2024-07-18 12:08:44 +10:00
cpu_helper.c
target/riscv: Implement privilege mode filtering for cycle/instret
2024-07-18 12:08:44 +10:00
cpu_user.h
Supply missing header guards
2019-06-12 13:20:21 +02:00
cpu_vendorid.h
target/riscv: add Ventana's Veyron V1 CPU
2023-05-05 10:49:50 +10:00
cpu-param.h
target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'
2024-04-26 15:31:37 +02:00
cpu-qom.h
target/riscv: add rv32i, rv32e and rv64e CPUs
2024-02-09 20:49:41 +10:00
cpu.c
target/riscv: Expose the Smcntrpmf config
2024-07-18 12:08:45 +10:00
cpu.h
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
2024-07-18 12:08:45 +10:00
crypto_helper.c
target/riscv: Use accelerated helper for AES64KS1I
2023-09-11 11:45:55 +10:00
csr.c
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
2024-07-18 12:08:45 +10:00
debug.c
target/riscv: Apply modularized matching conditions for icount trigger
2024-06-27 13:09:16 +10:00
debug.h
exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header
2024-04-26 17:03:05 +02:00
fpu_helper.c
target/riscv: Fix froundnx.h nanbox check
2024-06-26 23:02:35 +10:00
gdbstub.c
riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
2024-06-05 13:07:02 +03:00
helper.h
target/riscv: Raise exceptions on wrs.nto
2024-06-03 11:12:11 +10:00
insn16.decode
target/riscv: Add zcmop extension
2024-07-18 12:00:42 +10:00
insn32.decode
target/riscv: Add amocas.[b|h] for Zabha
2024-07-18 12:00:42 +10:00
instmap.h
target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
2022-09-07 09:18:32 +02:00
internals.h
target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation
2024-07-11 11:41:34 +01:00
Kconfig
target/riscv: Restrict semihosting to TCG
2024-07-22 09:38:11 +01:00
m128_helper.c
target/helpers: Remove unnecessary 'qemu/main-loop.h' header
2023-08-31 19:47:43 +02:00
machine.c
target/riscv: Save counter values during countinhibit update
2024-07-18 12:08:44 +10:00
meson.build
riscv: thead: Add th.sxstatus CSR emulation
2024-06-03 11:12:12 +10:00
monitor.c
riscv: spelling fixes
2023-09-08 13:08:52 +03:00
op_helper.c
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
2024-07-18 12:08:45 +10:00
pmp.c
exec/cpu: Extract page-protection definitions to page-protection.h
2024-05-06 11:17:15 +02:00
pmp.h
target/riscv/pmp: Use hwaddr instead of target_ulong for RV32
2024-01-10 18:47:46 +10:00
pmu.c
target/riscv: Add asserts for out-of-bound access
2024-08-06 14:20:16 +10:00
pmu.h
target/riscv: More accurately model priv mode filtering.
2024-07-18 12:08:45 +10:00
riscv-qmp-cmds.c
target: Improve error reporting for CpuModelInfo member @props
2024-03-12 14:03:00 +01:00
sbi_ecall_interface.h
target/riscv/kvm: implement SBI debug console (DBCN) calls
2024-06-03 11:12:11 +10:00
th_csr.c
riscv: thead: Add th.sxstatus CSR emulation
2024-06-03 11:12:12 +10:00
time_helper.c
target/riscv: Simplify type conversion for CPURISCVState
2023-05-05 10:49:49 +10:00
time_helper.h
target/riscv: Simplify type conversion for CPURISCVState
2023-05-05 10:49:49 +10:00
trace-events
target/riscv: Add ePMP CSR access functions
2021-05-11 20:02:06 +10:00
trace.h
trace: switch position of headers to what Meson requires
2020-08-21 06:18:24 -04:00
translate.c
v9.1.1 release
2024-10-25 22:10:51 +02:00
vcrypto_helper.c
target/riscv/vector_helpers: do early exit when vstart >= vl
2024-03-22 15:20:02 +10:00
vector_helper.c
target/riscv: Simplify probing in vext_ldff
2024-07-23 10:57:42 +10:00
vector_internals.c
target/riscv: Fix the element agnostic function problem
2024-06-05 13:03:44 +03:00
vector_internals.h
target/riscv/vector_helpers: do early exit when vstart >= vl
2024-03-22 15:20:02 +10:00
xthead.decode
RISC-V: Adding XTheadFmv ISA extension
2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode
target/riscv: Add XVentanaCondOps custom extension
2022-02-16 12:24:18 +10:00
zce_helper.c
target/riscv: add support for Zcmt extension
2023-05-05 10:49:50 +10:00