a1750b2cba
The OCC is an On Chip Controller that handles various thermal and power management. It is a PPC405 microcontroller that runs its own firmware which is out of scope of the powernv machine model. Some dynamic behaviour and interfaces that are important for host CPU testing can be implemented with a much simpler state machine. This change adds a 100ms timer that ticks through a simple state machine that looks for "OCC command requests" coming from host firmware, and responds to them. For now the powercap command is implemented because that is used by OPAL and exported to Linux and is easy to test. $ F=/sys/firmware/opal/powercap/system-powercap/powercap-current $ cat $F 100 $ echo 50 | sudo tee $F 50 $ cat $F 50 Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
73 lines
2.1 KiB
C
73 lines
2.1 KiB
C
/*
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* QEMU PowerPC PowerNV Emulation of a few OCC related registers
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*
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* Copyright (c) 2015-2022, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PPC_PNV_OCC_H
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#define PPC_PNV_OCC_H
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#include "exec/memory.h"
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#include "hw/qdev-core.h"
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#define TYPE_PNV_OCC "pnv-occ"
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OBJECT_DECLARE_TYPE(PnvOCC, PnvOCCClass,
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PNV_OCC)
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#define TYPE_PNV8_OCC TYPE_PNV_OCC "-POWER8"
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DECLARE_INSTANCE_CHECKER(PnvOCC, PNV8_OCC,
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TYPE_PNV8_OCC)
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#define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9"
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DECLARE_INSTANCE_CHECKER(PnvOCC, PNV9_OCC,
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TYPE_PNV9_OCC)
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#define TYPE_PNV10_OCC TYPE_PNV_OCC "-POWER10"
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DECLARE_INSTANCE_CHECKER(PnvOCC, PNV10_OCC, TYPE_PNV10_OCC)
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#define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
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#define PNV_OCC_SENSOR_DATA_BLOCK_SIZE 0x00025800
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struct PnvOCC {
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DeviceState xd;
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/* OCC dynamic model is driven by this timer. */
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QEMUTimer state_machine_timer;
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/* OCC Misc interrupt */
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uint64_t occmisc;
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qemu_irq psi_irq;
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/* OCCs operate on regions of HOMER memory */
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PnvHomer *homer;
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MemoryRegion xscom_regs;
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MemoryRegion sram_regs;
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};
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struct PnvOCCClass {
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DeviceClass parent_class;
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hwaddr opal_shared_memory_offset; /* offset in HOMER */
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uint8_t opal_shared_memory_version;
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int xscom_size;
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const MemoryRegionOps *xscom_ops;
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};
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#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \
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(PNV_OCC_SENSOR_DATA_BLOCK_OFFSET + (i) * PNV_OCC_SENSOR_DATA_BLOCK_SIZE)
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#endif /* PPC_PNV_OCC_H */
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