b8d5503a3e
In expression 1ULL << tlb_ps, left shifting by more than 63 bits has
undefined behavior. The shift amount, tlb_ps, is as much as 64. check
"tlb_ps >=64" to fix.
Resolves: Coverity CID 1593475
Fixes: d882c284a3 ("target/loongarch: check tlb_ps")
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
139 lines
3.2 KiB
C
139 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* LoongArch emulation helpers for CSRs
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "internals.h"
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#include "qemu/host-utils.h"
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#include "exec/helper-proto.h"
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#include "exec/cputlb.h"
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#include "exec/cpu_ldst.h"
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#include "hw/irq.h"
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#include "cpu-csr.h"
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target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
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{
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int64_t old_v = env->CSR_STLBPS;
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/*
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* The real hardware only supports the min tlb_ps is 12
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* tlb_ps=0 may cause undefined-behavior.
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*/
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uint8_t tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
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if (!check_ps(env, tlb_ps)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Attempted set ps %d\n", tlb_ps);
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}
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return old_v;
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}
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target_ulong helper_csrrd_pgd(CPULoongArchState *env)
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{
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int64_t v;
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if (env->CSR_TLBRERA & 0x1) {
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v = env->CSR_TLBRBADV;
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} else {
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v = env->CSR_BADV;
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}
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if ((v >> 63) & 0x1) {
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v = env->CSR_PGDH;
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} else {
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v = env->CSR_PGDL;
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}
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return v;
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}
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target_ulong helper_csrrd_cpuid(CPULoongArchState *env)
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{
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LoongArchCPU *lac = env_archcpu(env);
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env->CSR_CPUID = CPU(lac)->cpu_index;
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return env->CSR_CPUID;
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}
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target_ulong helper_csrrd_tval(CPULoongArchState *env)
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{
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LoongArchCPU *cpu = env_archcpu(env);
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return cpu_loongarch_get_constant_timer_ticks(cpu);
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}
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target_ulong helper_csrwr_estat(CPULoongArchState *env, target_ulong val)
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{
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int64_t old_v = env->CSR_ESTAT;
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/* Only IS[1:0] can be written */
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env->CSR_ESTAT = deposit64(env->CSR_ESTAT, 0, 2, val);
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return old_v;
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}
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target_ulong helper_csrwr_asid(CPULoongArchState *env, target_ulong val)
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{
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int64_t old_v = env->CSR_ASID;
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/* Only ASID filed of CSR_ASID can be written */
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env->CSR_ASID = deposit64(env->CSR_ASID, 0, 10, val);
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if (old_v != env->CSR_ASID) {
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tlb_flush(env_cpu(env));
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}
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return old_v;
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}
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target_ulong helper_csrwr_tcfg(CPULoongArchState *env, target_ulong val)
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{
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LoongArchCPU *cpu = env_archcpu(env);
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int64_t old_v = env->CSR_TCFG;
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cpu_loongarch_store_constant_timer_config(cpu, val);
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return old_v;
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}
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target_ulong helper_csrwr_ticlr(CPULoongArchState *env, target_ulong val)
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{
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LoongArchCPU *cpu = env_archcpu(env);
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int64_t old_v = 0;
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if (val & 0x1) {
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bql_lock();
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loongarch_cpu_set_irq(cpu, IRQ_TIMER, 0);
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bql_unlock();
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}
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return old_v;
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}
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target_ulong helper_csrwr_pwcl(CPULoongArchState *env, target_ulong val)
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{
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uint8_t shift, ptbase;
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int64_t old_v = env->CSR_PWCL;
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/*
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* The real hardware only supports 64bit PTE width now, 128bit or others
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* treated as illegal.
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*/
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shift = FIELD_EX64(val, CSR_PWCL, PTEWIDTH);
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ptbase = FIELD_EX64(val, CSR_PWCL, PTBASE);
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if (shift) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Attempted set pte width with %d bit\n", 64 << shift);
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val = FIELD_DP64(val, CSR_PWCL, PTEWIDTH, 0);
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}
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if (!check_ps(env, ptbase)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Attrmpted set ptbase 2^%d\n", ptbase);
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}
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env->CSR_PWCL =val;
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return old_v;
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}
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