6b8abd244b
For loongarch, mips, riscv and sparc, a zero register is available all the time. For aarch64, register index 31 depends on context: sometimes it is the stack pointer, and sometimes it is the zero register. Introduce a new general-purpose constraint which maps 0 to TCG_REG_ZERO, if defined. This differs from existing constant constraints in that const_arg[*] is recorded as false, indicating that the value is in a register. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
53 lines
1.6 KiB
C
53 lines
1.6 KiB
C
/*
|
|
* Initial TCG Implementation for aarch64
|
|
*
|
|
* Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH
|
|
* Written by Claudio Fontana
|
|
*
|
|
* This work is licensed under the terms of the GNU GPL, version 2 or
|
|
* (at your option) any later version.
|
|
*
|
|
* See the COPYING file in the top-level directory for details.
|
|
*/
|
|
|
|
#ifndef AARCH64_TCG_TARGET_H
|
|
#define AARCH64_TCG_TARGET_H
|
|
|
|
#define TCG_TARGET_INSN_UNIT_SIZE 4
|
|
#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
|
|
|
|
typedef enum {
|
|
TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
|
|
TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,
|
|
TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,
|
|
TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
|
|
TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19,
|
|
TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23,
|
|
TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27,
|
|
TCG_REG_X28, TCG_REG_X29, TCG_REG_X30,
|
|
|
|
/* X31 is either the stack pointer or zero, depending on context. */
|
|
TCG_REG_SP = 31,
|
|
TCG_REG_XZR = 31,
|
|
|
|
TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
|
|
TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
|
|
TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
|
|
TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
|
|
TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
|
|
TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
|
|
TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
|
|
TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
|
|
|
|
/* Aliases. */
|
|
TCG_REG_FP = TCG_REG_X29,
|
|
TCG_REG_LR = TCG_REG_X30,
|
|
TCG_AREG0 = TCG_REG_X19,
|
|
} TCGReg;
|
|
|
|
#define TCG_REG_ZERO TCG_REG_XZR
|
|
|
|
#define TCG_TARGET_NB_REGS 64
|
|
|
|
#endif /* AARCH64_TCG_TARGET_H */
|