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FRET-qemu/include/hw/misc/xlnx-versal-cframe-reg.h
Romain Malmain 7c3c7877d8 Update to QEMU 9.0.0 (#67) 
* Update to QEMU v9.0.0

---------

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Zheyu Ma <zheyuma97@gmail.com>
Signed-off-by: Ido Plat <ido.plat@ibm.com>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Signed-off-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Thomas Lamprecht <t.lamprecht@proxmox.com>
Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
Signed-off-by: Gregory Price <gregory.price@memverge.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Lorenz Brun <lorenz@brun.one>
Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Joonas Kankaala <joonas.a.kankaala@gmail.com>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Oleg Sviridov <oleg.sviridov@red-soft.ru>
Signed-off-by: Artem Chernyshev <artem.chernyshev@red-soft.ru>
Signed-off-by: Yajun Wu <yajunw@nvidia.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
Signed-off-by: Lei Wang <lei4.wang@intel.com>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Signed-off-by: Martin Hundebøll <martin@geanix.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Wafer <wafer@jaguarmicro.com>
Signed-off-by: Yuxue Liu <yuxue.liu@jaguarmicro.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Nguyen Dinh Phi <phind.uet@gmail.com>
Signed-off-by: Zack Buhman <zack@buhman.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Yuquan Wang wangyuquan1236@phytium.com.cn
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Cindy Lu <lulu@redhat.com>
Co-authored-by: Peter Maydell <peter.maydell@linaro.org>
Co-authored-by: Fabiano Rosas <farosas@suse.de>
Co-authored-by: Peter Xu <peterx@redhat.com>
Co-authored-by: Thomas Huth <thuth@redhat.com>
Co-authored-by: Cédric Le Goater <clg@redhat.com>
Co-authored-by: Zheyu Ma <zheyuma97@gmail.com>
Co-authored-by: Ido Plat <ido.plat@ibm.com>
Co-authored-by: Ilya Leoshkevich <iii@linux.ibm.com>
Co-authored-by: Markus Armbruster <armbru@redhat.com>
Co-authored-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Co-authored-by: Paolo Bonzini <pbonzini@redhat.com>
Co-authored-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Co-authored-by: David Hildenbrand <david@redhat.com>
Co-authored-by: Kevin Wolf <kwolf@redhat.com>
Co-authored-by: Stefan Reiter <s.reiter@proxmox.com>
Co-authored-by: Fiona Ebner <f.ebner@proxmox.com>
Co-authored-by: Gregory Price <gregory.price@memverge.com>
Co-authored-by: Lorenz Brun <lorenz@brun.one>
Co-authored-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
Co-authored-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Co-authored-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Co-authored-by: BALATON Zoltan <balaton@eik.bme.hu>
Co-authored-by: Igor Mammedov <imammedo@redhat.com>
Co-authored-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Co-authored-by: Sven Schnelle <svens@stackframe.org>
Co-authored-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Co-authored-by: Helge Deller <deller@kernel.org>
Co-authored-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Co-authored-by: Benjamin Gray <bgray@linux.ibm.com>
Co-authored-by: Nicholas Piggin <npiggin@gmail.com>
Co-authored-by: Avihai Horon <avihaih@nvidia.com>
Co-authored-by: Michael Tokarev <mjt@tls.msk.ru>
Co-authored-by: Joonas Kankaala <joonas.a.kankaala@gmail.com>
Co-authored-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Co-authored-by: Stefan Weil <sw@weilnetz.de>
Co-authored-by: Dayu Liu <liu.dayu@zte.com.cn>
Co-authored-by: Zhao Liu <zhao1.liu@intel.com>
Co-authored-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Co-authored-by: Artem Chernyshev <artem.chernyshev@red-soft.ru>
Co-authored-by: Yajun Wu <yajunw@nvidia.com>
Co-authored-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Co-authored-by: Pierre-Clément Tosi <ptosi@google.com>
Co-authored-by: Wei Wang <wei.w.wang@intel.com>
Co-authored-by: Martin Hundebøll <martin@geanix.com>
Co-authored-by: Michael S. Tsirkin <mst@redhat.com>
Co-authored-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Co-authored-by: Wafer <wafer@jaguarmicro.com>
Co-authored-by: lyx634449800 <yuxue.liu@jaguarmicro.com>
Co-authored-by: Gerd Hoffmann <kraxel@redhat.com>
Co-authored-by: Nguyen Dinh Phi <phind.uet@gmail.com>
Co-authored-by: Zack Buhman <zack@buhman.org>
Co-authored-by: Keith Packard <keithp@keithp.com>
Co-authored-by: Yuquan Wang <wangyuquan1236@phytium.com.cn>
Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Co-authored-by: Cindy Lu <lulu@redhat.com>
2024-05-01 16:10:20 +02:00

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/*
* QEMU model of the Configuration Frame Control module
*
* Copyright (C) 2023, Advanced Micro Devices, Inc.
*
* Written by Francisco Iglesias <francisco.iglesias@amd.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*
* References:
* [1] Versal ACAP Technical Reference Manual,
* https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
*
* [2] Versal ACAP Register Reference,
* https://docs.xilinx.com/r/en-US/am012-versal-register-reference/CFRAME_REG-Module
*/
#ifndef HW_MISC_XLNX_VERSAL_CFRAME_REG_H
#define HW_MISC_XLNX_VERSAL_CFRAME_REG_H
#include "hw/sysbus.h"
#include "hw/register.h"
#include "hw/misc/xlnx-cfi-if.h"
#include "hw/misc/xlnx-versal-cfu.h"
#include "qemu/fifo32.h"
#define TYPE_XLNX_VERSAL_CFRAME_REG "xlnx-cframe-reg"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFrameReg, XLNX_VERSAL_CFRAME_REG)
#define TYPE_XLNX_VERSAL_CFRAME_BCAST_REG "xlnx.cframe-bcast-reg"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFrameBcastReg,
XLNX_VERSAL_CFRAME_BCAST_REG)
/*
* The registers in this module are 128 bits wide but it is ok to write
* and read them through 4 sequential 32 bit accesses (address[3:2] = 0,
* 1, 2, 3).
*/
REG32(CRC0, 0x0)
FIELD(CRC, CRC, 0, 32)
REG32(CRC1, 0x4)
REG32(CRC2, 0x8)
REG32(CRC3, 0xc)
REG32(FAR0, 0x10)
FIELD(FAR0, SEGMENT, 23, 2)
FIELD(FAR0, BLOCKTYPE, 20, 3)
FIELD(FAR0, FRAME_ADDR, 0, 20)
REG32(FAR1, 0x14)
REG32(FAR2, 0x18)
REG32(FAR3, 0x1c)
REG32(FAR_SFR0, 0x20)
FIELD(FAR_SFR0, BLOCKTYPE, 20, 3)
FIELD(FAR_SFR0, FRAME_ADDR, 0, 20)
REG32(FAR_SFR1, 0x24)
REG32(FAR_SFR2, 0x28)
REG32(FAR_SFR3, 0x2c)
REG32(FDRI0, 0x40)
REG32(FDRI1, 0x44)
REG32(FDRI2, 0x48)
REG32(FDRI3, 0x4c)
REG32(FRCNT0, 0x50)
FIELD(FRCNT0, FRCNT, 0, 32)
REG32(FRCNT1, 0x54)
REG32(FRCNT2, 0x58)
REG32(FRCNT3, 0x5c)
REG32(CMD0, 0x60)
FIELD(CMD0, CMD, 0, 5)
REG32(CMD1, 0x64)
REG32(CMD2, 0x68)
REG32(CMD3, 0x6c)
REG32(CR_MASK0, 0x70)
REG32(CR_MASK1, 0x74)
REG32(CR_MASK2, 0x78)
REG32(CR_MASK3, 0x7c)
REG32(CTL0, 0x80)
FIELD(CTL, PER_FRAME_CRC, 0, 1)
REG32(CTL1, 0x84)
REG32(CTL2, 0x88)
REG32(CTL3, 0x8c)
REG32(CFRM_ISR0, 0x150)
FIELD(CFRM_ISR0, READ_BROADCAST_ERROR, 21, 1)
FIELD(CFRM_ISR0, CMD_MISSING_ERROR, 20, 1)
FIELD(CFRM_ISR0, RW_ROWOFF_ERROR, 19, 1)
FIELD(CFRM_ISR0, READ_REG_ADDR_ERROR, 18, 1)
FIELD(CFRM_ISR0, READ_BLK_TYPE_ERROR, 17, 1)
FIELD(CFRM_ISR0, READ_FRAME_ADDR_ERROR, 16, 1)
FIELD(CFRM_ISR0, WRITE_REG_ADDR_ERROR, 15, 1)
FIELD(CFRM_ISR0, WRITE_BLK_TYPE_ERROR, 13, 1)
FIELD(CFRM_ISR0, WRITE_FRAME_ADDR_ERROR, 12, 1)
FIELD(CFRM_ISR0, MFW_OVERRUN_ERROR, 11, 1)
FIELD(CFRM_ISR0, FAR_FIFO_UNDERFLOW, 10, 1)
FIELD(CFRM_ISR0, FAR_FIFO_OVERFLOW, 9, 1)
FIELD(CFRM_ISR0, PER_FRAME_SEQ_ERROR, 8, 1)
FIELD(CFRM_ISR0, CRC_ERROR, 7, 1)
FIELD(CFRM_ISR0, WRITE_OVERRUN_ERROR, 6, 1)
FIELD(CFRM_ISR0, READ_OVERRUN_ERROR, 5, 1)
FIELD(CFRM_ISR0, CMD_INTERRUPT_ERROR, 4, 1)
FIELD(CFRM_ISR0, WRITE_INTERRUPT_ERROR, 3, 1)
FIELD(CFRM_ISR0, READ_INTERRUPT_ERROR, 2, 1)
FIELD(CFRM_ISR0, SEU_CRC_ERROR, 1, 1)
FIELD(CFRM_ISR0, SEU_ECC_ERROR, 0, 1)
REG32(CFRM_ISR1, 0x154)
REG32(CFRM_ISR2, 0x158)
REG32(CFRM_ISR3, 0x15c)
REG32(CFRM_IMR0, 0x160)
FIELD(CFRM_IMR0, READ_BROADCAST_ERROR, 21, 1)
FIELD(CFRM_IMR0, CMD_MISSING_ERROR, 20, 1)
FIELD(CFRM_IMR0, RW_ROWOFF_ERROR, 19, 1)
FIELD(CFRM_IMR0, READ_REG_ADDR_ERROR, 18, 1)
FIELD(CFRM_IMR0, READ_BLK_TYPE_ERROR, 17, 1)
FIELD(CFRM_IMR0, READ_FRAME_ADDR_ERROR, 16, 1)
FIELD(CFRM_IMR0, WRITE_REG_ADDR_ERROR, 15, 1)
FIELD(CFRM_IMR0, WRITE_BLK_TYPE_ERROR, 13, 1)
FIELD(CFRM_IMR0, WRITE_FRAME_ADDR_ERROR, 12, 1)
FIELD(CFRM_IMR0, MFW_OVERRUN_ERROR, 11, 1)
FIELD(CFRM_IMR0, FAR_FIFO_UNDERFLOW, 10, 1)
FIELD(CFRM_IMR0, FAR_FIFO_OVERFLOW, 9, 1)
FIELD(CFRM_IMR0, PER_FRAME_SEQ_ERROR, 8, 1)
FIELD(CFRM_IMR0, CRC_ERROR, 7, 1)
FIELD(CFRM_IMR0, WRITE_OVERRUN_ERROR, 6, 1)
FIELD(CFRM_IMR0, READ_OVERRUN_ERROR, 5, 1)
FIELD(CFRM_IMR0, CMD_INTERRUPT_ERROR, 4, 1)
FIELD(CFRM_IMR0, WRITE_INTERRUPT_ERROR, 3, 1)
FIELD(CFRM_IMR0, READ_INTERRUPT_ERROR, 2, 1)
FIELD(CFRM_IMR0, SEU_CRC_ERROR, 1, 1)
FIELD(CFRM_IMR0, SEU_ECC_ERROR, 0, 1)
REG32(CFRM_IMR1, 0x164)
REG32(CFRM_IMR2, 0x168)
REG32(CFRM_IMR3, 0x16c)
REG32(CFRM_IER0, 0x170)
FIELD(CFRM_IER0, READ_BROADCAST_ERROR, 21, 1)
FIELD(CFRM_IER0, CMD_MISSING_ERROR, 20, 1)
FIELD(CFRM_IER0, RW_ROWOFF_ERROR, 19, 1)
FIELD(CFRM_IER0, READ_REG_ADDR_ERROR, 18, 1)
FIELD(CFRM_IER0, READ_BLK_TYPE_ERROR, 17, 1)
FIELD(CFRM_IER0, READ_FRAME_ADDR_ERROR, 16, 1)
FIELD(CFRM_IER0, WRITE_REG_ADDR_ERROR, 15, 1)
FIELD(CFRM_IER0, WRITE_BLK_TYPE_ERROR, 13, 1)
FIELD(CFRM_IER0, WRITE_FRAME_ADDR_ERROR, 12, 1)
FIELD(CFRM_IER0, MFW_OVERRUN_ERROR, 11, 1)
FIELD(CFRM_IER0, FAR_FIFO_UNDERFLOW, 10, 1)
FIELD(CFRM_IER0, FAR_FIFO_OVERFLOW, 9, 1)
FIELD(CFRM_IER0, PER_FRAME_SEQ_ERROR, 8, 1)
FIELD(CFRM_IER0, CRC_ERROR, 7, 1)
FIELD(CFRM_IER0, WRITE_OVERRUN_ERROR, 6, 1)
FIELD(CFRM_IER0, READ_OVERRUN_ERROR, 5, 1)
FIELD(CFRM_IER0, CMD_INTERRUPT_ERROR, 4, 1)
FIELD(CFRM_IER0, WRITE_INTERRUPT_ERROR, 3, 1)
FIELD(CFRM_IER0, READ_INTERRUPT_ERROR, 2, 1)
FIELD(CFRM_IER0, SEU_CRC_ERROR, 1, 1)
FIELD(CFRM_IER0, SEU_ECC_ERROR, 0, 1)
REG32(CFRM_IER1, 0x174)
REG32(CFRM_IER2, 0x178)
REG32(CFRM_IER3, 0x17c)
REG32(CFRM_IDR0, 0x180)
FIELD(CFRM_IDR0, READ_BROADCAST_ERROR, 21, 1)
FIELD(CFRM_IDR0, CMD_MISSING_ERROR, 20, 1)
FIELD(CFRM_IDR0, RW_ROWOFF_ERROR, 19, 1)
FIELD(CFRM_IDR0, READ_REG_ADDR_ERROR, 18, 1)
FIELD(CFRM_IDR0, READ_BLK_TYPE_ERROR, 17, 1)
FIELD(CFRM_IDR0, READ_FRAME_ADDR_ERROR, 16, 1)
FIELD(CFRM_IDR0, WRITE_REG_ADDR_ERROR, 15, 1)
FIELD(CFRM_IDR0, WRITE_BLK_TYPE_ERROR, 13, 1)
FIELD(CFRM_IDR0, WRITE_FRAME_ADDR_ERROR, 12, 1)
FIELD(CFRM_IDR0, MFW_OVERRUN_ERROR, 11, 1)
FIELD(CFRM_IDR0, FAR_FIFO_UNDERFLOW, 10, 1)
FIELD(CFRM_IDR0, FAR_FIFO_OVERFLOW, 9, 1)
FIELD(CFRM_IDR0, PER_FRAME_SEQ_ERROR, 8, 1)
FIELD(CFRM_IDR0, CRC_ERROR, 7, 1)
FIELD(CFRM_IDR0, WRITE_OVERRUN_ERROR, 6, 1)
FIELD(CFRM_IDR0, READ_OVERRUN_ERROR, 5, 1)
FIELD(CFRM_IDR0, CMD_INTERRUPT_ERROR, 4, 1)
FIELD(CFRM_IDR0, WRITE_INTERRUPT_ERROR, 3, 1)
FIELD(CFRM_IDR0, READ_INTERRUPT_ERROR, 2, 1)
FIELD(CFRM_IDR0, SEU_CRC_ERROR, 1, 1)
FIELD(CFRM_IDR0, SEU_ECC_ERROR, 0, 1)
REG32(CFRM_IDR1, 0x184)
REG32(CFRM_IDR2, 0x188)
REG32(CFRM_IDR3, 0x18c)
REG32(CFRM_ITR0, 0x190)
FIELD(CFRM_ITR0, READ_BROADCAST_ERROR, 21, 1)
FIELD(CFRM_ITR0, CMD_MISSING_ERROR, 20, 1)
FIELD(CFRM_ITR0, RW_ROWOFF_ERROR, 19, 1)
FIELD(CFRM_ITR0, READ_REG_ADDR_ERROR, 18, 1)
FIELD(CFRM_ITR0, READ_BLK_TYPE_ERROR, 17, 1)
FIELD(CFRM_ITR0, READ_FRAME_ADDR_ERROR, 16, 1)
FIELD(CFRM_ITR0, WRITE_REG_ADDR_ERROR, 15, 1)
FIELD(CFRM_ITR0, WRITE_BLK_TYPE_ERROR, 13, 1)
FIELD(CFRM_ITR0, WRITE_FRAME_ADDR_ERROR, 12, 1)
FIELD(CFRM_ITR0, MFW_OVERRUN_ERROR, 11, 1)
FIELD(CFRM_ITR0, FAR_FIFO_UNDERFLOW, 10, 1)
FIELD(CFRM_ITR0, FAR_FIFO_OVERFLOW, 9, 1)
FIELD(CFRM_ITR0, PER_FRAME_SEQ_ERROR, 8, 1)
FIELD(CFRM_ITR0, CRC_ERROR, 7, 1)
FIELD(CFRM_ITR0, WRITE_OVERRUN_ERROR, 6, 1)
FIELD(CFRM_ITR0, READ_OVERRUN_ERROR, 5, 1)
FIELD(CFRM_ITR0, CMD_INTERRUPT_ERROR, 4, 1)
FIELD(CFRM_ITR0, WRITE_INTERRUPT_ERROR, 3, 1)
FIELD(CFRM_ITR0, READ_INTERRUPT_ERROR, 2, 1)
FIELD(CFRM_ITR0, SEU_CRC_ERROR, 1, 1)
FIELD(CFRM_ITR0, SEU_ECC_ERROR, 0, 1)
REG32(CFRM_ITR1, 0x194)
REG32(CFRM_ITR2, 0x198)
REG32(CFRM_ITR3, 0x19c)
REG32(SEU_SYNDRM00, 0x1a0)
REG32(SEU_SYNDRM01, 0x1a4)
REG32(SEU_SYNDRM02, 0x1a8)
REG32(SEU_SYNDRM03, 0x1ac)
REG32(SEU_SYNDRM10, 0x1b0)
REG32(SEU_SYNDRM11, 0x1b4)
REG32(SEU_SYNDRM12, 0x1b8)
REG32(SEU_SYNDRM13, 0x1bc)
REG32(SEU_SYNDRM20, 0x1c0)
REG32(SEU_SYNDRM21, 0x1c4)
REG32(SEU_SYNDRM22, 0x1c8)
REG32(SEU_SYNDRM23, 0x1cc)
REG32(SEU_SYNDRM30, 0x1d0)
REG32(SEU_SYNDRM31, 0x1d4)
REG32(SEU_SYNDRM32, 0x1d8)
REG32(SEU_SYNDRM33, 0x1dc)
REG32(SEU_VIRTUAL_SYNDRM0, 0x1e0)
REG32(SEU_VIRTUAL_SYNDRM1, 0x1e4)
REG32(SEU_VIRTUAL_SYNDRM2, 0x1e8)
REG32(SEU_VIRTUAL_SYNDRM3, 0x1ec)
REG32(SEU_CRC0, 0x1f0)
REG32(SEU_CRC1, 0x1f4)
REG32(SEU_CRC2, 0x1f8)
REG32(SEU_CRC3, 0x1fc)
REG32(CFRAME_FAR_BOT0, 0x200)
REG32(CFRAME_FAR_BOT1, 0x204)
REG32(CFRAME_FAR_BOT2, 0x208)
REG32(CFRAME_FAR_BOT3, 0x20c)
REG32(CFRAME_FAR_TOP0, 0x210)
REG32(CFRAME_FAR_TOP1, 0x214)
REG32(CFRAME_FAR_TOP2, 0x218)
REG32(CFRAME_FAR_TOP3, 0x21c)
REG32(LAST_FRAME_BOT0, 0x220)
FIELD(LAST_FRAME_BOT0, BLOCKTYPE1_LAST_FRAME_LSB, 20, 12)
FIELD(LAST_FRAME_BOT0, BLOCKTYPE0_LAST_FRAME, 0, 20)
REG32(LAST_FRAME_BOT1, 0x224)
FIELD(LAST_FRAME_BOT1, BLOCKTYPE3_LAST_FRAME_LSB, 28, 4)
FIELD(LAST_FRAME_BOT1, BLOCKTYPE2_LAST_FRAME, 8, 20)
FIELD(LAST_FRAME_BOT1, BLOCKTYPE1_LAST_FRAME_MSB, 0, 8)
REG32(LAST_FRAME_BOT2, 0x228)
FIELD(LAST_FRAME_BOT2, BLOCKTYPE3_LAST_FRAME_MSB, 0, 16)
REG32(LAST_FRAME_BOT3, 0x22c)
REG32(LAST_FRAME_TOP0, 0x230)
FIELD(LAST_FRAME_TOP0, BLOCKTYPE5_LAST_FRAME_LSB, 20, 12)
FIELD(LAST_FRAME_TOP0, BLOCKTYPE4_LAST_FRAME, 0, 20)
REG32(LAST_FRAME_TOP1, 0x234)
FIELD(LAST_FRAME_TOP1, BLOCKTYPE6_LAST_FRAME, 8, 20)
FIELD(LAST_FRAME_TOP1, BLOCKTYPE5_LAST_FRAME_MSB, 0, 8)
REG32(LAST_FRAME_TOP2, 0x238)
REG32(LAST_FRAME_TOP3, 0x23c)
#define CFRAME_REG_R_MAX (R_LAST_FRAME_TOP3 + 1)
#define FRAME_NUM_QWORDS 25
#define FRAME_NUM_WORDS (FRAME_NUM_QWORDS * 4) /* 25 * 128 bits */
typedef struct XlnxCFrame {
uint32_t data[FRAME_NUM_WORDS];
} XlnxCFrame;
struct XlnxVersalCFrameReg {
SysBusDevice parent_obj;
MemoryRegion iomem;
MemoryRegion iomem_fdri;
qemu_irq irq_cfrm_imr;
/* 128-bit wfifo. */
uint32_t wfifo[WFIFO_SZ];
uint32_t regs[CFRAME_REG_R_MAX];
RegisterInfo regs_info[CFRAME_REG_R_MAX];
bool rowon;
bool wcfg;
bool rcfg;
GTree *cframes;
Fifo32 new_f_data;
struct {
XlnxCfiIf *cfu_fdro;
uint32_t blktype_num_frames[7];
} cfg;
bool row_configured;
};
struct XlnxVersalCFrameBcastReg {
SysBusDevice parent_obj;
MemoryRegion iomem_reg;
MemoryRegion iomem_fdri;
/* 128-bit wfifo. */
uint32_t wfifo[WFIFO_SZ];
struct {
XlnxCfiIf *cframe[15];
} cfg;
};
#endif
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