21dda465fc
* Run docker probe only if docker or podman are available
The docker probe uses "sudo -n" which can cause an e-mail with a security warning
each time when configure is run. Therefore run docker probe only if either docker
or podman are available.
That avoids the problematic "sudo -n" on build environments which have neither
docker nor podman installed.
Fixes: c4575b59155e2e00 ("configure: store container engine in config-host.mak")
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20221030083510.310584-1-sw@weilnetz.de>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20221117172532.538149-2-alex.bennee@linaro.org>
* tests/avocado/machine_aspeed.py: Reduce noise on the console for SDK tests
The Aspeed SDK images are based on OpenBMC which starts a lot of
services. The output noise on the console can break from time to time
the test waiting for the logging prompt.
Change the U-Boot bootargs variable to add "quiet" to the kernel
command line and reduce the output volume. This also drops the test on
the CPU id which was nice to have but not essential.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20221104075347.370503-1-clg@kaod.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20221117172532.538149-3-alex.bennee@linaro.org>
* tests/docker: allow user to override check target
This is useful when trying to bisect a particular failing test behind
a docker run. For example:
make docker-test-clang@fedora \
TARGET_LIST=arm-softmmu \
TEST_COMMAND="meson test qtest-arm/qos-test" \
J=9 V=1
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221117172532.538149-4-alex.bennee@linaro.org>
* docs/devel: add a maintainers section to development process
We don't currently have a clear place in the documentation to describe
the roles and responsibilities of a maintainer. Lets create one so we
can. I've moved a few small bits out of other files to try and keep
everything in one place.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221117172532.538149-5-alex.bennee@linaro.org>
* docs/devel: make language a little less code centric
We welcome all sorts of patches.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221117172532.538149-6-alex.bennee@linaro.org>
* docs/devel: simplify the minimal checklist
The bullet points are quite long and contain process tips. Move those
bits of the bullet to the relevant sections and link to them. Use a
table for nicer formatting of the checklist.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221117172532.538149-7-alex.bennee@linaro.org>
* docs/devel: try and improve the language around patch review
It is important that contributors take the review process seriously
and we collaborate in a respectful way while avoiding personal
attacks. Try and make this clear in the language.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221117172532.538149-8-alex.bennee@linaro.org>
* tests/avocado: Raise timeout for boot_linux.py:BootLinuxPPC64.test_pseries_tcg
On my machine, a debug build of QEMU takes about 260 seconds to
complete this test, so with the current timeout value of 180 seconds
it always times out. Double the timeout value to 360 so the test
definitely has enough time to complete.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20221110142901.3832318-1-peter.maydell@linaro.org>
Message-Id: <20221117172532.538149-9-alex.bennee@linaro.org>
* tests/avocado: introduce alpine virt test for CI
The boot_linux tests download and run a full cloud image boot and
start a full distro. While the ability to test the full boot chain is
worthwhile it is perhaps a little too heavy weight and causes issues
in CI. Fix this by introducing a new alpine linux ISO boot in
machine_aarch64_virt.
This boots a fully loaded -cpu max with all the bells and whistles in
31s on my machine. A full debug build takes around 180s on my machine
so we set a more generous timeout to cover that.
We don't add a test for lesser GIC versions although there is some
coverage for that already in the boot_xen.py tests. If we want to
introduce more comprehensive testing we can do it with a custom kernel
and initrd rather than a full distro boot.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221117172532.538149-10-alex.bennee@linaro.org>
* tests/avocado: skip aarch64 cloud TCG tests in CI
We now have a much lighter weight test in machine_aarch64_virt which
tests the full boot chain in less time. Rename the tests while we are
at it to make it clear it is a Fedora cloud image.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221117172532.538149-11-alex.bennee@linaro.org>
* gitlab: integrate coverage report
This should hopefully give is nice coverage information about what our
tests (or at least the subset we are running) have hit. Ideally we
would want a way to trigger coverage on tests likely to be affected by
the current commit.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221117172532.538149-12-alex.bennee@linaro.org>
* vhost: mask VIRTIO_F_RING_RESET for vhost and vhost-user devices
Commit 69e1c14aa2 ("virtio: core: vq reset feature negotation support")
enabled VIRTIO_F_RING_RESET by default for all virtio devices.
This feature is not currently emulated by QEMU, so for vhost and
vhost-user devices we need to make sure it is supported by the offloaded
device emulation (in-kernel or in another process).
To do this we need to add VIRTIO_F_RING_RESET to the features bitmap
passed to vhost_get_features(). This way it will be masked if the device
does not support it.
This issue was initially discovered with vhost-vsock and vhost-user-vsock,
and then also tested with vhost-user-rng which confirmed the same issue.
They fail when sending features through VHOST_SET_FEATURES ioctl or
VHOST_USER_SET_FEATURES message, since VIRTIO_F_RING_RESET is negotiated
by the guest (Linux >= v6.0), but not supported by the device.
Fixes: 69e1c14aa2 ("virtio: core: vq reset feature negotation support")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1318
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20221121101101.29400-1-sgarzare@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Acked-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Acked-by: Jason Wang <jasowang@redhat.com>
* tests: acpi: whitelist DSDT before moving PRQx to _SB scope
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221121153613.3972225-2-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* acpi: x86: move RPQx field back to _SB scope
Commit 47a373faa6b2 (acpi: pc/q35: drop ad-hoc PCI-ISA bridge AML routines and let bus ennumeration generate AML)
moved ISA bridge AML generation to respective devices and was using
aml_alias() to provide PRQx fields in _SB. scope. However, it turned
out that SeaBIOS was not able to process Alias opcode when parsing DSDT,
resulting in lack of keyboard during boot (SeaBIOS console, grub, FreeDOS).
While fix for SeaBIOS is posted
https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/RGPL7HESH5U5JRLEO6FP77CZVHZK5J65/
fixed SeaBIOS might not make into QEMU-7.2 in time.
Hence this workaround that puts PRQx back into _SB scope
and gets rid of aliases in ISA bridge description, so
DSDT will be parsable by broken SeaBIOS.
That brings back hardcoded references to ISA bridge
PCI0.S08.P40C/PCI0.SF8.PIRQ
where middle part now is auto generated based on slot it's
plugged in, but it should be fine as bridge initialization
also hardcodes PCI address of the bridge so it can't ever
move. Once QEMU tree has fixed SeaBIOS blob, we should be able
to drop this part and revert back to alias based approach
Reported-by: Volker Rümelin <vr_qemu@t-online.de>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221121153613.3972225-3-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* tests: acpi: x86: update expected DSDT after moving PRQx fields in _SB scope
Expected DSDT changes,
pc:
- Field (P40C, ByteAcc, NoLock, Preserve)
+ Scope (\_SB)
{
- PRQ0, 8,
- PRQ1, 8,
- PRQ2, 8,
- PRQ3, 8
+ Field (PCI0.S08.P40C, ByteAcc, NoLock, Preserve)
+ {
+ PRQ0, 8,
+ PRQ1, 8,
+ PRQ2, 8,
+ PRQ3, 8
+ }
}
- Alias (PRQ0, \_SB.PRQ0)
- Alias (PRQ1, \_SB.PRQ1)
- Alias (PRQ2, \_SB.PRQ2)
- Alias (PRQ3, \_SB.PRQ3)
q35:
- Field (PIRQ, ByteAcc, NoLock, Preserve)
- {
- PRQA, 8,
- PRQB, 8,
- PRQC, 8,
- PRQD, 8,
- Offset (0x08),
- PRQE, 8,
- PRQF, 8,
- PRQG, 8,
- PRQH, 8
+ Scope (\_SB)
+ {
+ Field (PCI0.SF8.PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+ Offset (0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
}
- Alias (PRQA, \_SB.PRQA)
- Alias (PRQB, \_SB.PRQB)
- Alias (PRQC, \_SB.PRQC)
- Alias (PRQD, \_SB.PRQD)
- Alias (PRQE, \_SB.PRQE)
- Alias (PRQF, \_SB.PRQF)
- Alias (PRQG, \_SB.PRQG)
- Alias (PRQH, \_SB.PRQH)
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221121153613.3972225-4-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* MAINTAINERS: add mst to list of biosbits maintainers
Adding Michael's name to the list of bios bits maintainers so that all changes
and fixes into biosbits framework can go through his tree and he is notified.
Suggested-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Ani Sinha <ani@anisinha.ca>
Message-Id: <20221111151138.36988-1-ani@anisinha.ca>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* tests/avocado: configure acpi-bits to use avocado timeout
Instead of using a hardcoded timeout, just rely on Avocado's built-in
test case timeout. This helps avoid timeout issues on machines where 60
seconds is not sufficient.
Signed-off-by: John Snow <jsnow@redhat.com>
Message-Id: <20221115212759.3095751-1-jsnow@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
* acpi/tests/avocado/bits: keep the work directory when BITS_DEBUG is set in env
Debugging bits issue often involves running the QEMU command line manually
outside of the avocado environment with the generated ISO. Hence, its
inconvenient if the iso gets cleaned up after the test has finished. This change
makes sure that the work directory is kept after the test finishes if the test
is run with BITS_DEBUG=1 in the environment so that the iso is available for use
with the QEMU command line.
CC: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Ani Sinha <ani@anisinha.ca>
Message-Id: <20221117113630.543495-1-ani@anisinha.ca>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* virtio: disable error for out of spec queue-enable
Virtio 1.0 is pretty clear that features have to be
negotiated before enabling VQs. Unfortunately Seabios
ignored this ever since gaining 1.0 support (UEFI is ok).
Comment the error out for now, and add a TODO.
Fixes: 3c37f8b8d1 ("virtio: introduce virtio_queue_enable()")
Cc: "Kangjie Xu" <kangjie.xu@linux.alibaba.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221121200339.362452-1-mst@redhat.com>
* hw/loongarch: Add default stdout uart in fdt
Add "chosen" subnode into LoongArch fdt, and set it's
"stdout-path" prop to uart node.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221115114923.3372414-1-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
* hw/loongarch: Fix setprop_sized method in fdt rtc node.
Fix setprop_sized method in fdt rtc node.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221116040300.3459818-1-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
* hw/loongarch: Replace the value of uart info with macro
Using macro to replace the value of uart info such as addr, size
in acpi_build method.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221115115008.3372489-1-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
* target/arm: Don't do two-stage lookup if stage 2 is disabled
In get_phys_addr_with_struct(), we call get_phys_addr_twostage() if
the CPU supports EL2. However, we don't check here that stage 2 is
actually enabled. Instead we only check that inside
get_phys_addr_twostage() to skip stage 2 translation. This means
that even if stage 2 is disabled we still tell the stage 1 lookup to
do its page table walks via stage 2.
This works by luck for normal CPU accesses, but it breaks for debug
accesses, which are used by the disassembler and also by semihosting
file reads and writes, because the debug case takes a different code
path inside S1_ptw_translate().
This means that setups that use semihosting for file loads are broken
(a regression since 7.1, introduced in recent ptw refactoring), and
that sometimes disassembly in debug logs reports "unable to read
memory" rather than showing the guest insns.
Fix the bug by hoisting the "is stage 2 enabled?" check up to
get_phys_addr_with_struct(), so that we handle S2 disabled the same
way we do the "no EL2" case, with a simple single stage lookup.
Reported-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221121212404.1450382-1-peter.maydell@linaro.org
* target/arm: Use signed quantity to represent VMSAv8-64 translation level
The LPA2 extension implements 52-bit virtual addressing for 4k and 16k
translation granules, and for the former, this means an additional level
of translation is needed. This means we start counting at -1 instead of
0 when doing a walk, and so 'level' is now a signed quantity, and should
be typed as such. So turn it from uint32_t into int32_t.
This avoids a level of -1 getting misinterpreted as being >= 3, and
terminating a page table walk prematurely with a bogus output address.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Update VERSION for v7.2.0-rc2
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* tests/avocado: Update the URLs of the advent calendar images
The qemu-advent-calendar.org server will be decommissioned soon.
I've mirrored the images that we use for the QEMU CI to gitlab,
so update their URLs to point to the new location.
Message-Id: <20221121102436.78635-1-thuth@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/qtest: Decrease the amount of output from the qom-test
The logs in the gitlab-CI have a size constraint, and sometimes
we already hit this limit. The biggest part of the log then seems
to be filled by the qom-test, so we should decrease the size of
the output - which can be done easily by not printing the path
for each property, since the path has already been logged at the
beginning of each node that we handle here.
However, if we omit the path, we should make sure to not recurse
into child nodes in between, so that it is clear to which node
each property belongs. Thus store the children and links in a
temporary list and recurse only at the end of each node, when
all properties have already been printed.
Message-Id: <20221121194240.149268-1-thuth@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/avocado: use new rootfs for orangepi test
The old URL wasn't stable. I suspect the current URL will only be
stable for a few months so maybe we need another strategy for hosting
rootfs snapshots?
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20221118113309.1057790-1-alex.bennee@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
* Revert "usbredir: avoid queuing hello packet on snapshot restore"
Run state is also in RUN_STATE_PRELAUNCH while "-S" is used.
This reverts commit 0631d4b448454ae8a1ab091c447e3f71ab6e088a
Signed-off-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
The original commit broke the usage of usbredir with libvirt, which
starts every domain with "-S".
This workaround is no longer needed because the usbredir behavior
has been fixed in the meantime:
https://gitlab.freedesktop.org/spice/usbredir/-/merge_requests/61
Signed-off-by: Ján Tomko <jtomko@redhat.com>
Message-Id: <1689cec3eadcea87255e390cb236033aca72e168.1669193161.git.jtomko@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* gtk: disable GTK Clipboard with a new meson option
The GTK Clipboard implementation may cause guest hangs.
Therefore implement new configure switch: --enable-gtk-clipboard,
as a meson option disabled by default, which warns in the help
text about the experimental nature of the feature.
Regenerate the meson build options to include it.
The initialization of the clipboard is gtk.c, as well as the
compilation of gtk-clipboard.c are now conditional on this new
option to be set.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1150
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jim Fehlig <jfehlig@suse.com>
Message-Id: <20221121135538.14625-1-cfontana@suse.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* hw/usb/hcd-xhci.c: spelling: tranfer
Fixes: effaf5a240e03020f4ae953e10b764622c3e87cc
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20221105114851.306206-1-mjt@msgid.tls.msk.ru>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* ui/gtk: prevent ui lock up when dpy_gl_update called again before current draw event occurs
A warning, "qemu: warning: console: no gl-unblock within" followed by
guest scanout lockup can happen if dpy_gl_update is called in a row
and the second call is made before gd_draw_event scheduled by the first
call is taking place. This is because draw call returns without decrementing
gl_block ref count if the dmabuf was already submitted as shown below.
(gd_gl_area_draw/gd_egl_draw)
if (dmabuf) {
if (!dmabuf->draw_submitted) {
return;
} else {
dmabuf->draw_submitted = false;
}
}
So it should not schedule any redundant draw event in case draw_submitted is
already set in gd_egl_fluch/gd_gl_area_scanout_flush.
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Vivek Kasireddy <vivek.kasireddy@intel.com>
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221021192315.9110-1-dongwon.kim@intel.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* hw/usb/hcd-xhci: Reset the XHCIState with device_cold_reset()
Currently the hcd-xhci-pci and hcd-xhci-sysbus devices, which are
mostly wrappers around the TYPE_XHCI device, which is a direct
subclass of TYPE_DEVICE. Since TYPE_DEVICE devices are not on any
qbus and do not get automatically reset, the wrapper devices both
reset the TYPE_XHCI device in their own reset functions. However,
they do this using device_legacy_reset(), which will reset the device
itself but not any bus it has.
Switch to device_cold_reset(), which avoids using a deprecated
function and also propagates reset along any child buses.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20221014145423.2102706-1-peter.maydell@linaro.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* hw/audio/intel-hda: don't reset codecs twice
Currently the intel-hda device has a reset method which manually
resets all the codecs by calling device_legacy_reset() on them. This
means they get reset twice, once because child devices on a qbus get
reset before the parent device's reset method is called, and then
again because we're manually resetting them.
Drop the manual reset call, and ensure that codecs are still reset
when the guest does a reset via ICH6_GCTL_RESET by using
device_cold_reset() (which resets all the devices on the qbus as well
as the device itself) instead of a direct call to the reset function.
This is a slight ordering change because the (only) codec reset now
happens before the controller registers etc are reset, rather than
once before and then once after, but the codec reset function
hda_audio_reset() doesn't care.
This lets us drop a use of device_legacy_reset(), which is
deprecated.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221014142632.2092404-2-peter.maydell@linaro.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* hw/audio/intel-hda: Drop unnecessary prototype
The only use of intel_hda_reset() is after its definition, so we
don't need to separately declare its prototype at the top of the
file; drop the unnecessary line.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221014142632.2092404-3-peter.maydell@linaro.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* add syx snapshot extras
* it compiles!
* virtiofsd: Add `sigreturn` to the seccomp whitelist
The virtiofsd currently crashes on s390x. This is because of a
`sigreturn` system call. See audit log below:
type=SECCOMP msg=audit(1669382477.611:459): auid=4294967295 uid=0 gid=0 ses=4294967295 subj=system_u:system_r:virtd_t:s0-s0:c0.c1023 pid=6649 comm="virtiofsd" exe="/usr/libexec/virtiofsd" sig=31 arch=80000016 syscall=119 compat=0 ip=0x3fff15f748a code=0x80000000AUID="unset" UID="root" GID="root" ARCH=s390x SYSCALL=sigreturn
Signed-off-by: Marc Hartmayer <mhartmay@linux.ibm.com>
Reviewed-by: German Maglione <gmaglione@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221125143946.27717-1-mhartmay@linux.ibm.com>
* libvhost-user: Fix wrong type of argument to formatting function (reported by LGTM)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20220422070144.1043697-2-sw@weilnetz.de>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221126152507.283271-2-sw@weilnetz.de>
* libvhost-user: Fix format strings
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220422070144.1043697-3-sw@weilnetz.de>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221126152507.283271-3-sw@weilnetz.de>
* libvhost-user: Fix two more format strings
This fix is required for 32 bit hosts. The bug was detected by CI
for arm-linux, but is also relevant for i386-linux.
Reported-by: Stefan Hajnoczi <stefanha@gmail.com>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221126152507.283271-4-sw@weilnetz.de>
* libvhost-user: Add format attribute to local function vu_panic
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220422070144.1043697-4-sw@weilnetz.de>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221126152507.283271-5-sw@weilnetz.de>
* MAINTAINERS: Add subprojects/libvhost-user to section "vhost"
Signed-off-by: Stefan Weil <sw@weilnetz.de>
[Michael agreed to act as maintainer for libvhost-user via email in
https://lore.kernel.org/qemu-devel/20221123015218-mutt-send-email-mst@kernel.org/.
--Stefan]
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221126152507.283271-6-sw@weilnetz.de>
* Add G_GNUC_PRINTF to function qemu_set_info_str and fix related issues
With the G_GNUC_PRINTF function attribute the compiler detects
two potential insecure format strings:
../../../net/stream.c:248:31: warning: format string is not a string literal (potentially insecure) [-Wformat-security]
qemu_set_info_str(&s->nc, uri);
^~~
../../../net/stream.c:322:31: warning: format string is not a string literal (potentially insecure) [-Wformat-security]
qemu_set_info_str(&s->nc, uri);
^~~
There are also two other warnings:
../../../net/socket.c:182:35: warning: zero-length gnu_printf format string [-Wformat-zero-length]
182 | qemu_set_info_str(&s->nc, "");
| ^~
../../../net/stream.c:170:35: warning: zero-length gnu_printf format string [-Wformat-zero-length]
170 | qemu_set_info_str(&s->nc, "");
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221126152507.283271-7-sw@weilnetz.de>
* del ramfile
* update seabios source from 1.16.0 to 1.16.1
git shortlog rel-1.16.0..rel-1.16.1
===================================
Gerd Hoffmann (3):
malloc: use variable for ZoneHigh size
malloc: use large ZoneHigh when there is enough memory
virtio-blk: use larger default request size
Igor Mammedov (1):
acpi: parse Alias object
Volker Rümelin (2):
pci: refactor the pci_config_*() functions
reset: force standard PCI configuration access
Xiaofei Lee (1):
virtio-blk: Fix incorrect type conversion in virtio_blk_op()
Xuan Zhuo (2):
virtio-mmio: read/write the hi 32 features for mmio
virtio: finalize features before using device
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* update seabios binaries to 1.16.1
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* fix for non i386 archs
* replay: Fix declaration of replay_read_next_clock
Fixes the build with gcc 13:
replay/replay-time.c:34:6: error: conflicting types for \
'replay_read_next_clock' due to enum/integer mismatch; \
have 'void(ReplayClockKind)' [-Werror=enum-int-mismatch]
34 | void replay_read_next_clock(ReplayClockKind kind)
| ^~~~~~~~~~~~~~~~~~~~~~
In file included from ../qemu/replay/replay-time.c:14:
replay/replay-internal.h:139:6: note: previous declaration of \
'replay_read_next_clock' with type 'void(unsigned int)'
139 | void replay_read_next_clock(unsigned int kind);
| ^~~~~~~~~~~~~~~~~~~~~~
Fixes: 8eda206e090 ("replay: recording and replaying clock ticks")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221129010547.284051-1-richard.henderson@linaro.org>
* hw/display/qxl: Have qxl_log_command Return early if no log_cmd handler
Only 3 command types are logged: no need to call qxl_phys2virt()
for the other types. Using different cases will help to pass
different structure sizes to qxl_phys2virt() in a pair of commits.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221128202741.4945-2-philmd@linaro.org>
* hw/display/qxl: Document qxl_phys2virt()
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221128202741.4945-3-philmd@linaro.org>
* hw/display/qxl: Pass requested buffer size to qxl_phys2virt()
Currently qxl_phys2virt() doesn't check for buffer overrun.
In order to do so in the next commit, pass the buffer size
as argument.
For QXLCursor in qxl_render_cursor() -> qxl_cursor() we
verify the size of the chunked data ahead, checking we can
access 'sizeof(QXLCursor) + chunk->data_size' bytes.
Since in the SPICE_CURSOR_TYPE_MONO case the cursor is
assumed to fit in one chunk, no change are required.
In SPICE_CURSOR_TYPE_ALPHA the ahead read is handled in
qxl_unpack_chunks().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221128202741.4945-4-philmd@linaro.org>
* hw/display/qxl: Avoid buffer overrun in qxl_phys2virt (CVE-2022-4144)
Have qxl_get_check_slot_offset() return false if the requested
buffer size does not fit within the slot memory region.
Similarly qxl_phys2virt() now returns NULL in such case, and
qxl_dirty_one_surface() aborts.
This avoids buffer overrun in the host pointer returned by
memory_region_get_ram_ptr().
Fixes: CVE-2022-4144 (out-of-bounds read)
Reported-by: Wenxu Yin (@awxylitol)
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1336
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221128202741.4945-5-philmd@linaro.org>
* hw/display/qxl: Assert memory slot fits in preallocated MemoryRegion
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221128202741.4945-6-philmd@linaro.org>
* block-backend: avoid bdrv_unregister_buf() NULL pointer deref
bdrv_*() APIs expect a valid BlockDriverState. Calling them with bs=NULL
leads to undefined behavior.
Jonathan Cameron reported this following NULL pointer dereference when a
VM with a virtio-blk device and a memory-backend-file object is
terminated:
1. qemu_cleanup() closes all drives, setting blk->root to NULL
2. qemu_cleanup() calls user_creatable_cleanup(), which results in a RAM
block notifier callback because the memory-backend-file is destroyed.
3. blk_unregister_buf() is called by virtio-blk's BlockRamRegistrar
notifier callback and undefined behavior occurs.
Fixes: baf422684d73 ("virtio-blk: use BDRV_REQ_REGISTERED_BUF optimization hint")
Co-authored-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221121211923.1993171-1-stefanha@redhat.com>
* target/arm: Set TCGCPUOps.restore_state_to_opc for v7m
This setting got missed, breaking v7m.
Fixes: 56c6c98df85c ("target/arm: Convert to tcg_ops restore_state_to_opc")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1347
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Evgeny Ermakov <evgeny.v.ermakov@gmail.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221129204146.550394-1-richard.henderson@linaro.org>
* Update VERSION for v7.2.0-rc3
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* hooks are now post mem access
* tests/qtests: override "force-legacy" for gpio virtio-mmio tests
The GPIO device is a VIRTIO_F_VERSION_1 devices but running with a
legacy MMIO interface we miss out that feature bit causing confusion.
For the GPIO test force the mmio bus to support non-legacy so we can
properly test it.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1333
Message-Id: <20221130112439.2527228-2-alex.bennee@linaro.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* vhost: enable vrings in vhost_dev_start() for vhost-user devices
Commit 02b61f38d3 ("hw/virtio: incorporate backend features in features")
properly negotiates VHOST_USER_F_PROTOCOL_FEATURES with the vhost-user
backend, but we forgot to enable vrings as specified in
docs/interop/vhost-user.rst:
If ``VHOST_USER_F_PROTOCOL_FEATURES`` has not been negotiated, the
ring starts directly in the enabled state.
If ``VHOST_USER_F_PROTOCOL_FEATURES`` has been negotiated, the ring is
initialized in a disabled state and is enabled by
``VHOST_USER_SET_VRING_ENABLE`` with parameter 1.
Some vhost-user front-ends already did this by calling
vhost_ops.vhost_set_vring_enable() directly:
- backends/cryptodev-vhost.c
- hw/net/virtio-net.c
- hw/virtio/vhost-user-gpio.c
But most didn't do that, so we would leave the vrings disabled and some
backends would not work. We observed this issue with the rust version of
virtiofsd [1], which uses the event loop [2] provided by the
vhost-user-backend crate where requests are not processed if vring is
not enabled.
Let's fix this issue by enabling the vrings in vhost_dev_start() for
vhost-user front-ends that don't already do this directly. Same thing
also in vhost_dev_stop() where we disable vrings.
[1] https://gitlab.com/virtio-fs/virtiofsd
[2] https://github.com/rust-vmm/vhost/blob/240fc2966/crates/vhost-user-backend/src/event_loop.rs#L217
Fixes: 02b61f38d3 ("hw/virtio: incorporate backend features in features")
Reported-by: German Maglione <gmaglione@redhat.com>
Tested-by: German Maglione <gmaglione@redhat.com>
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com>
Acked-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20221123131630.52020-1-sgarzare@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221130112439.2527228-3-alex.bennee@linaro.org>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/virtio: add started_vu status field to vhost-user-gpio
As per the fix to vhost-user-blk in f5b22d06fb (vhost: recheck dev
state in the vhost_migration_log routine) we really should track the
connection and starting separately.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221130112439.2527228-4-alex.bennee@linaro.org>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/virtio: generalise CHR_EVENT_CLOSED handling
..and use for both virtio-user-blk and virtio-user-gpio. This avoids
the circular close by deferring shutdown due to disconnection until a
later point. virtio-user-blk already had this mechanism in place so
generalise it as a vhost-user helper function and use for both blk and
gpio devices.
While we are at it we also fix up vhost-user-gpio to re-establish the
event handler after close down so we can reconnect later.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Message-Id: <20221130112439.2527228-5-alex.bennee@linaro.org>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* include/hw: VM state takes precedence in virtio_device_should_start
The VM status should always preempt the device status for these
checks. This ensures the device is in the correct state when we
suspend the VM prior to migrations. This restores the checks to the
order they where in before the refactoring moved things around.
While we are at it lets improve our documentation of the various
fields involved and document the two functions.
Fixes: 9f6bcfd99f (hw/virtio: move vm_running check to virtio_device_started)
Fixes: 259d69c00b (hw/virtio: introduce virtio_device_should_start)
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Christian Borntraeger <borntraeger@linux.ibm.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221130112439.2527228-6-alex.bennee@linaro.org>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/nvme: fix aio cancel in format
There are several bugs in the async cancel code for the Format command.
Firstly, cancelling a format operation neglects to set iocb->ret as well
as clearing the iocb->aiocb after cancelling the underlying aiocb which
causes the aio callback to ignore the cancellation. Trivial fix.
Secondly, and worse, because the request is queued up for posting to the
CQ in a bottom half, if the cancellation is due to the submission queue
being deleted (which calls blk_aio_cancel), the req structure is
deallocated in nvme_del_sq prior to the bottom half being schedulued.
Fix this by simply removing the bottom half, there is no reason to defer
it anyway.
Fixes: 3bcf26d3d619 ("hw/nvme: reimplement format nvm to allow cancellation")
Reported-by: Jonathan Derrick <jonathan.derrick@linux.dev>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
* hw/nvme: fix aio cancel in flush
Make sure that iocb->aiocb is NULL'ed when cancelling.
Fix a potential use-after-free by removing the bottom half and enqueuing
the completion directly.
Fixes: 38f4ac65ac88 ("hw/nvme: reimplement flush to allow cancellation")
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
* hw/nvme: fix aio cancel in zone reset
If the zone reset operation is cancelled but the block unmap operation
completes normally, the callback will continue resetting the next zone
since it neglects to check iocb->ret which will have been set to
-ECANCELED. Make sure that this is checked and bail out if an error is
present.
Secondly, fix a potential use-after-free by removing the bottom half and
enqueuing the completion directly.
Fixes: 63d96e4ffd71 ("hw/nvme: reimplement zone reset to allow cancellation")
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
* hw/nvme: fix aio cancel in dsm
When the DSM operation is cancelled asynchronously, we set iocb->ret to
-ECANCELED. However, the callback function only checks the return value
of the completed aio, which may have completed succesfully prior to the
cancellation and thus the callback ends up continuing the dsm operation
instead of bailing out. Fix this.
Secondly, fix a potential use-after-free by removing the bottom half and
enqueuing the completion directly.
Fixes: d7d1474fd85d ("hw/nvme: reimplement dsm to allow cancellation")
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
* hw/nvme: remove copy bh scheduling
Fix a potential use-after-free by removing the bottom half and enqueuing
the completion directly.
Fixes: 796d20681d9b ("hw/nvme: reimplement the copy command to allow aio cancellation")
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
* target/i386: allow MMX instructions with CR4.OSFXSR=0
MMX state is saved/restored by FSAVE/FRSTOR so the instructions are
not illegal opcodes even if CR4.OSFXSR=0. Make sure that validate_vex
takes into account the prefix and only checks HF_OSFXSR_MASK in the
presence of an SSE instruction.
Fixes: 20581aadec5e ("target/i386: validate VEX prefixes via the instructions' exception classes", 2022-10-18)
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1350
Reported-by: Helge Konetzka (@hejko on gitlab.com)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/i386: Always completely initialize TranslateFault
In get_physical_address, the canonical address check failed to
set TranslateFault.stage2, which resulted in an uninitialized
read from the struct when reporting the fault in x86_cpu_tlb_fill.
Adjust all error paths to use structure assignment so that the
entire struct is always initialized.
Reported-by: Daniel Hoffman <dhoff749@gmail.com>
Fixes: 9bbcf372193a ("target/i386: Reorg GET_HPHYS")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221201074522.178498-1-richard.henderson@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1324
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/loongarch/virt: Add cfi01 pflash device
Add cfi01 pflash device for LoongArch virt machine
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221130100647.398565-1-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
* Sync pc on breakpoints
* tests/qtest/migration-test: Fix unlink error and memory leaks
When running the migration test compiled with Clang from Fedora 37
and sanitizers enabled, there is an error complaining about unlink():
../tests/qtest/migration-test.c:1072:12: runtime error: null pointer
passed as argument 1, which is declared to never be null
/usr/include/unistd.h:858:48: note: nonnull attribute specified here
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior
../tests/qtest/migration-test.c:1072:12 in
(test program exited with status code 1)
TAP parsing error: Too few tests run (expected 33, got 20)
The data->clientcert and data->clientkey pointers can indeed be unset
in some tests, so we have to check them before calling unlink() with
those.
While we're at it, I also noticed that the code is only freeing
some but not all of the allocated strings in this function, and
indeed, valgrind is also complaining about memory leaks here.
So let's call g_free() on all allocated strings to avoid leaking
memory here.
Message-Id: <20221125083054.117504-1-thuth@redhat.com>
Tested-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
* target/s390x/tcg: Fix and improve the SACF instruction
The SET ADDRESS SPACE CONTROL FAST instruction is not privileged, it can be
used from problem space, too. Just the switching to the home address space
is privileged and should still generate a privilege exception. This bug is
e.g. causing programs like Java that use the "getcpu" vdso kernel function
to crash (see https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=990417#26 ).
While we're at it, also check if DAT is not enabled. In that case the
instruction is supposed to generate a special operation exception.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/655
Message-Id: <20221201184443.136355-1-thuth@redhat.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/display/next-fb: Fix comment typo
Signed-off-by: Evgeny Ermakov <evgeny.v.ermakov@gmail.com>
Message-Id: <20221125160849.23711-1-evgeny.v.ermakov@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
* fix dev snapshots
* working syx snaps
* Revert "hw/loongarch/virt: Add cfi01 pflash device"
This reverts commit 14dccc8ea6ece7ee63273144fb55e4770a05e0fd.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221205113007.683505-1-gaosong@loongson.cn>
* Update VERSION for v7.2.0-rc4
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Ani Sinha <ani@anisinha.ca>
Signed-off-by: John Snow <jsnow@redhat.com>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Ján Tomko <jtomko@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Signed-off-by: Marc Hartmayer <mhartmay@linux.ibm.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Evgeny Ermakov <evgeny.v.ermakov@gmail.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Co-authored-by: Stefan Weil <sw@weilnetz.de>
Co-authored-by: Cédric Le Goater <clg@kaod.org>
Co-authored-by: Alex Bennée <alex.bennee@linaro.org>
Co-authored-by: Peter Maydell <peter.maydell@linaro.org>
Co-authored-by: Stefano Garzarella <sgarzare@redhat.com>
Co-authored-by: Igor Mammedov <imammedo@redhat.com>
Co-authored-by: Ani Sinha <ani@anisinha.ca>
Co-authored-by: John Snow <jsnow@redhat.com>
Co-authored-by: Michael S. Tsirkin <mst@redhat.com>
Co-authored-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Co-authored-by: Stefan Hajnoczi <stefanha@redhat.com>
Co-authored-by: Ard Biesheuvel <ardb@kernel.org>
Co-authored-by: Thomas Huth <thuth@redhat.com>
Co-authored-by: Joelle van Dyne <j@getutm.app>
Co-authored-by: Claudio Fontana <cfontana@suse.de>
Co-authored-by: Michael Tokarev <mjt@tls.msk.ru>
Co-authored-by: Dongwon Kim <dongwon.kim@intel.com>
Co-authored-by: Marc Hartmayer <mhartmay@linux.ibm.com>
Co-authored-by: Stefan Weil via <qemu-devel@nongnu.org>
Co-authored-by: Gerd Hoffmann <kraxel@redhat.com>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Co-authored-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Co-authored-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Co-authored-by: Evgeny Ermakov <evgeny.v.ermakov@gmail.com>
Co-authored-by: Klaus Jensen <k.jensen@samsung.com>
Co-authored-by: Paolo Bonzini <pbonzini@redhat.com>
Co-authored-by: Song Gao <gaosong@loongson.cn>
1845 lines
70 KiB
C++
1845 lines
70 KiB
C++
/*
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* New-style decoder for i386 instructions
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*
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* Copyright (c) 2022 Red Hat, Inc.
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*
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* Author: Paolo Bonzini <pbonzini@redhat.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* The decoder is mostly based on tables copied from the Intel SDM. As
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* a result, most operand load and writeback is done entirely in common
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* table-driven code using the same operand type (X86_TYPE_*) and
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* size (X86_SIZE_*) codes used in the manual.
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*
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* The main difference is that the V, U and W types are extended to
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* cover MMX as well; if an instruction is like
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*
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* por Pq, Qq
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* 66 por Vx, Hx, Wx
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*
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* only the second row is included and the instruction is marked as a
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* valid MMX instruction. The MMX flag directs the decoder to rewrite
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* the V/U/H/W types to P/N/P/Q if there is no prefix, as well as changing
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* "x" to "q" if there is no prefix.
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*
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* In addition, the ss/ps/sd/pd types are sometimes mushed together as "x"
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* if the difference is expressed via prefixes. Individual instructions
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* are separated by prefix in the generator functions.
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*
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* There are a couple cases in which instructions (e.g. MOVD) write the
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* whole XMM or MM register but are established incorrectly in the manual
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* as "d" or "q". These have to be fixed for the decoder to work correctly.
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*/
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#define X86_OP_NONE { 0 },
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#define X86_OP_GROUP3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \
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.decode = glue(decode_, op), \
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.op0 = glue(X86_TYPE_, op0_), \
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.s0 = glue(X86_SIZE_, s0_), \
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.op1 = glue(X86_TYPE_, op1_), \
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.s1 = glue(X86_SIZE_, s1_), \
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.op2 = glue(X86_TYPE_, op2_), \
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.s2 = glue(X86_SIZE_, s2_), \
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.is_decode = true, \
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## __VA_ARGS__ \
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}
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#define X86_OP_GROUP2(op, op0, s0, op1, s1, ...) \
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X86_OP_GROUP3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__)
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#define X86_OP_GROUP0(op, ...) \
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X86_OP_GROUP3(op, None, None, None, None, None, None, ## __VA_ARGS__)
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#define X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) { \
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.gen = glue(gen_, op), \
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.op0 = glue(X86_TYPE_, op0_), \
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.s0 = glue(X86_SIZE_, s0_), \
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.op1 = glue(X86_TYPE_, op1_), \
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.s1 = glue(X86_SIZE_, s1_), \
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.op2 = glue(X86_TYPE_, op2_), \
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.s2 = glue(X86_SIZE_, s2_), \
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## __VA_ARGS__ \
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}
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#define X86_OP_ENTRY4(op, op0_, s0_, op1_, s1_, op2_, s2_, ...) \
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X86_OP_ENTRY3(op, op0_, s0_, op1_, s1_, op2_, s2_, \
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.op3 = X86_TYPE_I, .s3 = X86_SIZE_b, \
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## __VA_ARGS__)
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#define X86_OP_ENTRY2(op, op0, s0, op1, s1, ...) \
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X86_OP_ENTRY3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__)
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#define X86_OP_ENTRYw(op, op0, s0, ...) \
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X86_OP_ENTRY3(op, op0, s0, None, None, None, None, ## __VA_ARGS__)
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#define X86_OP_ENTRYr(op, op0, s0, ...) \
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X86_OP_ENTRY3(op, None, None, None, None, op0, s0, ## __VA_ARGS__)
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#define X86_OP_ENTRY0(op, ...) \
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X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__)
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#define cpuid(feat) .cpuid = X86_FEAT_##feat,
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#define i64 .special = X86_SPECIAL_i64,
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#define o64 .special = X86_SPECIAL_o64,
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#define xchg .special = X86_SPECIAL_Locked,
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#define mmx .special = X86_SPECIAL_MMX,
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#define zext0 .special = X86_SPECIAL_ZExtOp0,
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#define zext2 .special = X86_SPECIAL_ZExtOp2,
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#define avx_movx .special = X86_SPECIAL_AVXExtMov,
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#define vex1 .vex_class = 1,
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#define vex1_rep3 .vex_class = 1, .vex_special = X86_VEX_REPScalar,
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#define vex2 .vex_class = 2,
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#define vex2_rep3 .vex_class = 2, .vex_special = X86_VEX_REPScalar,
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#define vex3 .vex_class = 3,
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#define vex4 .vex_class = 4,
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#define vex4_unal .vex_class = 4, .vex_special = X86_VEX_SSEUnaligned,
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#define vex5 .vex_class = 5,
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#define vex6 .vex_class = 6,
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#define vex7 .vex_class = 7,
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#define vex8 .vex_class = 8,
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#define vex11 .vex_class = 11,
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#define vex12 .vex_class = 12,
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#define vex13 .vex_class = 13,
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#define avx2_256 .vex_special = X86_VEX_AVX2_256,
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#define P_00 1
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#define P_66 (1 << PREFIX_DATA)
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#define P_F3 (1 << PREFIX_REPZ)
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#define P_F2 (1 << PREFIX_REPNZ)
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#define p_00 .valid_prefix = P_00,
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#define p_66 .valid_prefix = P_66,
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#define p_f3 .valid_prefix = P_F3,
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#define p_f2 .valid_prefix = P_F2,
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#define p_00_66 .valid_prefix = P_00 | P_66,
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#define p_00_f3 .valid_prefix = P_00 | P_F3,
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#define p_66_f2 .valid_prefix = P_66 | P_F2,
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#define p_00_66_f3 .valid_prefix = P_00 | P_66 | P_F3,
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#define p_66_f3_f2 .valid_prefix = P_66 | P_F3 | P_F2,
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#define p_00_66_f3_f2 .valid_prefix = P_00 | P_66 | P_F3 | P_F2,
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static uint8_t get_modrm(DisasContext *s, CPUX86State *env)
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{
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if (!s->has_modrm) {
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s->modrm = x86_ldub_code(env, s);
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s->has_modrm = true;
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}
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return s->modrm;
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}
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static inline const X86OpEntry *decode_by_prefix(DisasContext *s, const X86OpEntry entries[4])
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{
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if (s->prefix & PREFIX_REPNZ) {
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return &entries[3];
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} else if (s->prefix & PREFIX_REPZ) {
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return &entries[2];
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} else if (s->prefix & PREFIX_DATA) {
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return &entries[1];
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} else {
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return &entries[0];
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}
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}
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static void decode_group15(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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/* only includes ldmxcsr and stmxcsr, because they have AVX variants. */
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static const X86OpEntry group15_reg[8] = {
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};
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static const X86OpEntry group15_mem[8] = {
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[2] = X86_OP_ENTRYr(LDMXCSR, E,d, vex5),
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[3] = X86_OP_ENTRYw(STMXCSR, E,d, vex5),
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};
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uint8_t modrm = get_modrm(s, env);
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if ((modrm >> 6) == 3) {
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*entry = group15_reg[(modrm >> 3) & 7];
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} else {
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*entry = group15_mem[(modrm >> 3) & 7];
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}
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}
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static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86GenFunc group17_gen[8] = {
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NULL, gen_BLSR, gen_BLSMSK, gen_BLSI,
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};
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int op = (get_modrm(s, env) >> 3) & 7;
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entry->gen = group17_gen[op];
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}
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static void decode_group12(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry opcodes_group12[8] = {
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{},
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{},
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X86_OP_ENTRY3(PSRLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
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{},
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X86_OP_ENTRY3(PSRAW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
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{},
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X86_OP_ENTRY3(PSLLW_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
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{},
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};
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int op = (get_modrm(s, env) >> 3) & 7;
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*entry = opcodes_group12[op];
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}
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static void decode_group13(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry opcodes_group13[8] = {
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{},
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{},
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X86_OP_ENTRY3(PSRLD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
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{},
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X86_OP_ENTRY3(PSRAD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
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{},
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X86_OP_ENTRY3(PSLLD_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
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{},
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};
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int op = (get_modrm(s, env) >> 3) & 7;
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*entry = opcodes_group13[op];
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}
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static void decode_group14(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry opcodes_group14[8] = {
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/* grp14 */
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{},
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{},
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X86_OP_ENTRY3(PSRLQ_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
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X86_OP_ENTRY3(PSRLDQ_i, H,x, U,x, I,b, vex7 avx2_256 p_66),
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{},
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{},
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X86_OP_ENTRY3(PSLLQ_i, H,x, U,x, I,b, vex7 mmx avx2_256 p_00_66),
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X86_OP_ENTRY3(PSLLDQ_i, H,x, U,x, I,b, vex7 avx2_256 p_66),
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};
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int op = (get_modrm(s, env) >> 3) & 7;
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*entry = opcodes_group14[op];
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}
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static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry opcodes_0F6F[4] = {
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X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex1 mmx), /* movq */
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X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1), /* movdqa */
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X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* movdqu */
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{},
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};
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*entry = *decode_by_prefix(s, opcodes_0F6F);
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}
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static void decode_0F70(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry pshufw[4] = {
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X86_OP_ENTRY3(PSHUFW, P,q, Q,q, I,b, vex4 mmx),
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X86_OP_ENTRY3(PSHUFD, V,x, W,x, I,b, vex4 avx2_256),
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X86_OP_ENTRY3(PSHUFHW, V,x, W,x, I,b, vex4 avx2_256),
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X86_OP_ENTRY3(PSHUFLW, V,x, W,x, I,b, vex4 avx2_256),
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};
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*entry = *decode_by_prefix(s, pshufw);
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}
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static void decode_0F77(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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if (!(s->prefix & PREFIX_VEX)) {
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entry->gen = gen_EMMS;
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} else if (!s->vex_l) {
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entry->gen = gen_VZEROUPPER;
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entry->vex_class = 8;
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} else {
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entry->gen = gen_VZEROALL;
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entry->vex_class = 8;
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}
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}
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static void decode_0F78(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry opcodes_0F78[4] = {
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{},
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X86_OP_ENTRY3(EXTRQ_i, V,x, None,None, I,w, cpuid(SSE4A)),
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{},
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X86_OP_ENTRY3(INSERTQ_i, V,x, U,x, I,w, cpuid(SSE4A)),
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};
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*entry = *decode_by_prefix(s, opcodes_0F78);
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}
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static void decode_0F79(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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if (s->prefix & PREFIX_REPNZ) {
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entry->gen = gen_INSERTQ_r;
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} else if (s->prefix & PREFIX_DATA) {
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entry->gen = gen_EXTRQ_r;
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} else {
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entry->gen = NULL;
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};
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}
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static void decode_0F7E(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry opcodes_0F7E[4] = {
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X86_OP_ENTRY3(MOVD_from, E,y, None,None, P,y, vex5 mmx),
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X86_OP_ENTRY3(MOVD_from, E,y, None,None, V,y, vex5),
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X86_OP_ENTRY3(MOVQ, V,x, None,None, W,q, vex5), /* wrong dest Vy on SDM! */
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{},
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};
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*entry = *decode_by_prefix(s, opcodes_0F7E);
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}
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static void decode_0F7F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry opcodes_0F7F[4] = {
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X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 mmx), /* movq */
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X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1), /* movdqa */
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X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* movdqu */
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{},
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};
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*entry = *decode_by_prefix(s, opcodes_0F7F);
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}
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static void decode_0FD6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry movq[4] = {
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{},
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X86_OP_ENTRY3(MOVQ, W,x, None, None, V,q, vex5),
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X86_OP_ENTRY3(MOVq_dq, V,dq, None, None, N,q),
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X86_OP_ENTRY3(MOVq_dq, P,q, None, None, U,q),
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};
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*entry = *decode_by_prefix(s, movq);
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}
|
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|
|
static const X86OpEntry opcodes_0F38_00toEF[240] = {
|
|
[0x00] = X86_OP_ENTRY3(PSHUFB, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
[0x01] = X86_OP_ENTRY3(PHADDW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
[0x02] = X86_OP_ENTRY3(PHADDD, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
[0x03] = X86_OP_ENTRY3(PHADDSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
[0x04] = X86_OP_ENTRY3(PMADDUBSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
[0x05] = X86_OP_ENTRY3(PHSUBW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
[0x06] = X86_OP_ENTRY3(PHSUBD, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
[0x07] = X86_OP_ENTRY3(PHSUBSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
|
|
[0x10] = X86_OP_ENTRY2(PBLENDVB, V,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
[0x13] = X86_OP_ENTRY2(VCVTPH2PS, V,x, W,ph, vex11 cpuid(F16C) p_66),
|
|
[0x14] = X86_OP_ENTRY2(BLENDVPS, V,x, W,x, vex4 cpuid(SSE41) p_66),
|
|
[0x15] = X86_OP_ENTRY2(BLENDVPD, V,x, W,x, vex4 cpuid(SSE41) p_66),
|
|
/* Listed incorrectly as type 4 */
|
|
[0x16] = X86_OP_ENTRY3(VPERMD, V,qq, H,qq, W,qq, vex6 cpuid(AVX2) p_66),
|
|
[0x17] = X86_OP_ENTRY3(VPTEST, None,None, V,x, W,x, vex4 cpuid(SSE41) p_66),
|
|
|
|
/*
|
|
* Source operand listed as Mq/Ux and similar in the manual; incorrectly listed
|
|
* as 128-bit only in 2-17.
|
|
*/
|
|
[0x20] = X86_OP_ENTRY3(VPMOVSXBW, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
|
|
[0x21] = X86_OP_ENTRY3(VPMOVSXBD, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
|
|
[0x22] = X86_OP_ENTRY3(VPMOVSXBQ, V,x, None,None, W,w, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
|
|
[0x23] = X86_OP_ENTRY3(VPMOVSXWD, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
|
|
[0x24] = X86_OP_ENTRY3(VPMOVSXWQ, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
|
|
[0x25] = X86_OP_ENTRY3(VPMOVSXDQ, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
|
|
|
|
/* Same as PMOVSX. */
|
|
[0x30] = X86_OP_ENTRY3(VPMOVZXBW, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
|
|
[0x31] = X86_OP_ENTRY3(VPMOVZXBD, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
|
|
[0x32] = X86_OP_ENTRY3(VPMOVZXBQ, V,x, None,None, W,w, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
|
|
[0x33] = X86_OP_ENTRY3(VPMOVZXWD, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
|
|
[0x34] = X86_OP_ENTRY3(VPMOVZXWQ, V,x, None,None, W,d, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
|
|
[0x35] = X86_OP_ENTRY3(VPMOVZXDQ, V,x, None,None, W,q, vex5 cpuid(SSE41) avx_movx avx2_256 p_66),
|
|
[0x36] = X86_OP_ENTRY3(VPERMD, V,qq, H,qq, W,qq, vex6 cpuid(AVX2) p_66),
|
|
[0x37] = X86_OP_ENTRY3(PCMPGTQ, V,x, H,x, W,x, vex4 cpuid(SSE42) avx2_256 p_66),
|
|
|
|
[0x40] = X86_OP_ENTRY3(PMULLD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
[0x41] = X86_OP_ENTRY3(VPHMINPOSUW, V,dq, None,None, W,dq, vex4 cpuid(SSE41) p_66),
|
|
/* Listed incorrectly as type 4 */
|
|
[0x45] = X86_OP_ENTRY3(VPSRLV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66),
|
|
[0x46] = X86_OP_ENTRY3(VPSRAV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66),
|
|
[0x47] = X86_OP_ENTRY3(VPSLLV, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66),
|
|
|
|
[0x90] = X86_OP_ENTRY3(VPGATHERD, V,x, H,x, M,d, vex12 cpuid(AVX2) p_66), /* vpgatherdd/q */
|
|
[0x91] = X86_OP_ENTRY3(VPGATHERQ, V,x, H,x, M,q, vex12 cpuid(AVX2) p_66), /* vpgatherqd/q */
|
|
[0x92] = X86_OP_ENTRY3(VPGATHERD, V,x, H,x, M,d, vex12 cpuid(AVX2) p_66), /* vgatherdps/d */
|
|
[0x93] = X86_OP_ENTRY3(VPGATHERQ, V,x, H,x, M,q, vex12 cpuid(AVX2) p_66), /* vgatherqps/d */
|
|
|
|
/* Should be exception type 2 but they do not have legacy SSE equivalents? */
|
|
[0x96] = X86_OP_ENTRY3(VFMADDSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0x97] = X86_OP_ENTRY3(VFMSUBADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
|
|
[0xa6] = X86_OP_ENTRY3(VFMADDSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xa7] = X86_OP_ENTRY3(VFMSUBADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
|
|
[0xb6] = X86_OP_ENTRY3(VFMADDSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xb7] = X86_OP_ENTRY3(VFMSUBADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
|
|
[0x08] = X86_OP_ENTRY3(PSIGNB, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
[0x09] = X86_OP_ENTRY3(PSIGNW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
[0x0a] = X86_OP_ENTRY3(PSIGND, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
[0x0b] = X86_OP_ENTRY3(PMULHRSW, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
[0x0c] = X86_OP_ENTRY3(VPERMILPS, V,x, H,x, W,x, vex4 cpuid(AVX) p_00_66),
|
|
[0x0d] = X86_OP_ENTRY3(VPERMILPD, V,x, H,x, W,x, vex4 cpuid(AVX) p_66),
|
|
[0x0e] = X86_OP_ENTRY3(VTESTPS, None,None, V,x, W,x, vex4 cpuid(AVX) p_66),
|
|
[0x0f] = X86_OP_ENTRY3(VTESTPD, None,None, V,x, W,x, vex4 cpuid(AVX) p_66),
|
|
|
|
[0x18] = X86_OP_ENTRY3(VPBROADCASTD, V,x, None,None, W,d, vex6 cpuid(AVX) p_66), /* vbroadcastss */
|
|
[0x19] = X86_OP_ENTRY3(VPBROADCASTQ, V,qq, None,None, W,q, vex6 cpuid(AVX) p_66), /* vbroadcastsd */
|
|
[0x1a] = X86_OP_ENTRY3(VBROADCASTx128, V,qq, None,None, WM,dq,vex6 cpuid(AVX) p_66),
|
|
[0x1c] = X86_OP_ENTRY3(PABSB, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
[0x1d] = X86_OP_ENTRY3(PABSW, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
[0x1e] = X86_OP_ENTRY3(PABSD, V,x, None,None, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
|
|
[0x28] = X86_OP_ENTRY3(PMULDQ, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
[0x29] = X86_OP_ENTRY3(PCMPEQQ, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
[0x2a] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, WM,x, vex1 cpuid(SSE41) avx2_256 p_66), /* movntdqa */
|
|
[0x2b] = X86_OP_ENTRY3(VPACKUSDW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
[0x2c] = X86_OP_ENTRY3(VMASKMOVPS, V,x, H,x, WM,x, vex6 cpuid(AVX) p_66),
|
|
[0x2d] = X86_OP_ENTRY3(VMASKMOVPD, V,x, H,x, WM,x, vex6 cpuid(AVX) p_66),
|
|
/* Incorrectly listed as Mx,Hx,Vx in the manual */
|
|
[0x2e] = X86_OP_ENTRY3(VMASKMOVPS_st, M,x, V,x, H,x, vex6 cpuid(AVX) p_66),
|
|
[0x2f] = X86_OP_ENTRY3(VMASKMOVPD_st, M,x, V,x, H,x, vex6 cpuid(AVX) p_66),
|
|
|
|
[0x38] = X86_OP_ENTRY3(PMINSB, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
[0x39] = X86_OP_ENTRY3(PMINSD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
[0x3a] = X86_OP_ENTRY3(PMINUW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
[0x3b] = X86_OP_ENTRY3(PMINUD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
[0x3c] = X86_OP_ENTRY3(PMAXSB, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
[0x3d] = X86_OP_ENTRY3(PMAXSD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
[0x3e] = X86_OP_ENTRY3(PMAXUW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
[0x3f] = X86_OP_ENTRY3(PMAXUD, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
|
|
[0x58] = X86_OP_ENTRY3(VPBROADCASTD, V,x, None,None, W,d, vex6 cpuid(AVX2) p_66),
|
|
[0x59] = X86_OP_ENTRY3(VPBROADCASTQ, V,x, None,None, W,q, vex6 cpuid(AVX2) p_66),
|
|
[0x5a] = X86_OP_ENTRY3(VBROADCASTx128, V,qq, None,None, WM,dq,vex6 cpuid(AVX2) p_66),
|
|
|
|
[0x78] = X86_OP_ENTRY3(VPBROADCASTB, V,x, None,None, W,b, vex6 cpuid(AVX2) p_66),
|
|
[0x79] = X86_OP_ENTRY3(VPBROADCASTW, V,x, None,None, W,w, vex6 cpuid(AVX2) p_66),
|
|
|
|
[0x8c] = X86_OP_ENTRY3(VPMASKMOV, V,x, H,x, WM,x, vex6 cpuid(AVX2) p_66),
|
|
[0x8e] = X86_OP_ENTRY3(VPMASKMOV_st, M,x, V,x, H,x, vex6 cpuid(AVX2) p_66),
|
|
|
|
/* Should be exception type 2 or 3 but they do not have legacy SSE equivalents? */
|
|
[0x98] = X86_OP_ENTRY3(VFMADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0x99] = X86_OP_ENTRY3(VFMADD132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0x9a] = X86_OP_ENTRY3(VFMSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0x9b] = X86_OP_ENTRY3(VFMSUB132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0x9c] = X86_OP_ENTRY3(VFNMADD132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0x9d] = X86_OP_ENTRY3(VFNMADD132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0x9e] = X86_OP_ENTRY3(VFNMSUB132Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0x9f] = X86_OP_ENTRY3(VFNMSUB132Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
|
|
[0xa8] = X86_OP_ENTRY3(VFMADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xa9] = X86_OP_ENTRY3(VFMADD213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xaa] = X86_OP_ENTRY3(VFMSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xab] = X86_OP_ENTRY3(VFMSUB213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xac] = X86_OP_ENTRY3(VFNMADD213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xad] = X86_OP_ENTRY3(VFNMADD213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xae] = X86_OP_ENTRY3(VFNMSUB213Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xaf] = X86_OP_ENTRY3(VFNMSUB213Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
|
|
[0xb8] = X86_OP_ENTRY3(VFMADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xb9] = X86_OP_ENTRY3(VFMADD231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xba] = X86_OP_ENTRY3(VFMSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xbb] = X86_OP_ENTRY3(VFMSUB231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xbc] = X86_OP_ENTRY3(VFNMADD231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xbd] = X86_OP_ENTRY3(VFNMADD231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xbe] = X86_OP_ENTRY3(VFNMSUB231Px, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
[0xbf] = X86_OP_ENTRY3(VFNMSUB231Sx, V,x, H,x, W,x, vex6 cpuid(FMA) p_66),
|
|
|
|
[0xdb] = X86_OP_ENTRY3(VAESIMC, V,dq, None,None, W,dq, vex4 cpuid(AES) p_66),
|
|
[0xdc] = X86_OP_ENTRY3(VAESENC, V,x, H,x, W,x, vex4 cpuid(AES) p_66),
|
|
[0xdd] = X86_OP_ENTRY3(VAESENCLAST, V,x, H,x, W,x, vex4 cpuid(AES) p_66),
|
|
[0xde] = X86_OP_ENTRY3(VAESDEC, V,x, H,x, W,x, vex4 cpuid(AES) p_66),
|
|
[0xdf] = X86_OP_ENTRY3(VAESDECLAST, V,x, H,x, W,x, vex4 cpuid(AES) p_66),
|
|
};
|
|
|
|
/* five rows for no prefix, 66, F3, F2, 66+F2 */
|
|
static const X86OpEntry opcodes_0F38_F0toFF[16][5] = {
|
|
[0] = {
|
|
X86_OP_ENTRY3(MOVBE, G,y, M,y, None,None, cpuid(MOVBE)),
|
|
X86_OP_ENTRY3(MOVBE, G,w, M,w, None,None, cpuid(MOVBE)),
|
|
{},
|
|
X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)),
|
|
X86_OP_ENTRY2(CRC32, G,d, E,b, cpuid(SSE42)),
|
|
},
|
|
[1] = {
|
|
X86_OP_ENTRY3(MOVBE, M,y, G,y, None,None, cpuid(MOVBE)),
|
|
X86_OP_ENTRY3(MOVBE, M,w, G,w, None,None, cpuid(MOVBE)),
|
|
{},
|
|
X86_OP_ENTRY2(CRC32, G,d, E,y, cpuid(SSE42)),
|
|
X86_OP_ENTRY2(CRC32, G,d, E,w, cpuid(SSE42)),
|
|
},
|
|
[2] = {
|
|
X86_OP_ENTRY3(ANDN, G,y, B,y, E,y, vex13 cpuid(BMI1)),
|
|
{},
|
|
{},
|
|
{},
|
|
{},
|
|
},
|
|
[3] = {
|
|
X86_OP_GROUP3(group17, B,y, E,y, None,None, vex13 cpuid(BMI1)),
|
|
{},
|
|
{},
|
|
{},
|
|
{},
|
|
},
|
|
[5] = {
|
|
X86_OP_ENTRY3(BZHI, G,y, E,y, B,y, vex13 cpuid(BMI1)),
|
|
{},
|
|
X86_OP_ENTRY3(PEXT, G,y, B,y, E,y, vex13 cpuid(BMI2)),
|
|
X86_OP_ENTRY3(PDEP, G,y, B,y, E,y, vex13 cpuid(BMI2)),
|
|
{},
|
|
},
|
|
[6] = {
|
|
{},
|
|
X86_OP_ENTRY2(ADCX, G,y, E,y, cpuid(ADX)),
|
|
X86_OP_ENTRY2(ADOX, G,y, E,y, cpuid(ADX)),
|
|
X86_OP_ENTRY3(MULX, /* B,y, */ G,y, E,y, 2,y, vex13 cpuid(BMI2)),
|
|
{},
|
|
},
|
|
[7] = {
|
|
X86_OP_ENTRY3(BEXTR, G,y, E,y, B,y, vex13 cpuid(BMI1)),
|
|
X86_OP_ENTRY3(SHLX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
|
|
X86_OP_ENTRY3(SARX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
|
|
X86_OP_ENTRY3(SHRX, G,y, E,y, B,y, vex13 cpuid(BMI1)),
|
|
{},
|
|
},
|
|
};
|
|
|
|
static void decode_0F38(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
*b = x86_ldub_code(env, s);
|
|
if (*b < 0xf0) {
|
|
*entry = opcodes_0F38_00toEF[*b];
|
|
} else {
|
|
int row = 0;
|
|
if (s->prefix & PREFIX_REPZ) {
|
|
/* The REPZ (F3) prefix has priority over 66 */
|
|
row = 2;
|
|
} else {
|
|
row += s->prefix & PREFIX_REPNZ ? 3 : 0;
|
|
row += s->prefix & PREFIX_DATA ? 1 : 0;
|
|
}
|
|
*entry = opcodes_0F38_F0toFF[*b & 15][row];
|
|
}
|
|
}
|
|
|
|
static void decode_VINSERTPS(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
static const X86OpEntry
|
|
vinsertps_reg = X86_OP_ENTRY4(VINSERTPS_r, V,dq, H,dq, U,dq, vex5 cpuid(SSE41) p_66),
|
|
vinsertps_mem = X86_OP_ENTRY4(VINSERTPS_m, V,dq, H,dq, M,d, vex5 cpuid(SSE41) p_66);
|
|
|
|
int modrm = get_modrm(s, env);
|
|
*entry = (modrm >> 6) == 3 ? vinsertps_reg : vinsertps_mem;
|
|
}
|
|
|
|
static const X86OpEntry opcodes_0F3A[256] = {
|
|
/*
|
|
* These are VEX-only, but incorrectly listed in the manual as exception type 4.
|
|
* Also the "qq" instructions are sometimes omitted by Table 2-17, but are VEX256
|
|
* only.
|
|
*/
|
|
[0x00] = X86_OP_ENTRY3(VPERMQ, V,qq, W,qq, I,b, vex6 cpuid(AVX2) p_66),
|
|
[0x01] = X86_OP_ENTRY3(VPERMQ, V,qq, W,qq, I,b, vex6 cpuid(AVX2) p_66), /* VPERMPD */
|
|
[0x02] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex6 cpuid(AVX2) p_66), /* VPBLENDD */
|
|
[0x04] = X86_OP_ENTRY3(VPERMILPS_i, V,x, W,x, I,b, vex6 cpuid(AVX) p_66),
|
|
[0x05] = X86_OP_ENTRY3(VPERMILPD_i, V,x, W,x, I,b, vex6 cpuid(AVX) p_66),
|
|
[0x06] = X86_OP_ENTRY4(VPERM2x128, V,qq, H,qq, W,qq, vex6 cpuid(AVX) p_66),
|
|
|
|
[0x14] = X86_OP_ENTRY3(PEXTRB, E,b, V,dq, I,b, vex5 cpuid(SSE41) zext0 p_66),
|
|
[0x15] = X86_OP_ENTRY3(PEXTRW, E,w, V,dq, I,b, vex5 cpuid(SSE41) zext0 p_66),
|
|
[0x16] = X86_OP_ENTRY3(PEXTR, E,y, V,dq, I,b, vex5 cpuid(SSE41) p_66),
|
|
[0x17] = X86_OP_ENTRY3(VEXTRACTPS, E,d, V,dq, I,b, vex5 cpuid(SSE41) p_66),
|
|
[0x1d] = X86_OP_ENTRY3(VCVTPS2PH, W,ph, V,x, I,b, vex11 cpuid(F16C) p_66),
|
|
|
|
[0x20] = X86_OP_ENTRY4(PINSRB, V,dq, H,dq, E,b, vex5 cpuid(SSE41) zext2 p_66),
|
|
[0x21] = X86_OP_GROUP0(VINSERTPS),
|
|
[0x22] = X86_OP_ENTRY4(PINSR, V,dq, H,dq, E,y, vex5 cpuid(SSE41) p_66),
|
|
|
|
[0x40] = X86_OP_ENTRY4(VDDPS, V,x, H,x, W,x, vex2 cpuid(SSE41) p_66),
|
|
[0x41] = X86_OP_ENTRY4(VDDPD, V,dq, H,dq, W,dq, vex2 cpuid(SSE41) p_66),
|
|
[0x42] = X86_OP_ENTRY4(VMPSADBW, V,x, H,x, W,x, vex2 cpuid(SSE41) avx2_256 p_66),
|
|
[0x44] = X86_OP_ENTRY4(PCLMULQDQ, V,dq, H,dq, W,dq, vex4 cpuid(PCLMULQDQ) p_66),
|
|
[0x46] = X86_OP_ENTRY4(VPERM2x128, V,qq, H,qq, W,qq, vex6 cpuid(AVX2) p_66),
|
|
|
|
[0x60] = X86_OP_ENTRY4(PCMPESTRM, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
|
|
[0x61] = X86_OP_ENTRY4(PCMPESTRI, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
|
|
[0x62] = X86_OP_ENTRY4(PCMPISTRM, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
|
|
[0x63] = X86_OP_ENTRY4(PCMPISTRI, None,None, V,dq, W,dq, vex4_unal cpuid(SSE42) p_66),
|
|
|
|
[0x08] = X86_OP_ENTRY3(VROUNDPS, V,x, W,x, I,b, vex2 cpuid(SSE41) p_66),
|
|
[0x09] = X86_OP_ENTRY3(VROUNDPD, V,x, W,x, I,b, vex2 cpuid(SSE41) p_66),
|
|
/*
|
|
* Not listed as four operand in the manual. Also writes and reads 128-bits
|
|
* from the first two operands due to the V operand picking higher entries of
|
|
* the H operand; the "Vss,Hss,Wss" description from the manual is incorrect.
|
|
* For other unary operations such as VSQRTSx this is hidden by the "REPScalar"
|
|
* value of vex_special, because the table lists the operand types of VSQRTPx.
|
|
*/
|
|
[0x0a] = X86_OP_ENTRY4(VROUNDSS, V,x, H,x, W,ss, vex3 cpuid(SSE41) p_66),
|
|
[0x0b] = X86_OP_ENTRY4(VROUNDSD, V,x, H,x, W,sd, vex3 cpuid(SSE41) p_66),
|
|
[0x0c] = X86_OP_ENTRY4(VBLENDPS, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
|
|
[0x0d] = X86_OP_ENTRY4(VBLENDPD, V,x, H,x, W,x, vex4 cpuid(SSE41) p_66),
|
|
[0x0e] = X86_OP_ENTRY4(VPBLENDW, V,x, H,x, W,x, vex4 cpuid(SSE41) avx2_256 p_66),
|
|
[0x0f] = X86_OP_ENTRY4(PALIGNR, V,x, H,x, W,x, vex4 cpuid(SSSE3) mmx avx2_256 p_00_66),
|
|
|
|
[0x18] = X86_OP_ENTRY4(VINSERTx128, V,qq, H,qq, W,qq, vex6 cpuid(AVX) p_66),
|
|
[0x19] = X86_OP_ENTRY3(VEXTRACTx128, W,dq, V,qq, I,b, vex6 cpuid(AVX) p_66),
|
|
|
|
[0x38] = X86_OP_ENTRY4(VINSERTx128, V,qq, H,qq, W,qq, vex6 cpuid(AVX2) p_66),
|
|
[0x39] = X86_OP_ENTRY3(VEXTRACTx128, W,dq, V,qq, I,b, vex6 cpuid(AVX2) p_66),
|
|
|
|
/* Listed incorrectly as type 4 */
|
|
[0x4a] = X86_OP_ENTRY4(VBLENDVPS, V,x, H,x, W,x, vex6 cpuid(AVX) p_66),
|
|
[0x4b] = X86_OP_ENTRY4(VBLENDVPD, V,x, H,x, W,x, vex6 cpuid(AVX) p_66),
|
|
[0x4c] = X86_OP_ENTRY4(VPBLENDVB, V,x, H,x, W,x, vex6 cpuid(AVX) p_66 avx2_256),
|
|
|
|
[0xdf] = X86_OP_ENTRY3(VAESKEYGEN, V,dq, W,dq, I,b, vex4 cpuid(AES) p_66),
|
|
|
|
[0xF0] = X86_OP_ENTRY3(RORX, G,y, E,y, I,b, vex13 cpuid(BMI2) p_f2),
|
|
};
|
|
|
|
static void decode_0F3A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
*b = x86_ldub_code(env, s);
|
|
*entry = opcodes_0F3A[*b];
|
|
}
|
|
|
|
/*
|
|
* There are some mistakes in the operands in the manual, and the load/store/register
|
|
* cases are easiest to keep separate, so the entries for 10-17 follow simplicity and
|
|
* efficiency of implementation rather than copying what the manual says.
|
|
*
|
|
* In particular:
|
|
*
|
|
* 1) "VMOVSS m32, xmm1" and "VMOVSD m64, xmm1" do not support VEX.vvvv != 1111b,
|
|
* but this is not mentioned in the tables.
|
|
*
|
|
* 2) MOVHLPS, MOVHPS, MOVHPD, MOVLPD, MOVLPS read the high quadword of one of their
|
|
* operands, which must therefore be dq; MOVLPD and MOVLPS also write the high
|
|
* quadword of the V operand.
|
|
*/
|
|
static void decode_0F10(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
static const X86OpEntry opcodes_0F10_reg[4] = {
|
|
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */
|
|
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */
|
|
X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex4),
|
|
X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex4), /* MOVSD */
|
|
};
|
|
|
|
static const X86OpEntry opcodes_0F10_mem[4] = {
|
|
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */
|
|
X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */
|
|
X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex4),
|
|
X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex4),
|
|
};
|
|
|
|
if ((get_modrm(s, env) >> 6) == 3) {
|
|
*entry = *decode_by_prefix(s, opcodes_0F10_reg);
|
|
} else {
|
|
*entry = *decode_by_prefix(s, opcodes_0F10_mem);
|
|
}
|
|
}
|
|
|
|
static void decode_0F11(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
static const X86OpEntry opcodes_0F11_reg[4] = {
|
|
X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPS */
|
|
X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPD */
|
|
X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex4),
|
|
X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex4), /* MOVSD */
|
|
};
|
|
|
|
static const X86OpEntry opcodes_0F11_mem[4] = {
|
|
X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPS */
|
|
X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPD */
|
|
X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4),
|
|
X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4), /* MOVSD */
|
|
};
|
|
|
|
if ((get_modrm(s, env) >> 6) == 3) {
|
|
*entry = *decode_by_prefix(s, opcodes_0F11_reg);
|
|
} else {
|
|
*entry = *decode_by_prefix(s, opcodes_0F11_mem);
|
|
}
|
|
}
|
|
|
|
static void decode_0F12(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
static const X86OpEntry opcodes_0F12_mem[4] = {
|
|
/*
|
|
* Use dq for operand for compatibility with gen_MOVSD and
|
|
* to allow VEX128 only.
|
|
*/
|
|
X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex4), /* MOVLPS */
|
|
X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex4), /* MOVLPD */
|
|
X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)),
|
|
X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, WM,q, vex4 cpuid(SSE3)), /* qq if VEX.256 */
|
|
};
|
|
static const X86OpEntry opcodes_0F12_reg[4] = {
|
|
X86_OP_ENTRY3(VMOVHLPS, V,dq, H,dq, U,dq, vex4),
|
|
X86_OP_ENTRY3(VMOVLPx, W,x, H,x, U,q, vex4), /* MOVLPD */
|
|
X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
|
|
X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
|
|
};
|
|
|
|
if ((get_modrm(s, env) >> 6) == 3) {
|
|
*entry = *decode_by_prefix(s, opcodes_0F12_reg);
|
|
} else {
|
|
*entry = *decode_by_prefix(s, opcodes_0F12_mem);
|
|
if ((s->prefix & PREFIX_REPNZ) && s->vex_l) {
|
|
entry->s2 = X86_SIZE_qq;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void decode_0F16(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
static const X86OpEntry opcodes_0F16_mem[4] = {
|
|
/*
|
|
* Operand 1 technically only reads the low 64 bits, but uses dq so that
|
|
* it is easier to check for op0 == op1 in an endianness-neutral manner.
|
|
*/
|
|
X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex4), /* MOVHPS */
|
|
X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex4), /* MOVHPD */
|
|
X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)),
|
|
{},
|
|
};
|
|
static const X86OpEntry opcodes_0F16_reg[4] = {
|
|
/* Same as above, operand 1 could be Hq if it wasn't for big-endian. */
|
|
X86_OP_ENTRY3(VMOVLHPS, V,dq, H,dq, U,q, vex4),
|
|
X86_OP_ENTRY3(VMOVHPx, V,x, H,x, U,x, vex4), /* MOVHPD */
|
|
X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
|
|
{},
|
|
};
|
|
|
|
if ((get_modrm(s, env) >> 6) == 3) {
|
|
*entry = *decode_by_prefix(s, opcodes_0F16_reg);
|
|
} else {
|
|
*entry = *decode_by_prefix(s, opcodes_0F16_mem);
|
|
}
|
|
}
|
|
|
|
static void decode_0F2A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
static const X86OpEntry opcodes_0F2A[4] = {
|
|
X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q),
|
|
X86_OP_ENTRY3(CVTPI2Px, V,x, None,None, Q,q),
|
|
X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3),
|
|
X86_OP_ENTRY3(VCVTSI2Sx, V,x, H,x, E,y, vex3),
|
|
};
|
|
*entry = *decode_by_prefix(s, opcodes_0F2A);
|
|
}
|
|
|
|
static void decode_0F2B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
static const X86OpEntry opcodes_0F2B[4] = {
|
|
X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPS */
|
|
X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPD */
|
|
X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSS */
|
|
X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4 cpuid(SSE4A)), /* MOVNTSD */
|
|
};
|
|
|
|
*entry = *decode_by_prefix(s, opcodes_0F2B);
|
|
}
|
|
|
|
static void decode_0F2C(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
static const X86OpEntry opcodes_0F2C[4] = {
|
|
/* Listed as ps/pd in the manual, but CVTTPS2PI only reads 64-bit. */
|
|
X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,q),
|
|
X86_OP_ENTRY3(CVTTPx2PI, P,q, None,None, W,dq),
|
|
X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,ss, vex3),
|
|
X86_OP_ENTRY3(VCVTTSx2SI, G,y, None,None, W,sd, vex3),
|
|
};
|
|
*entry = *decode_by_prefix(s, opcodes_0F2C);
|
|
}
|
|
|
|
static void decode_0F2D(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
static const X86OpEntry opcodes_0F2D[4] = {
|
|
/* Listed as ps/pd in the manual, but CVTPS2PI only reads 64-bit. */
|
|
X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,q),
|
|
X86_OP_ENTRY3(CVTPx2PI, P,q, None,None, W,dq),
|
|
X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,ss, vex3),
|
|
X86_OP_ENTRY3(VCVTSx2SI, G,y, None,None, W,sd, vex3),
|
|
};
|
|
*entry = *decode_by_prefix(s, opcodes_0F2D);
|
|
}
|
|
|
|
static void decode_sse_unary(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ))) {
|
|
entry->op1 = X86_TYPE_None;
|
|
entry->s1 = X86_SIZE_None;
|
|
}
|
|
switch (*b) {
|
|
case 0x51: entry->gen = gen_VSQRT; break;
|
|
case 0x52: entry->gen = gen_VRSQRT; break;
|
|
case 0x53: entry->gen = gen_VRCP; break;
|
|
case 0x5A: entry->gen = gen_VCVTfp2fp; break;
|
|
}
|
|
}
|
|
|
|
static void decode_0F5B(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
static const X86OpEntry opcodes_0F5B[4] = {
|
|
X86_OP_ENTRY2(VCVTDQ2PS, V,x, W,x, vex2),
|
|
X86_OP_ENTRY2(VCVTPS2DQ, V,x, W,x, vex2),
|
|
X86_OP_ENTRY2(VCVTTPS2DQ, V,x, W,x, vex2),
|
|
{},
|
|
};
|
|
*entry = *decode_by_prefix(s, opcodes_0F5B);
|
|
}
|
|
|
|
static void decode_0FE6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
static const X86OpEntry opcodes_0FE6[4] = {
|
|
{},
|
|
X86_OP_ENTRY2(VCVTTPD2DQ, V,x, W,x, vex2),
|
|
X86_OP_ENTRY2(VCVTDQ2PD, V,x, W,x, vex2),
|
|
X86_OP_ENTRY2(VCVTPD2DQ, V,x, W,x, vex2),
|
|
};
|
|
*entry = *decode_by_prefix(s, opcodes_0FE6);
|
|
}
|
|
|
|
static const X86OpEntry opcodes_0F[256] = {
|
|
[0x0E] = X86_OP_ENTRY0(EMMS, cpuid(3DNOW)), /* femms */
|
|
/*
|
|
* 3DNow!'s opcode byte comes *after* modrm and displacements, making it
|
|
* more like an Ib operand. Dispatch to the right helper in a single gen_*
|
|
* function.
|
|
*/
|
|
[0x0F] = X86_OP_ENTRY3(3dnow, P,q, Q,q, I,b, cpuid(3DNOW)),
|
|
|
|
[0x10] = X86_OP_GROUP0(0F10),
|
|
[0x11] = X86_OP_GROUP0(0F11),
|
|
[0x12] = X86_OP_GROUP0(0F12),
|
|
[0x13] = X86_OP_ENTRY3(VMOVLPx_st, M,q, None,None, V,q, vex4 p_00_66),
|
|
[0x14] = X86_OP_ENTRY3(VUNPCKLPx, V,x, H,x, W,x, vex4 p_00_66),
|
|
[0x15] = X86_OP_ENTRY3(VUNPCKHPx, V,x, H,x, W,x, vex4 p_00_66),
|
|
[0x16] = X86_OP_GROUP0(0F16),
|
|
/* Incorrectly listed as Mq,Vq in the manual */
|
|
[0x17] = X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex4 p_00_66),
|
|
|
|
[0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66),
|
|
[0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
|
|
[0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex5 p_00_f3),
|
|
[0x53] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex5 p_00_f3),
|
|
[0x54] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 p_00_66), /* vand */
|
|
[0x55] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 p_00_66), /* vandn */
|
|
[0x56] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 p_00_66), /* vor */
|
|
[0x57] = X86_OP_ENTRY3(PXOR, V,x, H,x, W,x, vex4 p_00_66), /* vxor */
|
|
|
|
[0x60] = X86_OP_ENTRY3(PUNPCKLBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x61] = X86_OP_ENTRY3(PUNPCKLWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x62] = X86_OP_ENTRY3(PUNPCKLDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x63] = X86_OP_ENTRY3(PACKSSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x64] = X86_OP_ENTRY3(PCMPGTB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x65] = X86_OP_ENTRY3(PCMPGTW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x66] = X86_OP_ENTRY3(PCMPGTD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x67] = X86_OP_ENTRY3(PACKUSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
|
|
[0x70] = X86_OP_GROUP0(0F70),
|
|
[0x71] = X86_OP_GROUP0(group12),
|
|
[0x72] = X86_OP_GROUP0(group13),
|
|
[0x73] = X86_OP_GROUP0(group14),
|
|
[0x74] = X86_OP_ENTRY3(PCMPEQB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x75] = X86_OP_ENTRY3(PCMPEQW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x76] = X86_OP_ENTRY3(PCMPEQD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x77] = X86_OP_GROUP0(0F77),
|
|
|
|
[0x28] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_66), /* MOVAPS */
|
|
[0x29] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_66), /* MOVAPS */
|
|
[0x2A] = X86_OP_GROUP0(0F2A),
|
|
[0x2B] = X86_OP_GROUP0(0F2B),
|
|
[0x2C] = X86_OP_GROUP0(0F2C),
|
|
[0x2D] = X86_OP_GROUP0(0F2D),
|
|
[0x2E] = X86_OP_ENTRY3(VUCOMI, None,None, V,x, W,x, vex4 p_00_66),
|
|
[0x2F] = X86_OP_ENTRY3(VCOMI, None,None, V,x, W,x, vex4 p_00_66),
|
|
|
|
[0x38] = X86_OP_GROUP0(0F38),
|
|
[0x3a] = X86_OP_GROUP0(0F3A),
|
|
|
|
[0x58] = X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
|
|
[0x59] = X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
|
|
[0x5a] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex3 p_00_66_f3_f2),
|
|
[0x5b] = X86_OP_GROUP0(0F5B),
|
|
[0x5c] = X86_OP_ENTRY3(VSUB, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
|
|
[0x5d] = X86_OP_ENTRY3(VMIN, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
|
|
[0x5e] = X86_OP_ENTRY3(VDIV, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
|
|
[0x5f] = X86_OP_ENTRY3(VMAX, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
|
|
|
|
[0x68] = X86_OP_ENTRY3(PUNPCKHBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x69] = X86_OP_ENTRY3(PUNPCKHWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x6a] = X86_OP_ENTRY3(PUNPCKHDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x6b] = X86_OP_ENTRY3(PACKSSDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0x6c] = X86_OP_ENTRY3(PUNPCKLQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256),
|
|
[0x6d] = X86_OP_ENTRY3(PUNPCKHQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256),
|
|
[0x6e] = X86_OP_ENTRY3(MOVD_to, V,x, None,None, E,y, vex5 mmx p_00_66), /* wrong dest Vy on SDM! */
|
|
[0x6f] = X86_OP_GROUP0(0F6F),
|
|
|
|
[0x78] = X86_OP_GROUP0(0F78),
|
|
[0x79] = X86_OP_GROUP2(0F79, V,x, U,x, cpuid(SSE4A)),
|
|
[0x7c] = X86_OP_ENTRY3(VHADD, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2),
|
|
[0x7d] = X86_OP_ENTRY3(VHSUB, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2),
|
|
[0x7e] = X86_OP_GROUP0(0F7E),
|
|
[0x7f] = X86_OP_GROUP0(0F7F),
|
|
|
|
[0xae] = X86_OP_GROUP0(group15),
|
|
|
|
[0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
|
|
[0xc4] = X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_00_66),
|
|
[0xc5] = X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_00_66),
|
|
[0xc6] = X86_OP_ENTRY4(VSHUF, V,x, H,x, W,x, vex4 p_00_66),
|
|
|
|
[0xd0] = X86_OP_ENTRY3(VADDSUB, V,x, H,x, W,x, vex2 cpuid(SSE3) p_66_f2),
|
|
[0xd1] = X86_OP_ENTRY3(PSRLW_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xd2] = X86_OP_ENTRY3(PSRLD_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xd3] = X86_OP_ENTRY3(PSRLQ_r, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xd4] = X86_OP_ENTRY3(PADDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xd5] = X86_OP_ENTRY3(PMULLW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xd6] = X86_OP_GROUP0(0FD6),
|
|
[0xd7] = X86_OP_ENTRY3(PMOVMSKB, G,d, None,None, U,x, vex7 mmx avx2_256 p_00_66),
|
|
|
|
[0xe0] = X86_OP_ENTRY3(PAVGB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xe1] = X86_OP_ENTRY3(PSRAW_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
|
|
[0xe2] = X86_OP_ENTRY3(PSRAD_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
|
|
[0xe3] = X86_OP_ENTRY3(PAVGW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xe4] = X86_OP_ENTRY3(PMULHUW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xe5] = X86_OP_ENTRY3(PMULHW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xe6] = X86_OP_GROUP0(0FE6),
|
|
[0xe7] = X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 mmx p_00_66), /* MOVNTQ/MOVNTDQ */
|
|
|
|
[0xf0] = X86_OP_ENTRY3(MOVDQ, V,x, None,None, WM,x, vex4_unal cpuid(SSE3) p_f2), /* LDDQU */
|
|
[0xf1] = X86_OP_ENTRY3(PSLLW_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
|
|
[0xf2] = X86_OP_ENTRY3(PSLLD_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
|
|
[0xf3] = X86_OP_ENTRY3(PSLLQ_r, V,x, H,x, W,x, vex7 mmx avx2_256 p_00_66),
|
|
[0xf4] = X86_OP_ENTRY3(PMULUDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xf5] = X86_OP_ENTRY3(PMADDWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xf6] = X86_OP_ENTRY3(PSADBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xf7] = X86_OP_ENTRY3(MASKMOV, None,None, V,dq, U,dq, vex4_unal avx2_256 mmx p_00_66),
|
|
|
|
/* Incorrectly missing from 2-17 */
|
|
[0xd8] = X86_OP_ENTRY3(PSUBUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xd9] = X86_OP_ENTRY3(PSUBUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xda] = X86_OP_ENTRY3(PMINUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xdb] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xdc] = X86_OP_ENTRY3(PADDUSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xdd] = X86_OP_ENTRY3(PADDUSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xde] = X86_OP_ENTRY3(PMAXUB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xdf] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
|
|
[0xe8] = X86_OP_ENTRY3(PSUBSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xe9] = X86_OP_ENTRY3(PSUBSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xea] = X86_OP_ENTRY3(PMINSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xeb] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xec] = X86_OP_ENTRY3(PADDSB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xed] = X86_OP_ENTRY3(PADDSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xee] = X86_OP_ENTRY3(PMAXSW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xef] = X86_OP_ENTRY3(PXOR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
|
|
[0xf8] = X86_OP_ENTRY3(PSUBB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xf9] = X86_OP_ENTRY3(PSUBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xfa] = X86_OP_ENTRY3(PSUBD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xfb] = X86_OP_ENTRY3(PSUBQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xfc] = X86_OP_ENTRY3(PADDB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xfd] = X86_OP_ENTRY3(PADDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
[0xfe] = X86_OP_ENTRY3(PADDD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
|
|
/* 0xff = UD0 */
|
|
};
|
|
|
|
static void do_decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
*entry = opcodes_0F[*b];
|
|
}
|
|
|
|
static void decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
*b = x86_ldub_code(env, s);
|
|
do_decode_0F(s, env, entry, b);
|
|
}
|
|
|
|
static const X86OpEntry opcodes_root[256] = {
|
|
[0x0F] = X86_OP_GROUP0(0F),
|
|
};
|
|
|
|
#undef mmx
|
|
#undef vex1
|
|
#undef vex2
|
|
#undef vex3
|
|
#undef vex4
|
|
#undef vex4_unal
|
|
#undef vex5
|
|
#undef vex6
|
|
#undef vex7
|
|
#undef vex8
|
|
#undef vex11
|
|
#undef vex12
|
|
#undef vex13
|
|
|
|
/*
|
|
* Decode the fixed part of the opcode and place the last
|
|
* in b.
|
|
*/
|
|
static void decode_root(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
|
{
|
|
*entry = opcodes_root[*b];
|
|
}
|
|
|
|
|
|
static int decode_modrm(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
|
|
X86DecodedOp *op, X86OpType type)
|
|
{
|
|
int modrm = get_modrm(s, env);
|
|
if ((modrm >> 6) == 3) {
|
|
if (s->prefix & PREFIX_LOCK) {
|
|
decode->e.gen = gen_illegal;
|
|
return 0xff;
|
|
}
|
|
op->n = (modrm & 7);
|
|
if (type != X86_TYPE_Q && type != X86_TYPE_N) {
|
|
op->n |= REX_B(s);
|
|
}
|
|
} else {
|
|
op->has_ea = true;
|
|
op->n = -1;
|
|
decode->mem = gen_lea_modrm_0(env, s, get_modrm(s, env));
|
|
}
|
|
return modrm;
|
|
}
|
|
|
|
static bool decode_op_size(DisasContext *s, X86OpEntry *e, X86OpSize size, MemOp *ot)
|
|
{
|
|
switch (size) {
|
|
case X86_SIZE_b: /* byte */
|
|
*ot = MO_8;
|
|
return true;
|
|
|
|
case X86_SIZE_d: /* 32-bit */
|
|
case X86_SIZE_ss: /* SSE/AVX scalar single precision */
|
|
*ot = MO_32;
|
|
return true;
|
|
|
|
case X86_SIZE_p: /* Far pointer, return offset size */
|
|
case X86_SIZE_s: /* Descriptor, return offset size */
|
|
case X86_SIZE_v: /* 16/32/64-bit, based on operand size */
|
|
*ot = s->dflag;
|
|
return true;
|
|
|
|
case X86_SIZE_pi: /* MMX */
|
|
case X86_SIZE_q: /* 64-bit */
|
|
case X86_SIZE_sd: /* SSE/AVX scalar double precision */
|
|
*ot = MO_64;
|
|
return true;
|
|
|
|
case X86_SIZE_w: /* 16-bit */
|
|
*ot = MO_16;
|
|
return true;
|
|
|
|
case X86_SIZE_y: /* 32/64-bit, based on operand size */
|
|
*ot = s->dflag == MO_16 ? MO_32 : s->dflag;
|
|
return true;
|
|
|
|
case X86_SIZE_z: /* 16-bit for 16-bit operand size, else 32-bit */
|
|
*ot = s->dflag == MO_16 ? MO_16 : MO_32;
|
|
return true;
|
|
|
|
case X86_SIZE_dq: /* SSE/AVX 128-bit */
|
|
if (e->special == X86_SPECIAL_MMX &&
|
|
!(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
|
|
*ot = MO_64;
|
|
return true;
|
|
}
|
|
if (s->vex_l && e->s0 != X86_SIZE_qq && e->s1 != X86_SIZE_qq) {
|
|
return false;
|
|
}
|
|
*ot = MO_128;
|
|
return true;
|
|
|
|
case X86_SIZE_qq: /* AVX 256-bit */
|
|
if (!s->vex_l) {
|
|
return false;
|
|
}
|
|
*ot = MO_256;
|
|
return true;
|
|
|
|
case X86_SIZE_x: /* 128/256-bit, based on operand size */
|
|
if (e->special == X86_SPECIAL_MMX &&
|
|
!(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
|
|
*ot = MO_64;
|
|
return true;
|
|
}
|
|
/* fall through */
|
|
case X86_SIZE_ps: /* SSE/AVX packed single precision */
|
|
case X86_SIZE_pd: /* SSE/AVX packed double precision */
|
|
*ot = s->vex_l ? MO_256 : MO_128;
|
|
return true;
|
|
|
|
case X86_SIZE_ph: /* SSE/AVX packed half precision */
|
|
*ot = s->vex_l ? MO_128 : MO_64;
|
|
return true;
|
|
|
|
case X86_SIZE_d64: /* Default to 64-bit in 64-bit mode */
|
|
*ot = CODE64(s) && s->dflag == MO_32 ? MO_64 : s->dflag;
|
|
return true;
|
|
|
|
case X86_SIZE_f64: /* Ignore size override prefix in 64-bit mode */
|
|
*ot = CODE64(s) ? MO_64 : s->dflag;
|
|
return true;
|
|
|
|
default:
|
|
*ot = -1;
|
|
return true;
|
|
}
|
|
}
|
|
|
|
static bool decode_op(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
|
|
X86DecodedOp *op, X86OpType type, int b)
|
|
{
|
|
int modrm;
|
|
|
|
switch (type) {
|
|
case X86_TYPE_None: /* Implicit or absent */
|
|
case X86_TYPE_A: /* Implicit */
|
|
case X86_TYPE_F: /* EFLAGS/RFLAGS */
|
|
break;
|
|
|
|
case X86_TYPE_B: /* VEX.vvvv selects a GPR */
|
|
op->unit = X86_OP_INT;
|
|
op->n = s->vex_v;
|
|
break;
|
|
|
|
case X86_TYPE_C: /* REG in the modrm byte selects a control register */
|
|
op->unit = X86_OP_CR;
|
|
goto get_reg;
|
|
|
|
case X86_TYPE_D: /* REG in the modrm byte selects a debug register */
|
|
op->unit = X86_OP_DR;
|
|
goto get_reg;
|
|
|
|
case X86_TYPE_G: /* REG in the modrm byte selects a GPR */
|
|
op->unit = X86_OP_INT;
|
|
goto get_reg;
|
|
|
|
case X86_TYPE_S: /* reg selects a segment register */
|
|
op->unit = X86_OP_SEG;
|
|
goto get_reg;
|
|
|
|
case X86_TYPE_P:
|
|
op->unit = X86_OP_MMX;
|
|
goto get_reg;
|
|
|
|
case X86_TYPE_V: /* reg in the modrm byte selects an XMM/YMM register */
|
|
if (decode->e.special == X86_SPECIAL_MMX &&
|
|
!(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
|
|
op->unit = X86_OP_MMX;
|
|
} else {
|
|
op->unit = X86_OP_SSE;
|
|
}
|
|
get_reg:
|
|
op->n = ((get_modrm(s, env) >> 3) & 7) | REX_R(s);
|
|
break;
|
|
|
|
case X86_TYPE_E: /* ALU modrm operand */
|
|
op->unit = X86_OP_INT;
|
|
goto get_modrm;
|
|
|
|
case X86_TYPE_Q: /* MMX modrm operand */
|
|
op->unit = X86_OP_MMX;
|
|
goto get_modrm;
|
|
|
|
case X86_TYPE_W: /* XMM/YMM modrm operand */
|
|
if (decode->e.special == X86_SPECIAL_MMX &&
|
|
!(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
|
|
op->unit = X86_OP_MMX;
|
|
} else {
|
|
op->unit = X86_OP_SSE;
|
|
}
|
|
goto get_modrm;
|
|
|
|
case X86_TYPE_N: /* R/M in the modrm byte selects an MMX register */
|
|
op->unit = X86_OP_MMX;
|
|
goto get_modrm_reg;
|
|
|
|
case X86_TYPE_U: /* R/M in the modrm byte selects an XMM/YMM register */
|
|
if (decode->e.special == X86_SPECIAL_MMX &&
|
|
!(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
|
|
op->unit = X86_OP_MMX;
|
|
} else {
|
|
op->unit = X86_OP_SSE;
|
|
}
|
|
goto get_modrm_reg;
|
|
|
|
case X86_TYPE_R: /* R/M in the modrm byte selects a register */
|
|
op->unit = X86_OP_INT;
|
|
get_modrm_reg:
|
|
modrm = get_modrm(s, env);
|
|
if ((modrm >> 6) != 3) {
|
|
return false;
|
|
}
|
|
goto get_modrm;
|
|
|
|
case X86_TYPE_WM: /* modrm byte selects an XMM/YMM memory operand */
|
|
op->unit = X86_OP_SSE;
|
|
/* fall through */
|
|
case X86_TYPE_M: /* modrm byte selects a memory operand */
|
|
modrm = get_modrm(s, env);
|
|
if ((modrm >> 6) == 3) {
|
|
return false;
|
|
}
|
|
get_modrm:
|
|
decode_modrm(s, env, decode, op, type);
|
|
break;
|
|
|
|
case X86_TYPE_O: /* Absolute address encoded in the instruction */
|
|
op->unit = X86_OP_INT;
|
|
op->has_ea = true;
|
|
op->n = -1;
|
|
decode->mem = (AddressParts) {
|
|
.def_seg = R_DS,
|
|
.base = -1,
|
|
.index = -1,
|
|
.disp = insn_get_addr(env, s, s->aflag)
|
|
};
|
|
break;
|
|
|
|
case X86_TYPE_H: /* For AVX, VEX.vvvv selects an XMM/YMM register */
|
|
if ((s->prefix & PREFIX_VEX)) {
|
|
op->unit = X86_OP_SSE;
|
|
op->n = s->vex_v;
|
|
break;
|
|
}
|
|
if (op == &decode->op[0]) {
|
|
/* shifts place the destination in VEX.vvvv, use modrm */
|
|
return decode_op(s, env, decode, op, decode->e.op1, b);
|
|
} else {
|
|
return decode_op(s, env, decode, op, decode->e.op0, b);
|
|
}
|
|
|
|
case X86_TYPE_I: /* Immediate */
|
|
op->unit = X86_OP_IMM;
|
|
decode->immediate = insn_get_signed(env, s, op->ot);
|
|
break;
|
|
|
|
case X86_TYPE_J: /* Relative offset for a jump */
|
|
op->unit = X86_OP_IMM;
|
|
decode->immediate = insn_get_signed(env, s, op->ot);
|
|
decode->immediate += s->pc - s->cs_base;
|
|
if (s->dflag == MO_16) {
|
|
decode->immediate &= 0xffff;
|
|
} else if (!CODE64(s)) {
|
|
decode->immediate &= 0xffffffffu;
|
|
}
|
|
break;
|
|
|
|
case X86_TYPE_L: /* The upper 4 bits of the immediate select a 128-bit register */
|
|
op->n = insn_get(env, s, op->ot) >> 4;
|
|
break;
|
|
|
|
case X86_TYPE_X: /* string source */
|
|
op->n = -1;
|
|
decode->mem = (AddressParts) {
|
|
.def_seg = R_DS,
|
|
.base = R_ESI,
|
|
.index = -1,
|
|
};
|
|
break;
|
|
|
|
case X86_TYPE_Y: /* string destination */
|
|
op->n = -1;
|
|
decode->mem = (AddressParts) {
|
|
.def_seg = R_ES,
|
|
.base = R_EDI,
|
|
.index = -1,
|
|
};
|
|
break;
|
|
|
|
case X86_TYPE_2op:
|
|
*op = decode->op[0];
|
|
break;
|
|
|
|
case X86_TYPE_LoBits:
|
|
op->n = (b & 7) | REX_B(s);
|
|
op->unit = X86_OP_INT;
|
|
break;
|
|
|
|
case X86_TYPE_0 ... X86_TYPE_7:
|
|
op->n = type - X86_TYPE_0;
|
|
op->unit = X86_OP_INT;
|
|
break;
|
|
|
|
case X86_TYPE_ES ... X86_TYPE_GS:
|
|
op->n = type - X86_TYPE_ES;
|
|
op->unit = X86_OP_SEG;
|
|
break;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool validate_sse_prefix(DisasContext *s, X86OpEntry *e)
|
|
{
|
|
uint16_t sse_prefixes;
|
|
|
|
if (!e->valid_prefix) {
|
|
return true;
|
|
}
|
|
if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
|
|
/* In SSE instructions, 0xF3 and 0xF2 cancel 0x66. */
|
|
s->prefix &= ~PREFIX_DATA;
|
|
}
|
|
|
|
/* Now, either zero or one bit is set in sse_prefixes. */
|
|
sse_prefixes = s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
|
|
return e->valid_prefix & (1 << sse_prefixes);
|
|
}
|
|
|
|
static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_func,
|
|
X86DecodedInsn *decode)
|
|
{
|
|
X86OpEntry *e = &decode->e;
|
|
|
|
decode_func(s, env, e, &decode->b);
|
|
while (e->is_decode) {
|
|
e->is_decode = false;
|
|
e->decode(s, env, e, &decode->b);
|
|
}
|
|
|
|
if (!validate_sse_prefix(s, e)) {
|
|
return false;
|
|
}
|
|
|
|
/* First compute size of operands in order to initialize s->rip_offset. */
|
|
if (e->op0 != X86_TYPE_None) {
|
|
if (!decode_op_size(s, e, e->s0, &decode->op[0].ot)) {
|
|
return false;
|
|
}
|
|
if (e->op0 == X86_TYPE_I) {
|
|
s->rip_offset += 1 << decode->op[0].ot;
|
|
}
|
|
}
|
|
if (e->op1 != X86_TYPE_None) {
|
|
if (!decode_op_size(s, e, e->s1, &decode->op[1].ot)) {
|
|
return false;
|
|
}
|
|
if (e->op1 == X86_TYPE_I) {
|
|
s->rip_offset += 1 << decode->op[1].ot;
|
|
}
|
|
}
|
|
if (e->op2 != X86_TYPE_None) {
|
|
if (!decode_op_size(s, e, e->s2, &decode->op[2].ot)) {
|
|
return false;
|
|
}
|
|
if (e->op2 == X86_TYPE_I) {
|
|
s->rip_offset += 1 << decode->op[2].ot;
|
|
}
|
|
}
|
|
if (e->op3 != X86_TYPE_None) {
|
|
/*
|
|
* A couple instructions actually use the extra immediate byte for an Lx
|
|
* register operand; those are handled in the gen_* functions as one off.
|
|
*/
|
|
assert(e->op3 == X86_TYPE_I && e->s3 == X86_SIZE_b);
|
|
s->rip_offset += 1;
|
|
}
|
|
|
|
if (e->op0 != X86_TYPE_None &&
|
|
!decode_op(s, env, decode, &decode->op[0], e->op0, decode->b)) {
|
|
return false;
|
|
}
|
|
|
|
if (e->op1 != X86_TYPE_None &&
|
|
!decode_op(s, env, decode, &decode->op[1], e->op1, decode->b)) {
|
|
return false;
|
|
}
|
|
|
|
if (e->op2 != X86_TYPE_None &&
|
|
!decode_op(s, env, decode, &decode->op[2], e->op2, decode->b)) {
|
|
return false;
|
|
}
|
|
|
|
if (e->op3 != X86_TYPE_None) {
|
|
decode->immediate = insn_get_signed(env, s, MO_8);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool has_cpuid_feature(DisasContext *s, X86CPUIDFeature cpuid)
|
|
{
|
|
switch (cpuid) {
|
|
case X86_FEAT_None:
|
|
return true;
|
|
case X86_FEAT_F16C:
|
|
return (s->cpuid_ext_features & CPUID_EXT_F16C);
|
|
case X86_FEAT_FMA:
|
|
return (s->cpuid_ext_features & CPUID_EXT_FMA);
|
|
case X86_FEAT_MOVBE:
|
|
return (s->cpuid_ext_features & CPUID_EXT_MOVBE);
|
|
case X86_FEAT_PCLMULQDQ:
|
|
return (s->cpuid_ext_features & CPUID_EXT_PCLMULQDQ);
|
|
case X86_FEAT_SSE:
|
|
return (s->cpuid_ext_features & CPUID_SSE);
|
|
case X86_FEAT_SSE2:
|
|
return (s->cpuid_ext_features & CPUID_SSE2);
|
|
case X86_FEAT_SSE3:
|
|
return (s->cpuid_ext_features & CPUID_EXT_SSE3);
|
|
case X86_FEAT_SSSE3:
|
|
return (s->cpuid_ext_features & CPUID_EXT_SSSE3);
|
|
case X86_FEAT_SSE41:
|
|
return (s->cpuid_ext_features & CPUID_EXT_SSE41);
|
|
case X86_FEAT_SSE42:
|
|
return (s->cpuid_ext_features & CPUID_EXT_SSE42);
|
|
case X86_FEAT_AES:
|
|
if (!(s->cpuid_ext_features & CPUID_EXT_AES)) {
|
|
return false;
|
|
} else if (!(s->prefix & PREFIX_VEX)) {
|
|
return true;
|
|
} else if (!(s->cpuid_ext_features & CPUID_EXT_AVX)) {
|
|
return false;
|
|
} else {
|
|
return !s->vex_l || (s->cpuid_7_0_ecx_features & CPUID_7_0_ECX_VAES);
|
|
}
|
|
|
|
case X86_FEAT_AVX:
|
|
return (s->cpuid_ext_features & CPUID_EXT_AVX);
|
|
|
|
case X86_FEAT_3DNOW:
|
|
return (s->cpuid_ext2_features & CPUID_EXT2_3DNOW);
|
|
case X86_FEAT_SSE4A:
|
|
return (s->cpuid_ext3_features & CPUID_EXT3_SSE4A);
|
|
|
|
case X86_FEAT_ADX:
|
|
return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX);
|
|
case X86_FEAT_BMI1:
|
|
return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI1);
|
|
case X86_FEAT_BMI2:
|
|
return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2);
|
|
case X86_FEAT_AVX2:
|
|
return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_AVX2);
|
|
}
|
|
g_assert_not_reached();
|
|
}
|
|
|
|
static bool validate_vex(DisasContext *s, X86DecodedInsn *decode)
|
|
{
|
|
X86OpEntry *e = &decode->e;
|
|
|
|
switch (e->vex_special) {
|
|
case X86_VEX_REPScalar:
|
|
/*
|
|
* Instructions which differ between 00/66 and F2/F3 in the
|
|
* exception classification and the size of the memory operand.
|
|
*/
|
|
assert(e->vex_class == 1 || e->vex_class == 2);
|
|
if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
|
|
e->vex_class = 3;
|
|
if (s->vex_l) {
|
|
goto illegal;
|
|
}
|
|
assert(decode->e.s2 == X86_SIZE_x);
|
|
if (decode->op[2].has_ea) {
|
|
decode->op[2].ot = s->prefix & PREFIX_REPZ ? MO_32 : MO_64;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case X86_VEX_SSEUnaligned:
|
|
/* handled in sse_needs_alignment. */
|
|
break;
|
|
|
|
case X86_VEX_AVX2_256:
|
|
if ((s->prefix & PREFIX_VEX) && s->vex_l && !has_cpuid_feature(s, X86_FEAT_AVX2)) {
|
|
goto illegal;
|
|
}
|
|
}
|
|
|
|
/* TODO: instructions that require VEX.W=0 (Table 2-16) */
|
|
|
|
switch (e->vex_class) {
|
|
case 0:
|
|
if (s->prefix & PREFIX_VEX) {
|
|
goto illegal;
|
|
}
|
|
return true;
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
case 4:
|
|
case 5:
|
|
case 7:
|
|
if (s->prefix & PREFIX_VEX) {
|
|
if (!(s->flags & HF_AVX_EN_MASK)) {
|
|
goto illegal;
|
|
}
|
|
} else if (e->special != X86_SPECIAL_MMX ||
|
|
(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) {
|
|
if (!(s->flags & HF_OSFXSR_MASK)) {
|
|
goto illegal;
|
|
}
|
|
}
|
|
break;
|
|
case 12:
|
|
/* Must have a VSIB byte and no address prefix. */
|
|
assert(s->has_modrm);
|
|
if ((s->modrm & 7) != 4 || s->aflag == MO_16) {
|
|
goto illegal;
|
|
}
|
|
|
|
/* Check no overlap between registers. */
|
|
if (!decode->op[0].has_ea &&
|
|
(decode->op[0].n == decode->mem.index || decode->op[0].n == decode->op[1].n)) {
|
|
goto illegal;
|
|
}
|
|
assert(!decode->op[1].has_ea);
|
|
if (decode->op[1].n == decode->mem.index) {
|
|
goto illegal;
|
|
}
|
|
if (!decode->op[2].has_ea &&
|
|
(decode->op[2].n == decode->mem.index || decode->op[2].n == decode->op[1].n)) {
|
|
goto illegal;
|
|
}
|
|
/* fall through */
|
|
case 6:
|
|
case 11:
|
|
if (!(s->prefix & PREFIX_VEX)) {
|
|
goto illegal;
|
|
}
|
|
if (!(s->flags & HF_AVX_EN_MASK)) {
|
|
goto illegal;
|
|
}
|
|
break;
|
|
case 8:
|
|
/* Non-VEX case handled in decode_0F77. */
|
|
assert(s->prefix & PREFIX_VEX);
|
|
if (!(s->flags & HF_AVX_EN_MASK)) {
|
|
goto illegal;
|
|
}
|
|
break;
|
|
case 13:
|
|
if (!(s->prefix & PREFIX_VEX)) {
|
|
goto illegal;
|
|
}
|
|
if (s->vex_l) {
|
|
goto illegal;
|
|
}
|
|
/* All integer instructions use VEX.vvvv, so exit. */
|
|
return true;
|
|
}
|
|
|
|
if (s->vex_v != 0 &&
|
|
e->op0 != X86_TYPE_H && e->op0 != X86_TYPE_B &&
|
|
e->op1 != X86_TYPE_H && e->op1 != X86_TYPE_B &&
|
|
e->op2 != X86_TYPE_H && e->op2 != X86_TYPE_B) {
|
|
goto illegal;
|
|
}
|
|
|
|
if (s->flags & HF_TS_MASK) {
|
|
goto nm_exception;
|
|
}
|
|
if (s->flags & HF_EM_MASK) {
|
|
goto illegal;
|
|
}
|
|
return true;
|
|
|
|
nm_exception:
|
|
gen_NM_exception(s);
|
|
return false;
|
|
illegal:
|
|
gen_illegal_opcode(s);
|
|
return false;
|
|
}
|
|
|
|
static void decode_temp_free(X86DecodedOp *op)
|
|
{
|
|
if (op->v_ptr) {
|
|
tcg_temp_free_ptr(op->v_ptr);
|
|
}
|
|
}
|
|
|
|
static void decode_temps_free(X86DecodedInsn *decode)
|
|
{
|
|
decode_temp_free(&decode->op[0]);
|
|
decode_temp_free(&decode->op[1]);
|
|
decode_temp_free(&decode->op[2]);
|
|
}
|
|
|
|
/*
|
|
* Convert one instruction. s->base.is_jmp is set if the translation must
|
|
* be stopped.
|
|
*/
|
|
static void disas_insn_new(DisasContext *s, CPUState *cpu, int b)
|
|
{
|
|
CPUX86State *env = cpu->env_ptr;
|
|
bool first = true;
|
|
X86DecodedInsn decode;
|
|
X86DecodeFunc decode_func = decode_root;
|
|
|
|
s->has_modrm = false;
|
|
|
|
next_byte:
|
|
if (first) {
|
|
first = false;
|
|
} else {
|
|
b = x86_ldub_code(env, s);
|
|
}
|
|
/* Collect prefixes. */
|
|
switch (b) {
|
|
case 0xf3:
|
|
s->prefix |= PREFIX_REPZ;
|
|
s->prefix &= ~PREFIX_REPNZ;
|
|
goto next_byte;
|
|
case 0xf2:
|
|
s->prefix |= PREFIX_REPNZ;
|
|
s->prefix &= ~PREFIX_REPZ;
|
|
goto next_byte;
|
|
case 0xf0:
|
|
s->prefix |= PREFIX_LOCK;
|
|
goto next_byte;
|
|
case 0x2e:
|
|
s->override = R_CS;
|
|
goto next_byte;
|
|
case 0x36:
|
|
s->override = R_SS;
|
|
goto next_byte;
|
|
case 0x3e:
|
|
s->override = R_DS;
|
|
goto next_byte;
|
|
case 0x26:
|
|
s->override = R_ES;
|
|
goto next_byte;
|
|
case 0x64:
|
|
s->override = R_FS;
|
|
goto next_byte;
|
|
case 0x65:
|
|
s->override = R_GS;
|
|
goto next_byte;
|
|
case 0x66:
|
|
s->prefix |= PREFIX_DATA;
|
|
goto next_byte;
|
|
case 0x67:
|
|
s->prefix |= PREFIX_ADR;
|
|
goto next_byte;
|
|
#ifdef TARGET_X86_64
|
|
case 0x40 ... 0x4f:
|
|
if (CODE64(s)) {
|
|
/* REX prefix */
|
|
s->prefix |= PREFIX_REX;
|
|
s->vex_w = (b >> 3) & 1;
|
|
s->rex_r = (b & 0x4) << 1;
|
|
s->rex_x = (b & 0x2) << 2;
|
|
s->rex_b = (b & 0x1) << 3;
|
|
goto next_byte;
|
|
}
|
|
break;
|
|
#endif
|
|
case 0xc5: /* 2-byte VEX */
|
|
case 0xc4: /* 3-byte VEX */
|
|
/*
|
|
* VEX prefixes cannot be used except in 32-bit mode.
|
|
* Otherwise the instruction is LES or LDS.
|
|
*/
|
|
if (CODE32(s) && !VM86(s)) {
|
|
static const int pp_prefix[4] = {
|
|
0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ
|
|
};
|
|
int vex3, vex2 = x86_ldub_code(env, s);
|
|
|
|
if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) {
|
|
/*
|
|
* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
|
|
* otherwise the instruction is LES or LDS.
|
|
*/
|
|
s->pc--; /* rewind the advance_pc() x86_ldub_code() did */
|
|
break;
|
|
}
|
|
|
|
/* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
|
|
if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ
|
|
| PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) {
|
|
goto illegal_op;
|
|
}
|
|
#ifdef TARGET_X86_64
|
|
s->rex_r = (~vex2 >> 4) & 8;
|
|
#endif
|
|
if (b == 0xc5) {
|
|
/* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */
|
|
vex3 = vex2;
|
|
decode_func = decode_0F;
|
|
} else {
|
|
/* 3-byte VEX prefix: RXBmmmmm wVVVVlpp */
|
|
vex3 = x86_ldub_code(env, s);
|
|
#ifdef TARGET_X86_64
|
|
s->rex_x = (~vex2 >> 3) & 8;
|
|
s->rex_b = (~vex2 >> 2) & 8;
|
|
#endif
|
|
s->vex_w = (vex3 >> 7) & 1;
|
|
switch (vex2 & 0x1f) {
|
|
case 0x01: /* Implied 0f leading opcode bytes. */
|
|
decode_func = decode_0F;
|
|
break;
|
|
case 0x02: /* Implied 0f 38 leading opcode bytes. */
|
|
decode_func = decode_0F38;
|
|
break;
|
|
case 0x03: /* Implied 0f 3a leading opcode bytes. */
|
|
decode_func = decode_0F3A;
|
|
break;
|
|
default: /* Reserved for future use. */
|
|
goto unknown_op;
|
|
}
|
|
}
|
|
s->vex_v = (~vex3 >> 3) & 0xf;
|
|
s->vex_l = (vex3 >> 2) & 1;
|
|
s->prefix |= pp_prefix[vex3 & 3] | PREFIX_VEX;
|
|
}
|
|
break;
|
|
default:
|
|
if (b >= 0x100) {
|
|
b -= 0x100;
|
|
decode_func = do_decode_0F;
|
|
}
|
|
break;
|
|
}
|
|
|
|
/* Post-process prefixes. */
|
|
if (CODE64(s)) {
|
|
/*
|
|
* In 64-bit mode, the default data size is 32-bit. Select 64-bit
|
|
* data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
|
|
* over 0x66 if both are present.
|
|
*/
|
|
s->dflag = (REX_W(s) ? MO_64 : s->prefix & PREFIX_DATA ? MO_16 : MO_32);
|
|
/* In 64-bit mode, 0x67 selects 32-bit addressing. */
|
|
s->aflag = (s->prefix & PREFIX_ADR ? MO_32 : MO_64);
|
|
} else {
|
|
/* In 16/32-bit mode, 0x66 selects the opposite data size. */
|
|
if (CODE32(s) ^ ((s->prefix & PREFIX_DATA) != 0)) {
|
|
s->dflag = MO_32;
|
|
} else {
|
|
s->dflag = MO_16;
|
|
}
|
|
/* In 16/32-bit mode, 0x67 selects the opposite addressing. */
|
|
if (CODE32(s) ^ ((s->prefix & PREFIX_ADR) != 0)) {
|
|
s->aflag = MO_32;
|
|
} else {
|
|
s->aflag = MO_16;
|
|
}
|
|
}
|
|
|
|
memset(&decode, 0, sizeof(decode));
|
|
decode.b = b;
|
|
if (!decode_insn(s, env, decode_func, &decode)) {
|
|
goto illegal_op;
|
|
}
|
|
if (!decode.e.gen) {
|
|
goto unknown_op;
|
|
}
|
|
|
|
if (!has_cpuid_feature(s, decode.e.cpuid)) {
|
|
goto illegal_op;
|
|
}
|
|
|
|
switch (decode.e.special) {
|
|
case X86_SPECIAL_None:
|
|
break;
|
|
|
|
case X86_SPECIAL_Locked:
|
|
if (decode.op[0].has_ea) {
|
|
s->prefix |= PREFIX_LOCK;
|
|
}
|
|
break;
|
|
|
|
case X86_SPECIAL_ProtMode:
|
|
if (!PE(s) || VM86(s)) {
|
|
goto illegal_op;
|
|
}
|
|
break;
|
|
|
|
case X86_SPECIAL_i64:
|
|
if (CODE64(s)) {
|
|
goto illegal_op;
|
|
}
|
|
break;
|
|
case X86_SPECIAL_o64:
|
|
if (!CODE64(s)) {
|
|
goto illegal_op;
|
|
}
|
|
break;
|
|
|
|
case X86_SPECIAL_ZExtOp0:
|
|
assert(decode.op[0].unit == X86_OP_INT);
|
|
if (!decode.op[0].has_ea) {
|
|
decode.op[0].ot = MO_32;
|
|
}
|
|
break;
|
|
|
|
case X86_SPECIAL_ZExtOp2:
|
|
assert(decode.op[2].unit == X86_OP_INT);
|
|
if (!decode.op[2].has_ea) {
|
|
decode.op[2].ot = MO_32;
|
|
}
|
|
break;
|
|
|
|
case X86_SPECIAL_AVXExtMov:
|
|
if (!decode.op[2].has_ea) {
|
|
decode.op[2].ot = s->vex_l ? MO_256 : MO_128;
|
|
} else if (s->vex_l) {
|
|
decode.op[2].ot++;
|
|
}
|
|
break;
|
|
|
|
case X86_SPECIAL_MMX:
|
|
if (!(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) {
|
|
gen_helper_enter_mmx(cpu_env);
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (!validate_vex(s, &decode)) {
|
|
return;
|
|
}
|
|
if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea) {
|
|
gen_load_ea(s, &decode.mem, decode.e.vex_class == 12);
|
|
}
|
|
if (s->prefix & PREFIX_LOCK) {
|
|
if (decode.op[0].unit != X86_OP_INT || !decode.op[0].has_ea) {
|
|
goto illegal_op;
|
|
}
|
|
gen_load(s, &decode, 2, s->T1);
|
|
decode.e.gen(s, env, &decode);
|
|
} else {
|
|
if (decode.op[0].unit == X86_OP_MMX) {
|
|
compute_mmx_offset(&decode.op[0]);
|
|
} else if (decode.op[0].unit == X86_OP_SSE) {
|
|
compute_xmm_offset(&decode.op[0]);
|
|
}
|
|
gen_load(s, &decode, 1, s->T0);
|
|
gen_load(s, &decode, 2, s->T1);
|
|
decode.e.gen(s, env, &decode);
|
|
gen_writeback(s, &decode, 0, s->T0);
|
|
}
|
|
decode_temps_free(&decode);
|
|
return;
|
|
illegal_op:
|
|
gen_illegal_opcode(s);
|
|
return;
|
|
unknown_op:
|
|
gen_unknown_opcode(env, s);
|
|
}
|