David Venhoff
cfcea9ee67
Based off b80915eb99
and compacted into a single commit so that it will fit on the uni git server
26 lines
655 B
Plaintext
26 lines
655 B
Plaintext
MediaTek PCIESYS controller
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============================
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The MediaTek PCIESYS controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be:
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- "mediatek,mt7622-pciesys", "syscon"
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- "mediatek,mt7629-pciesys", "syscon"
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- #clock-cells: Must be 1
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- #reset-cells: Must be 1
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The PCIESYS controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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pciesys: pciesys@1a100800 {
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compatible = "mediatek,mt7622-pciesys", "syscon";
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reg = <0 0x1a100800 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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