David Venhoff
cfcea9ee67
Based off b80915eb99
and compacted into a single commit so that it will fit on the uni git server
87 lines
2.0 KiB
YAML
87 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Serial NOR flash controller for MediaTek ARM SoCs
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maintainers:
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- Bayi Cheng <bayi.cheng@mediatek.com>
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- Chuanhong Guo <gch981213@gmail.com>
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description: |
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This spi controller support single, dual, or quad mode transfer for
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SPI NOR flash. There should be only one spi slave device following
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generic spi bindings. It's not recommended to use this controller
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for devices other than SPI NOR flash due to limited transfer
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capability of this controller.
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allOf:
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- $ref: /spi/spi-controller.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- mediatek,mt2701-nor
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- mediatek,mt2712-nor
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- mediatek,mt7622-nor
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- mediatek,mt7623-nor
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- mediatek,mt7629-nor
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- mediatek,mt8192-nor
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- enum:
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- mediatek,mt8173-nor
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- items:
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- const: mediatek,mt8173-nor
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: clock used for spi bus
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- description: clock used for controller
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clock-names:
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items:
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- const: spi
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- const: sf
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8173-clk.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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nor_flash: spi@1100d000 {
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compatible = "mediatek,mt8173-nor";
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reg = <0 0x1100d000 0 0xe0>;
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interrupts = <&spi_flash_irq>;
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clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
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clock-names = "spi", "sf";
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#address-cells = <1>;
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#size-cells = <0>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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};
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};
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};
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