target/arm: Implement SVE Predicate Misc Group
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
516e246a1a
commit
028e2a7b87
@ -540,6 +540,7 @@ typedef struct CPUARMState {
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#ifdef TARGET_AARCH64
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/* Store FFR as pregs[16] to make it easier to treat as any other. */
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#define FFR_PRED_NUM 16
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ARMPredicateReg pregs[17];
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/* Scratch space for aa64 sve predicate temporary. */
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ARMPredicateReg preg_tmp;
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@ -2975,4 +2976,7 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
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return &env->vfp.zregs[regno].d[0];
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}
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/* Shared between translate-sve.c and sve_helper.c. */
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extern const uint64_t pred_esz_masks[4];
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#endif
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@ -20,6 +20,9 @@
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DEF_HELPER_FLAGS_2(sve_predtest1, TCG_CALL_NO_WG, i32, i64, i64)
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DEF_HELPER_FLAGS_3(sve_predtest, TCG_CALL_NO_WG, i32, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_pfirst, TCG_CALL_NO_WG, i32, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_pnext, TCG_CALL_NO_WG, i32, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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@ -29,6 +29,7 @@
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# when creating helpers common to those for the individual
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# instruction patterns.
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&rr_esz rd rn esz
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&rri rd rn imm
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&rrr_esz rd rn rm esz
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&rprr_s rd pg rn rm s
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@ -37,6 +38,12 @@
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# Named instruction formats. These are generally used to
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# reduce the amount of duplication between instruction patterns.
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# Two operand with unused vector element size
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@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
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# Two operand
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@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
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# Three operand with unused vector element size
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@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
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@ -77,6 +84,30 @@ NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
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# SVE predicate test
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PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
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# SVE predicate initialize
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PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
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# SVE initialize FFR
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SETFFR 00100101 0010 1100 1001 0000 0000 0000
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# SVE zero predicate register
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PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
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# SVE predicate read from FFR (predicated)
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RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
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# SVE predicate read from FFR (unpredicated)
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RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
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# SVE FFR write from predicate (WRFFR)
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WRFFR 00100101 0010 1000 1001 000 rn:4 00000
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# SVE predicate first active
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PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
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# SVE predicate next active
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PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
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### SVE Memory - 32-bit Gather and Unsized Contiguous Group
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# SVE load predicate register
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@ -115,3 +115,87 @@ LOGICAL_PPPP(sve_nand_pppp, DO_NAND)
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#undef DO_NAND
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#undef DO_SEL
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#undef LOGICAL_PPPP
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/* Similar to the ARM LastActiveElement pseudocode function, except the
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result is multiplied by the element size. This includes the not found
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indication; e.g. not found for esz=3 is -8. */
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static intptr_t last_active_element(uint64_t *g, intptr_t words, intptr_t esz)
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{
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uint64_t mask = pred_esz_masks[esz];
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intptr_t i = words;
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do {
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uint64_t this_g = g[--i] & mask;
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if (this_g) {
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return i * 64 + (63 - clz64(this_g));
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}
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} while (i > 0);
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return (intptr_t)-1 << esz;
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}
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uint32_t HELPER(sve_pfirst)(void *vd, void *vg, uint32_t words)
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{
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uint32_t flags = PREDTEST_INIT;
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uint64_t *d = vd, *g = vg;
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intptr_t i = 0;
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do {
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uint64_t this_d = d[i];
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uint64_t this_g = g[i];
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if (this_g) {
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if (!(flags & 4)) {
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/* Set in D the first bit of G. */
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this_d |= this_g & -this_g;
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d[i] = this_d;
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}
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flags = iter_predtest_fwd(this_d, this_g, flags);
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}
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} while (++i < words);
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return flags;
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}
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uint32_t HELPER(sve_pnext)(void *vd, void *vg, uint32_t pred_desc)
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{
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intptr_t words = extract32(pred_desc, 0, SIMD_OPRSZ_BITS);
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intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
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uint32_t flags = PREDTEST_INIT;
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uint64_t *d = vd, *g = vg, esz_mask;
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intptr_t i, next;
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next = last_active_element(vd, words, esz) + (1 << esz);
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esz_mask = pred_esz_masks[esz];
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/* Similar to the pseudocode for pnext, but scaled by ESZ
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so that we find the correct bit. */
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if (next < words * 64) {
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uint64_t mask = -1;
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if (next & 63) {
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mask = ~((1ull << (next & 63)) - 1);
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next &= -64;
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}
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do {
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uint64_t this_g = g[next / 64] & esz_mask & mask;
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if (this_g != 0) {
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next = (next & -64) + ctz64(this_g);
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break;
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}
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next += 64;
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mask = -1;
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} while (next < words * 64);
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}
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i = 0;
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do {
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uint64_t this_d = 0;
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if (i == next / 64) {
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this_d = 1ull << (next & 63);
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}
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d[i] = this_d;
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flags = iter_predtest_fwd(this_d, g[i] & esz_mask, flags);
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} while (++i < words);
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return flags;
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}
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@ -22,6 +22,7 @@
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#include "exec/exec-all.h"
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#include "tcg-op.h"
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#include "tcg-op-gvec.h"
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#include "tcg-gvec-desc.h"
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#include "qemu/log.h"
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#include "arm_ldst.h"
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#include "translate.h"
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@ -192,6 +193,12 @@ static void do_predtest(DisasContext *s, int dofs, int gofs, int words)
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tcg_temp_free_i32(t);
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}
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/* For each element size, the bits within a predicate word that are active. */
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const uint64_t pred_esz_masks[4] = {
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0xffffffffffffffffull, 0x5555555555555555ull,
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0x1111111111111111ull, 0x0101010101010101ull
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};
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/*
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*** SVE Logical - Unpredicated Group
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*/
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@ -541,6 +548,208 @@ static bool trans_PTEST(DisasContext *s, arg_PTEST *a, uint32_t insn)
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return true;
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}
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/* See the ARM pseudocode DecodePredCount. */
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static unsigned decode_pred_count(unsigned fullsz, int pattern, int esz)
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{
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unsigned elements = fullsz >> esz;
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unsigned bound;
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switch (pattern) {
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case 0x0: /* POW2 */
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return pow2floor(elements);
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case 0x1: /* VL1 */
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case 0x2: /* VL2 */
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case 0x3: /* VL3 */
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case 0x4: /* VL4 */
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case 0x5: /* VL5 */
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case 0x6: /* VL6 */
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case 0x7: /* VL7 */
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case 0x8: /* VL8 */
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bound = pattern;
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break;
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case 0x9: /* VL16 */
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case 0xa: /* VL32 */
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case 0xb: /* VL64 */
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case 0xc: /* VL128 */
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case 0xd: /* VL256 */
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bound = 16 << (pattern - 9);
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break;
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case 0x1d: /* MUL4 */
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return elements - elements % 4;
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case 0x1e: /* MUL3 */
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return elements - elements % 3;
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case 0x1f: /* ALL */
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return elements;
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default: /* #uimm5 */
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return 0;
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}
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return elements >= bound ? bound : 0;
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}
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/* This handles all of the predicate initialization instructions,
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* PTRUE, PFALSE, SETFFR. For PFALSE, we will have set PAT == 32
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* so that decode_pred_count returns 0. For SETFFR, we will have
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* set RD == 16 == FFR.
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*/
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static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
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{
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if (!sve_access_check(s)) {
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return true;
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}
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unsigned fullsz = vec_full_reg_size(s);
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unsigned ofs = pred_full_reg_offset(s, rd);
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unsigned numelem, setsz, i;
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uint64_t word, lastword;
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TCGv_i64 t;
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numelem = decode_pred_count(fullsz, pat, esz);
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/* Determine what we must store into each bit, and how many. */
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if (numelem == 0) {
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lastword = word = 0;
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setsz = fullsz;
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} else {
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setsz = numelem << esz;
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lastword = word = pred_esz_masks[esz];
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if (setsz % 64) {
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lastword &= ~(-1ull << (setsz % 64));
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}
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}
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t = tcg_temp_new_i64();
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if (fullsz <= 64) {
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tcg_gen_movi_i64(t, lastword);
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tcg_gen_st_i64(t, cpu_env, ofs);
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goto done;
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}
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if (word == lastword) {
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unsigned maxsz = size_for_gvec(fullsz / 8);
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unsigned oprsz = size_for_gvec(setsz / 8);
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if (oprsz * 8 == setsz) {
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tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
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goto done;
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}
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if (oprsz * 8 == setsz + 8) {
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tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
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tcg_gen_movi_i64(t, 0);
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tcg_gen_st_i64(t, cpu_env, ofs + oprsz - 8);
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goto done;
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}
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}
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setsz /= 8;
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fullsz /= 8;
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tcg_gen_movi_i64(t, word);
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for (i = 0; i < setsz; i += 8) {
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tcg_gen_st_i64(t, cpu_env, ofs + i);
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}
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if (lastword != word) {
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tcg_gen_movi_i64(t, lastword);
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tcg_gen_st_i64(t, cpu_env, ofs + i);
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i += 8;
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}
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if (i < fullsz) {
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tcg_gen_movi_i64(t, 0);
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for (; i < fullsz; i += 8) {
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tcg_gen_st_i64(t, cpu_env, ofs + i);
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}
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}
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done:
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tcg_temp_free_i64(t);
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/* PTRUES */
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if (setflag) {
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tcg_gen_movi_i32(cpu_NF, -(word != 0));
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tcg_gen_movi_i32(cpu_CF, word == 0);
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tcg_gen_movi_i32(cpu_VF, 0);
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tcg_gen_mov_i32(cpu_ZF, cpu_NF);
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}
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return true;
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}
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static bool trans_PTRUE(DisasContext *s, arg_PTRUE *a, uint32_t insn)
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{
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return do_predset(s, a->esz, a->rd, a->pat, a->s);
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}
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static bool trans_SETFFR(DisasContext *s, arg_SETFFR *a, uint32_t insn)
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{
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/* Note pat == 31 is #all, to set all elements. */
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return do_predset(s, 0, FFR_PRED_NUM, 31, false);
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}
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static bool trans_PFALSE(DisasContext *s, arg_PFALSE *a, uint32_t insn)
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{
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/* Note pat == 32 is #unimp, to set no elements. */
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return do_predset(s, 0, a->rd, 32, false);
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}
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static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a, uint32_t insn)
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{
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/* The path through do_pppp_flags is complicated enough to want to avoid
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* duplication. Frob the arguments into the form of a predicated AND.
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*/
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arg_rprr_s alt_a = {
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.rd = a->rd, .pg = a->pg, .s = a->s,
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.rn = FFR_PRED_NUM, .rm = FFR_PRED_NUM,
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};
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return trans_AND_pppp(s, &alt_a, insn);
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}
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static bool trans_RDFFR(DisasContext *s, arg_RDFFR *a, uint32_t insn)
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{
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return do_mov_p(s, a->rd, FFR_PRED_NUM);
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}
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static bool trans_WRFFR(DisasContext *s, arg_WRFFR *a, uint32_t insn)
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{
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return do_mov_p(s, FFR_PRED_NUM, a->rn);
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}
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static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
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void (*gen_fn)(TCGv_i32, TCGv_ptr,
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TCGv_ptr, TCGv_i32))
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{
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if (!sve_access_check(s)) {
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return true;
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}
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TCGv_ptr t_pd = tcg_temp_new_ptr();
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TCGv_ptr t_pg = tcg_temp_new_ptr();
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TCGv_i32 t;
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unsigned desc;
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desc = DIV_ROUND_UP(pred_full_reg_size(s), 8);
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desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz);
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tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd));
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tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn));
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t = tcg_const_i32(desc);
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gen_fn(t, t_pd, t_pg, t);
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tcg_temp_free_ptr(t_pd);
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tcg_temp_free_ptr(t_pg);
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do_pred_flags(t);
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tcg_temp_free_i32(t);
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return true;
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}
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static bool trans_PFIRST(DisasContext *s, arg_rr_esz *a, uint32_t insn)
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{
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return do_pfirst_pnext(s, a, gen_helper_sve_pfirst);
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}
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static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a, uint32_t insn)
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{
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return do_pfirst_pnext(s, a, gen_helper_sve_pnext);
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}
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/*
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*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
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*/
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