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net/ftgmac100: add a 'aspeed' property

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The Aspeed SoCs have a different definition of the end of the ring
buffer bit. Add a property to specify which set of bits should be used
by the NIC.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
This commit is contained in:
Cédric Le Goater 2017-04-14 10:35:01 +02:00 committed by Jason Wang
parent bd44300d1a
commit 1335fe3eb2
2 changed files with 19 additions and 2 deletions
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17
hw/net/ftgmac100.c
View File

@ -126,6 +126,7 @@
#define FTGMAC100_TXDES0_CRC_ERR (1 << 19) #define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
#define FTGMAC100_TXDES0_LTS (1 << 28) #define FTGMAC100_TXDES0_LTS (1 << 28)
#define FTGMAC100_TXDES0_FTS (1 << 29) #define FTGMAC100_TXDES0_FTS (1 << 29)
#define FTGMAC100_TXDES0_EDOTR_ASPEED (1 << 30)
#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) #define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
@ -154,6 +155,7 @@
#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) #define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
#define FTGMAC100_RXDES0_LRS (1 << 28) #define FTGMAC100_RXDES0_LRS (1 << 28)
#define FTGMAC100_RXDES0_FRS (1 << 29) #define FTGMAC100_RXDES0_FRS (1 << 29)
#define FTGMAC100_RXDES0_EDORR_ASPEED (1 << 30)
#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) #define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
@ -462,7 +464,7 @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
/* Write back the modified descriptor. */ /* Write back the modified descriptor. */
ftgmac100_write_bd(&bd, addr); ftgmac100_write_bd(&bd, addr);
/* Advance to the next descriptor. */ /* Advance to the next descriptor. */
if (bd.des0 & FTGMAC100_TXDES0_EDOTR) { if (bd.des0 & s->txdes0_edotr) {
addr = tx_ring; addr = tx_ring;
} else { } else {
addr += sizeof(FTGMAC100Desc); addr += sizeof(FTGMAC100Desc);
@ -880,7 +882,7 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
s->isr |= FTGMAC100_INT_RPKT_FIFO; s->isr |= FTGMAC100_INT_RPKT_FIFO;
} }
ftgmac100_write_bd(&bd, addr); ftgmac100_write_bd(&bd, addr);
if (bd.des0 & FTGMAC100_RXDES0_EDORR) { if (bd.des0 & s->rxdes0_edorr) {
addr = s->rx_ring; addr = s->rx_ring;
} else { } else {
addr += sizeof(FTGMAC100Desc); addr += sizeof(FTGMAC100Desc);
@ -921,6 +923,14 @@ static void ftgmac100_realize(DeviceState *dev, Error **errp)
FTGMAC100State *s = FTGMAC100(dev); FTGMAC100State *s = FTGMAC100(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
if (s->aspeed) {
s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR_ASPEED;
s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR_ASPEED;
} else {
s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR;
s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR;
}
memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s, memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s,
TYPE_FTGMAC100, 0x2000); TYPE_FTGMAC100, 0x2000);
sysbus_init_mmio(sbd, &s->iomem); sysbus_init_mmio(sbd, &s->iomem);
@ -967,11 +977,14 @@ static const VMStateDescription vmstate_ftgmac100 = {
VMSTATE_UINT32(phy_advertise, FTGMAC100State), VMSTATE_UINT32(phy_advertise, FTGMAC100State),
VMSTATE_UINT32(phy_int, FTGMAC100State), VMSTATE_UINT32(phy_int, FTGMAC100State),
VMSTATE_UINT32(phy_int_mask, FTGMAC100State), VMSTATE_UINT32(phy_int_mask, FTGMAC100State),
VMSTATE_UINT32(txdes0_edotr, FTGMAC100State),
VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
static Property ftgmac100_properties[] = { static Property ftgmac100_properties[] = {
DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false),
DEFINE_NIC_PROPERTIES(FTGMAC100State, conf), DEFINE_NIC_PROPERTIES(FTGMAC100State, conf),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };

4
include/hw/net/ftgmac100.h
View File

@ -55,6 +55,10 @@ typedef struct FTGMAC100State {
uint32_t phy_advertise; uint32_t phy_advertise;
uint32_t phy_int; uint32_t phy_int;
uint32_t phy_int_mask; uint32_t phy_int_mask;
bool aspeed;
uint32_t txdes0_edotr;
uint32_t rxdes0_edorr;
} FTGMAC100State; } FTGMAC100State;
#endif #endif