target/ppc: Remove POWERPC_EXCP_STCX
Always use the gen_conditional_store implementation that uses atomic_cmpxchg. Make sure and clear reserve_addr across most interrupts crossing the cpu_loop. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Richard Henderson
David Gibson
parent
4a9b3c5dd3
commit
14db18997e
@ -65,99 +65,23 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
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return -1;
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}
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static int do_store_exclusive(CPUPPCState *env)
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{
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target_ulong addr;
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target_ulong page_addr;
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target_ulong val, val2 __attribute__((unused)) = 0;
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int flags;
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int segv = 0;
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addr = env->reserve_ea;
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page_addr = addr & TARGET_PAGE_MASK;
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start_exclusive();
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mmap_lock();
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flags = page_get_flags(page_addr);
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if ((flags & PAGE_READ) == 0) {
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segv = 1;
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} else {
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int reg = env->reserve_info & 0x1f;
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int size = env->reserve_info >> 5;
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int stored = 0;
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if (addr == env->reserve_addr) {
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switch (size) {
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case 1: segv = get_user_u8(val, addr); break;
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case 2: segv = get_user_u16(val, addr); break;
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case 4: segv = get_user_u32(val, addr); break;
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#if defined(TARGET_PPC64)
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case 8: segv = get_user_u64(val, addr); break;
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case 16: {
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segv = get_user_u64(val, addr);
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if (!segv) {
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segv = get_user_u64(val2, addr + 8);
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}
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break;
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}
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#endif
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default: abort();
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}
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if (!segv && val == env->reserve_val) {
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val = env->gpr[reg];
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switch (size) {
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case 1: segv = put_user_u8(val, addr); break;
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case 2: segv = put_user_u16(val, addr); break;
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case 4: segv = put_user_u32(val, addr); break;
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#if defined(TARGET_PPC64)
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case 8: segv = put_user_u64(val, addr); break;
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case 16: {
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if (val2 == env->reserve_val2) {
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if (msr_le) {
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val2 = val;
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val = env->gpr[reg+1];
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} else {
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val2 = env->gpr[reg+1];
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}
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segv = put_user_u64(val, addr);
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if (!segv) {
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segv = put_user_u64(val2, addr + 8);
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}
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}
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break;
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}
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#endif
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default: abort();
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}
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if (!segv) {
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stored = 1;
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}
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}
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}
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env->crf[0] = (stored << 1) | xer_so;
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env->reserve_addr = (target_ulong)-1;
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}
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if (!segv) {
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env->nip += 4;
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}
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mmap_unlock();
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end_exclusive();
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return segv;
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}
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void cpu_loop(CPUPPCState *env)
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{
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CPUState *cs = CPU(ppc_env_get_cpu(env));
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target_siginfo_t info;
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int trapnr;
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int trapnr, sig;
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target_ulong ret;
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for(;;) {
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bool arch_interrupt;
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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process_queued_cpu_work(cs);
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switch(trapnr) {
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arch_interrupt = true;
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switch (trapnr) {
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case POWERPC_EXCP_NONE:
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/* Just go on */
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break;
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@ -524,26 +448,15 @@ void cpu_loop(CPUPPCState *env)
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}
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env->gpr[3] = ret;
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break;
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case POWERPC_EXCP_STCX:
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if (do_store_exclusive(env)) {
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info.si_signo = TARGET_SIGSEGV;
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info.si_errno = 0;
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info.si_code = TARGET_SEGV_MAPERR;
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info._sifields._sigfault._addr = env->nip;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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break;
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case EXCP_DEBUG:
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{
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int sig;
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sig = gdb_handlesig(cs, TARGET_SIGTRAP);
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if (sig) {
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info.si_signo = sig;
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info.si_errno = 0;
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info.si_code = TARGET_TRAP_BRKPT;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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sig = gdb_handlesig(cs, TARGET_SIGTRAP);
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if (sig) {
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info.si_signo = sig;
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info.si_errno = 0;
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info.si_code = TARGET_TRAP_BRKPT;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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} else {
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arch_interrupt = false;
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}
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break;
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case EXCP_INTERRUPT:
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@ -551,12 +464,22 @@ void cpu_loop(CPUPPCState *env)
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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arch_interrupt = false;
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break;
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default:
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cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr);
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break;
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}
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process_pending_signals(env);
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/* Most of the traps imply a transition through kernel mode,
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* which implies an REI instruction has been executed. Which
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* means that RX and LOCK_ADDR should be cleared. But there
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* are a few exceptions for traps internal to QEMU.
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*/
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if (arch_interrupt) {
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env->reserve_addr = -1;
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}
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}
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}
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@ -196,7 +196,6 @@ enum {
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/* QEMU exceptions: special cases we want to stop translation */
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POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
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POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
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POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
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};
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/* Exceptions error codes */
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@ -994,10 +993,6 @@ struct CPUPPCState {
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/* Reservation value */
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target_ulong reserve_val;
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target_ulong reserve_val2;
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/* Reservation store address */
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target_ulong reserve_ea;
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/* Reserved store source register and size */
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target_ulong reserve_info;
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/* Those ones are used in supervisor mode only */
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/* machine state register */
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@ -3201,19 +3201,6 @@ ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
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ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
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#endif
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#if defined(CONFIG_USER_ONLY)
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static void gen_conditional_store(DisasContext *ctx, TCGv EA,
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int reg, int memop)
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{
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TCGv t0 = tcg_temp_new();
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tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
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tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
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tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
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tcg_temp_free(t0);
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gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
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}
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#else
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static void gen_conditional_store(DisasContext *ctx, TCGv EA,
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int reg, int memop)
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{
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@ -3244,7 +3231,6 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA,
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gen_set_label(l2);
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tcg_gen_movi_tl(cpu_reserve, -1);
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}
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#endif
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#define STCX(name, memop) \
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static void gen_##name(DisasContext *ctx) \
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