TriCore bugfixes
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCgAGBQJVUKAAAAoJEArSxjlracoU0WgP/Rsuv9C9EL4891vJbQPIyEAu Jzho25gx0b9XOnBn6bjTYXf8F5Laiqep7bakOLBp6vctnxY8TyMvwfVJ3vYXr9FD SvEJGUjz2ylQ+xxxp3FpeNylLf1Feplvow9sh9/jktf0KeCtUPmXxhEs9C1tUhdC 75KhYwzAtFp9fhmqyHqgVoCuZweXYt1PbOMx0vIGuLB1BaWwh/+99deIIivZbm95 WvjDnIhoeaoMdqFNW7yOgSHu8ighY6Jy0x1ui3c5apLAgrMLaYLT2coZGoyGvBD1 xh722JnTooifSz3HyAXXON4RA+ZSVCNHoSp0Q+pVxEcKPLVCwb4sQJvSZaXJAKur mmQAgamDRWKvD9gmxmRQHjE7FrcRp4g3ENkV8KK6i1ZFOU64Qq9GFLPXb7a+XGL0 6Zt//8as6N98LDl0SUPgxE8U3XIuX14lt2aP6R2wHd8GLVwEmYblehe4KARP/4RY vu9gPfCc+JYdI/fHy+GDgkeuurnEQs0a2gIBvAKfvD//ktiFBmLmgxSuo6u5RG/9 rjXfzuKFUieo5IhqiuSqwwtpJfsxtFy6T4sqzdL4SXMr2R+ycuka3V0JeqlwEJIk +hhDoauB5KAAbW5R5CSt5WdEbfrrLRj+aBw8PPiaXqplB53g5pbE6ErhOkgWl0ZY q3wiH4umH61dHMcNLSuJ =v6rd -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20150511' into staging TriCore bugfixes # gpg: Signature made Mon May 11 13:26:40 2015 BST using RSA key ID 6B69CA14 # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" * remotes/bkoppelmann/tags/pull-tricore-20150511: target-tricore: fix rfe not restoring the PC target-tricore: fix rslcx restoring the upper context instead of the lower target-tricore: fix BO_OFF10_SEXT calculating the wrong offset target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of 4 target-tricore: Fix LOOP using wrong register for compare Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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				@ -2458,6 +2458,7 @@ void helper_rfe(CPUTriCoreState *env)
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    if (!cdc_zero(&(env->PSW)) && (env->PSW & MASK_PSW_CDE)) {
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					    if (!cdc_zero(&(env->PSW)) && (env->PSW & MASK_PSW_CDE)) {
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        /* raise MNG trap */
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					        /* raise MNG trap */
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    }
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					    }
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					    env->PC = env->gpr_a[11] & ~0x1;
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    /* ICR.IE = PCXI.PIE; */
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					    /* ICR.IE = PCXI.PIE; */
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    env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15);
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					    env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15);
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    /* ICR.CCPN = PCXI.PCPN; */
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					    /* ICR.CCPN = PCXI.PCPN; */
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@ -2581,7 +2582,7 @@ void helper_rslcx(CPUTriCoreState *env)
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         ((env->PCXI & MASK_PCXI_PCXO) << 6);
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					         ((env->PCXI & MASK_PCXI_PCXO) << 6);
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    /* {new_PCXI, A[11], A[10], A[11], D[8], D[9], D[10], D[11], A[12],
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					    /* {new_PCXI, A[11], A[10], A[11], D[8], D[9], D[10], D[11], A[12],
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        A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
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					        A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
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    restore_context_upper(env, ea, &new_PCXI, &env->gpr_a[11]);
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					    restore_context_lower(env, ea, &env->gpr_a[11], &new_PCXI);
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    /* M(EA, word) = FCX; */
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					    /* M(EA, word) = FCX; */
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    cpu_stl_data(env, ea, env->FCX);
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					    cpu_stl_data(env, ea, env->FCX);
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    /* M(EA, word) = FCX; */
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					    /* M(EA, word) = FCX; */
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@ -3440,7 +3440,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
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        break;
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					        break;
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    case OPCM_32_BRR_LOOP:
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					    case OPCM_32_BRR_LOOP:
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        if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
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					        if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
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            gen_loop(ctx, r1, offset * 2);
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					            gen_loop(ctx, r2, offset * 2);
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        } else {
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					        } else {
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            /* OPC2_32_BRR_LOOPU */
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					            /* OPC2_32_BRR_LOOPU */
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            gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
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					            gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
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@ -3745,10 +3745,10 @@ static void decode_slr_opc(DisasContext *ctx, int op1)
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        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
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					        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
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        break;
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					        break;
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    case OPC1_16_SLR_LD_W:
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					    case OPC1_16_SLR_LD_W:
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        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
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					        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
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        break;
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					        break;
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    case OPC1_16_SLR_LD_W_POSTINC:
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					    case OPC1_16_SLR_LD_W_POSTINC:
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        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
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					        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
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        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
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					        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
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        break;
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					        break;
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    }
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					    }
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@ -107,7 +107,7 @@
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/* BO Format */
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					/* BO Format */
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#define MASK_OP_BO_OFF10(op)   (MASK_BITS_SHIFT(op, 16, 21) + \
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					#define MASK_OP_BO_OFF10(op)   (MASK_BITS_SHIFT(op, 16, 21) + \
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                               (MASK_BITS_SHIFT(op, 28, 31) << 6))
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					                               (MASK_BITS_SHIFT(op, 28, 31) << 6))
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#define MASK_OP_BO_OFF10_SEXT(op)   (MASK_BITS_SHIFT_SEXT(op, 16, 21) + \
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					#define MASK_OP_BO_OFF10_SEXT(op)   (MASK_BITS_SHIFT(op, 16, 21) + \
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                                    (MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6))
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					                                    (MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6))
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#define MASK_OP_BO_OP2(op)     MASK_BITS_SHIFT(op, 22, 27)
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					#define MASK_OP_BO_OP2(op)     MASK_BITS_SHIFT(op, 22, 27)
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#define MASK_OP_BO_S2(op)      MASK_BITS_SHIFT(op, 12, 15)
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					#define MASK_OP_BO_S2(op)      MASK_BITS_SHIFT(op, 12, 15)
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