i.MX: Split CCM emulator in a header file and a source file
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b1d6f990229b2608bbaba24f4ff359571c0b07da.1437080501.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jean-Christophe Dubois
Peter Maydell
parent
dbeedce78e
commit
282e74c83f
@ -115,7 +115,7 @@ static void kzm_init(MachineState *machine)
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imx_serial_create(0, 0x43f90000, qdev_get_gpio_in(dev, 45));
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imx_serial_create(1, 0x43f94000, qdev_get_gpio_in(dev, 32));
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ccm = sysbus_create_simple("imx_ccm", 0x53f80000, NULL);
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ccm = sysbus_create_simple(TYPE_IMX_CCM, 0x53f80000, NULL);
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imx_timerp_create(0x53f94000, qdev_get_gpio_in(dev, 28), ccm);
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imx_timerp_create(0x53f98000, qdev_get_gpio_in(dev, 27), ccm);
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@ -2,6 +2,7 @@
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* IMX31 Clock Control Module
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*
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* Copyright (C) 2012 NICTA
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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@ -10,10 +11,7 @@
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* the CCM.
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*/
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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#include "sysemu/sysemu.h"
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#include "hw/arm/imx.h"
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#include "hw/misc/imx_ccm.h"
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#define CKIH_FREQ 26000000 /* 26MHz crystal input */
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#define CKIL_FREQ 32768 /* nominal 32khz clock */
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@ -29,30 +27,6 @@ do { printf("imx_ccm: " fmt , ##args); } while (0)
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static int imx_ccm_post_load(void *opaque, int version_id);
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#define TYPE_IMX_CCM "imx_ccm"
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#define IMX_CCM(obj) OBJECT_CHECK(IMXCCMState, (obj), TYPE_IMX_CCM)
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typedef struct IMXCCMState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t ccmr;
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uint32_t pdr0;
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uint32_t pdr1;
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uint32_t mpctl;
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uint32_t spctl;
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uint32_t cgr[3];
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uint32_t pmcr0;
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uint32_t pmcr1;
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/* Frequencies precalculated on register changes */
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uint32_t pll_refclk_freq;
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uint32_t mcu_clk_freq;
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uint32_t hsp_clk_freq;
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uint32_t ipg_clk_freq;
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} IMXCCMState;
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static const VMStateDescription vmstate_imx_ccm = {
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.name = "imx-ccm",
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.version_id = 1,
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@ -72,44 +46,6 @@ static const VMStateDescription vmstate_imx_ccm = {
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.post_load = imx_ccm_post_load,
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};
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/* CCMR */
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#define CCMR_FPME (1<<0)
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#define CCMR_MPE (1<<3)
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#define CCMR_MDS (1<<7)
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#define CCMR_FPMF (1<<26)
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#define CCMR_PRCS (3<<1)
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/* PDR0 */
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#define PDR0_MCU_PODF_SHIFT (0)
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#define PDR0_MCU_PODF_MASK (0x7)
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#define PDR0_MAX_PODF_SHIFT (3)
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#define PDR0_MAX_PODF_MASK (0x7)
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#define PDR0_IPG_PODF_SHIFT (6)
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#define PDR0_IPG_PODF_MASK (0x3)
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#define PDR0_NFC_PODF_SHIFT (8)
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#define PDR0_NFC_PODF_MASK (0x7)
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#define PDR0_HSP_PODF_SHIFT (11)
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#define PDR0_HSP_PODF_MASK (0x7)
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#define PDR0_PER_PODF_SHIFT (16)
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#define PDR0_PER_PODF_MASK (0x1f)
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#define PDR0_CSI_PODF_SHIFT (23)
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#define PDR0_CSI_PODF_MASK (0x1ff)
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#define EXTRACT(value, name) (((value) >> PDR0_##name##_PODF_SHIFT) \
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& PDR0_##name##_PODF_MASK)
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#define INSERT(value, name) (((value) & PDR0_##name##_PODF_MASK) << \
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PDR0_##name##_PODF_SHIFT)
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/* PLL control registers */
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#define PD(v) (((v) >> 26) & 0xf)
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#define MFD(v) (((v) >> 16) & 0x3ff)
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#define MFI(v) (((v) >> 10) & 0xf);
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#define MFN(v) ((v) & 0x3ff)
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#define PLL_PD(x) (((x) & 0xf) << 26)
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#define PLL_MFD(x) (((x) & 0x3ff) << 16)
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#define PLL_MFI(x) (((x) & 0xf) << 10)
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#define PLL_MFN(x) (((x) & 0x3ff) << 0)
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uint32_t imx_clock_frequency(DeviceState *dev, IMXClk clock)
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{
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IMXCCMState *s = IMX_CCM(dev);
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@ -286,7 +222,7 @@ static int imx_ccm_init(SysBusDevice *dev)
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IMXCCMState *s = IMX_CCM(dev);
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memory_region_init_io(&s->iomem, OBJECT(dev), &imx_ccm_ops, s,
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"imx_ccm", 0x1000);
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TYPE_IMX_CCM, 0x1000);
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sysbus_init_mmio(dev, &s->iomem);
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return 0;
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@ -11,18 +11,10 @@
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#ifndef IMX_H
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#define IMX_H
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#include "hw/misc/imx_ccm.h"
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void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq);
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typedef enum {
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NOCLK,
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MCU,
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HSP,
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IPG,
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CLK_32k
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} IMXClk;
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uint32_t imx_clock_frequency(DeviceState *s, IMXClk clock);
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void imx_timerp_create(const hwaddr addr,
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qemu_irq irq,
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DeviceState *ccm);
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91
include/hw/misc/imx_ccm.h
Normal file
91
include/hw/misc/imx_ccm.h
Normal file
@ -0,0 +1,91 @@
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/*
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* IMX31 Clock Control Module
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*
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* Copyright (C) 2012 NICTA
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef IMX_CCM_H
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#define IMX_CCM_H
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#include "hw/sysbus.h"
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/* CCMR */
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#define CCMR_FPME (1<<0)
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#define CCMR_MPE (1<<3)
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#define CCMR_MDS (1<<7)
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#define CCMR_FPMF (1<<26)
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#define CCMR_PRCS (3<<1)
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/* PDR0 */
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#define PDR0_MCU_PODF_SHIFT (0)
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#define PDR0_MCU_PODF_MASK (0x7)
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#define PDR0_MAX_PODF_SHIFT (3)
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#define PDR0_MAX_PODF_MASK (0x7)
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#define PDR0_IPG_PODF_SHIFT (6)
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#define PDR0_IPG_PODF_MASK (0x3)
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#define PDR0_NFC_PODF_SHIFT (8)
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#define PDR0_NFC_PODF_MASK (0x7)
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#define PDR0_HSP_PODF_SHIFT (11)
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#define PDR0_HSP_PODF_MASK (0x7)
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#define PDR0_PER_PODF_SHIFT (16)
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#define PDR0_PER_PODF_MASK (0x1f)
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#define PDR0_CSI_PODF_SHIFT (23)
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#define PDR0_CSI_PODF_MASK (0x1ff)
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#define EXTRACT(value, name) (((value) >> PDR0_##name##_PODF_SHIFT) \
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& PDR0_##name##_PODF_MASK)
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#define INSERT(value, name) (((value) & PDR0_##name##_PODF_MASK) << \
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PDR0_##name##_PODF_SHIFT)
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/* PLL control registers */
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#define PD(v) (((v) >> 26) & 0xf)
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#define MFD(v) (((v) >> 16) & 0x3ff)
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#define MFI(v) (((v) >> 10) & 0xf);
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#define MFN(v) ((v) & 0x3ff)
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#define PLL_PD(x) (((x) & 0xf) << 26)
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#define PLL_MFD(x) (((x) & 0x3ff) << 16)
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#define PLL_MFI(x) (((x) & 0xf) << 10)
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#define PLL_MFN(x) (((x) & 0x3ff) << 0)
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#define TYPE_IMX_CCM "imx.ccm"
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#define IMX_CCM(obj) OBJECT_CHECK(IMXCCMState, (obj), TYPE_IMX_CCM)
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typedef struct IMXCCMState {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion iomem;
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uint32_t ccmr;
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uint32_t pdr0;
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uint32_t pdr1;
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uint32_t mpctl;
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uint32_t spctl;
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uint32_t cgr[3];
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uint32_t pmcr0;
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uint32_t pmcr1;
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/* Frequencies precalculated on register changes */
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uint32_t pll_refclk_freq;
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uint32_t mcu_clk_freq;
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uint32_t hsp_clk_freq;
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uint32_t ipg_clk_freq;
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} IMXCCMState;
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typedef enum {
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NOCLK,
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MCU,
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HSP,
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IPG,
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CLK_32k
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} IMXClk;
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uint32_t imx_clock_frequency(DeviceState *s, IMXClk clock);
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#endif /* IMX_CCM_H */
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